CH705950B1 - Variable pulse width signal generator. - Google Patents

Abstract

The present invention relates to a signal generator circuit (1) powered by a supply voltage and comprising switching means (2) comprising a first input to which is connected a DC input signal (E1) whose amplitude is defined, a second input to which is connected a clock signal (S CLK ) whose duty cycle is defined and a third input for the reset, and providing at output, an output signal (S1, S out ) whose the duty cycle is that of the clock signal (S CLK ) and the amplitude of which is that of the input signal (E1), characterized in that said circuit further comprises regulation means (3) arranged to compare the output signal (S1, S out ) with a setpoint signal (E3) representative of the desired duty cycle and to supply a control signal (S4) connected to the third input of the switching means (2) so as to activate the reset to zero to change the duty cycle of the signal from output (S1, S out ).

Description

The present invention relates to a signal generator circuit powered by a supply voltage and comprising switching means comprising a first input to which is connected a DC input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined and a third input for resetting, and providing at output, an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal.

TECHNOLOGICAL BACKGROUND

Signal generators are known comprising an AC analog comparator to which is connected a triangular signal Vi and a continuous input signal Ve having as amplitude a reference voltage as shown in FIG. 1. During operation of the comparator CA, the input signal and the triangular signal are compared to provide an output signal. This is in the form of a rectangular signal. Indeed, the output signal Vs is a continuous signal which switches when the voltage of the triangular signal reaches the voltage value of the input signal. As a result, the output signal has a regular square wave shape. This square-wave signal then has a pulse width, that is to say a ratio between the high state or the low state of the signal and the period. This ratio corresponds, in the case of the assembly described, to the ratio between the reference voltage and the amplitude of the triangular signal.

A disadvantage of this assembly is that it requires the AC comparator to be fast because the latter must switch at each time interval and the switching must be fast otherwise the output signal will be affected.

[0004] Furthermore, the adjustment of the duty cycle α is done by modifying the value of the reference voltage. However, the amplitude of the triangular signal must be linked to the voltage value of the reference signal. If such is not the case, then an error occurs at the level of the duty cycle and the latter is not the desired one.

[0005] It is also known to use a clock having a frequency N times greater than the desired frequency for the output signal. This ratio of N is the discrete step number of the duty cycle change. For this, a high-frequency synchronous counter and a digital comparator at the counter output are generally used. The desired duty cycle is the comparison value of the comparator.

[0006] Nevertheless, this technique is energy-intensive, especially if the frequency increases and if the resolution, that is to say the number of steps, increases.

SUMMARY OF THE INVENTION

The invention relates to a pulse-width modulation signal generator which is simple, reliable and energy-efficient.

To this end, the invention relates to a signal generator circuit intended to be supplied by a supply voltage and comprising switching means comprising a first input intended to receive a DC input signal whose voltage level is defined, a second input intended to receive a clock signal whose frequency and duty cycle are defined and a third input for the reset, and providing at the output an output signal whose frequency is that of the signal d clock and whose amplitude is that of the input signal, characterized in that said circuit further comprises regulation means arranged to compare the output signal with a reference signal representative of a desired duty cycle and to provide a control signal connected to the third input of the switching means so as to activate the reset to modify the duty cycle of the output signal. A first advantage of the present invention is that it allows simple adjustment of the duty cycle. Indeed, only the setpoint signal is modified, that is to say only the voltage level of the setpoint signal is increased or lowered to modify the duty cycle. It is therefore easy to provide a continuous signal whose amplitude can be varied, unlike a triangular signal which is more difficult to generate.

A second advantage is that the generator according to the present invention consumes little energy compared to the generator according to the prior art because it does not use high-frequency components. However, these high-frequency components have the disadvantage of being greedy in terms of electrical energy. In addition, since there is no need for rapidly switched front components, costs are minimized.

[0010] Advantageous embodiments of this sensor are the subject of the dependent claims.

In a first advantageous embodiment, the regulation means comprise a delay circuit connected to the output signal of the switching means and configured to supply the control signal resetting the output signal of the generator circuit when the high state of said output signal reaches the desired duty cycle,

In a second advantageous embodiment, the delay circuit comprises a first zone comprising a first P-type transistor having its source connected to the supply voltage and its drain connected to the drain of a first N-type transistor , the source of this first N-type transistor being connected to the drain of a second N-type transistor having its source connected to ground, the input signal being connected to the gate of the first P-type transistor and to the gate of the first N-type transistor, this first zone being connected to a second zone comprising a second P-type transistor and a third N-type transistor, the second P-type transistor having its source connected to the supply voltage and its drain connected to the drain of the third N-type transistor which has its source connected to circuit ground, the gates of the second P-type transistor and the third N-type transistor are both connected to the connection point of the d rains of the first P-type and N-type transistors, the output of the delay circuit being the connection point of the drains of the second P-type transistor and of the third N-type transistor, the first and second zones being connected by capacitors connected in parallel to ground.

In another advantageous embodiment, the regulation means further comprise a setpoint assembly comparing the output signal from the switching means to a setpoint signal representative of the desired duty cycle in order to generate an adjustment signal sent to the gate of the second N-type transistor of the delay circuit in order to delay or advance the resetting of the output signal of the generator circuit as a function of the setpoint signal representative of the desired duty cycle.

In another advantageous embodiment, the setpoint assembly comprises a filter circuit whose input is connected to the output signal of the switching means and used to average said output signal, and a comparator circuit whose inputs are, the output of the filtering circuit and the reference signal representative of the desired duty cycle, said comparator circuit supplying said adjustment signal including the voltage level, representative of the difference between the output of the filtering circuit and the reference signal, makes it possible to modify the current flowing in the second N-type transistor of the delay circuit.

[0015] In another advantageous embodiment, the filter circuit is a low-pass filter.

In another advantageous embodiment, the tilting means are a D flip-flop.

BRIEF DESCRIPTION OF FIGURES

The aims, advantages and characteristics of the signal generator circuit according to the present invention will appear more clearly in the following detailed description of at least one embodiment of the invention given solely by way of non-limiting example and illustrated by the attached drawings on which: FIG. 1 schematically represents a generator circuit according to the prior art; FIG. 2 schematically represents a block diagram of a generator circuit according to the invention; and FIG. 3 schematically represents the electrical diagram of the generator circuit according to the invention.

DETAILED DESCRIPTION

Figure 2 shows the pulse width modulation signal generator 1 according to the present invention. This generator 1 comprises switching means 2 comprising three inputs and one output. A first input CLK is connected to a clock signal Sclk. This signal is preferably a square signal. The second input is connected to a DC input signal E1 whose voltage level is the supply voltage Vdd. This input signal is used in order to reset the output signal to Vdd (logic level 1) at the time of the active edge of the clock signal CLK, this use will be explained later. The third input is a reset input to which a reset or reset RESET signal can be sent, this signal defines the time that the output signal S1 passes to the voltage level Vdd (logic level 1) and thus defined the duty cycle α of the output signal S1.

The output signal S1 of the switching means 2 is also the final output signal Sout of the generator. This output is also connected to a regulation loop 3. This regulation loop 3 comprises a filter circuit 4. The output signal S1 is connected to an input E2 of the filter circuit 4, the latter is used to average the signal S1 . The output of this filter circuit 4 provides a signal S2. This signal S2 is a DC voltage equal to the average of the output signal S1 and is connected to the negative input of an operational amplifier 6 also forming part of the regulation loop 3. The positive input of said operational amplifier 6 is connected to a continuous signal Vref whose voltage level can be defined by the user. The operational amplifier 6 provides, at output, a DC signal S3 whose voltage level is representative of the difference between the two signals. This output of the amplifier 6 is connected to a delay circuit 8 comprising an input E4 to which the output signal S1 of the switching means 2 is connected. This delay circuit 8, integrated in the regulation loop 3, is used so that the output signal S4 of this delay circuit 8 is a control signal passing through an inverter circuit 10 to then be connected to the RESET input of the switching means 2. This output signal S4 therefore acts as a signal reset

More specifically, the switching means 2 are a D flip-flop. this D flip-flop 2 has, as first input, a clock signal Sclk, preferably a square wave signal whose duty cycle α is 50%, and as second input , a continuous input signal E1 having as voltage level a reference voltage value. The output of this D flip-flop 2 supplies a square output signal S1 whose voltage level is that of the input signal E1. This output signal S1 of the D flip-flop 2 is the final output signal Sout of the generator 1.

Advantageously according to the invention, this final output signal Sout is controlled via regulation means 3 in the form of a regulation loop described in detail below.

The signal S1 is sent to a setpoint assembly 7 comprising a filter circuit 4. This filter circuit 4 is a low-pass filter, typically an RC circuit. A low-pass filter of the RLC or Sallen-Key type can also be envisaged. This filter circuit 4 is used to average the signal S1. The result of the filtering of the signal S1, which is a crenellated signal, is a continuous signal S2. The components of this filter circuit 4, that is to say the resistor R and the capacitor C, are calculated so that the voltage level obtained is proportional to the duty cycle. For example, for a signal S1 with a duty cycle of 50% and a voltage level Vdd, a continuous signal S2 would be obtained whose voltage level is Vdd/2. Similarly, for a signal S1 with a duty cycle of 25% and a voltage level Vdd, a continuous signal S2 would be obtained whose voltage level is Vdd/4.

This signal S2 is then connected to the negative input of the operational amplifier 6 which is also part of the instruction set 7. At the positive input of this operational amplifier 6, is connected to a signal E3. This signal E3 is a continuous voltage level signal Vref. The signal S2 and the signal E3 are compared with each other to supply at the output of said operational amplifier 6 a signal S3 called the reference signal. This setpoint signal S3 is connected to one of the inputs of the delay circuit 8. The latter also has as input the signal S1 coming out of the switching means 2.

The delay circuit 8 comprises two distinct zones. A first zone comprises three switching means 9, here MOSFET transistors. More particularly, these three switching means 9 are two N-type transistors N1 and N2 and a P-type transistor P1. These three transistors are mounted so that the first P-type transistor P1 at its source connected to the voltage of supply Vdd and its drain connected to the drain of a first N-type transistor N1. The source of this first N-type transistor N1 is connected to the drain of a second N-type transistor N2. The latter sees its source connected to the mass Vss of the delay circuit 8. The signal S1 is connected at the same time to the gate of the first P-type transistor P1 and to the gate of the first N-type transistor N1, the gate of the second N-type transistor N2 being connected to the signal S3.

The connection point between the first P-type transistor P1 and the first N-type transistor N1 is used to connect this first zone of the delay circuit to the second zone of the delay circuit. This second zone comprises two switching means 9 in the form of two transistors: a second P-type transistor P2 and a third N-type transistor N3. The second P-type transistor P2 has its source connected to the voltage of supply Vdd and its drain connected to the source of the third N-type transistor N3. The latter has its drain connected to ground Vss of circuit 8. The gates of transistors P2 and N3 are both connected to the connection point between the transistors P1 and N1.

Between these two areas, at least one decoupling capacitor C1 is arranged in parallel so that the input of capacitor C1 is connected to the connection point between transistors P1 and N1 and to the gates of transistors P2 and N3 while the output of capacitor C1 is connected to ground Vss. Of course, it is possible to have several capacitors connected in parallel to

The output of delay circuit 8 is the connection point between transistors P2 and N3. The signal at the output of the delay circuit 8 is the control signal S4 which is then inverted by an inverter circuit 10. Once this setpoint signal S4 has been inverted, it is connected to the RESET input of the D flip-flop 2. This connection allows control signal S4 to act directly on signal S1 to modify it.

During the operation of this signal generator 1, the duty cycle of the output signal S1, Sout is modified and regulated by the regulation loop 3. This regulation loop 3 comprises the delay circuit 8, the filter circuit 4 and operational amplifier 6.

Indeed, the filter circuit 4 and the operational amplifier 6, forming the setpoint 7, are used to compare the voltage level of the signal S2, proportional to the supply voltage Vdd and representative of the duty cycle α of signal S1, with voltage level Vref signal E3 and supplying a signal controlling delay circuit 8. Delay circuit 8 operates as explained below.

The signal S1 is applied to the input E4 of the delay circuit 8, that is to say applied to the gates of the transistors N1 and P1.

At startup, the signal S1, which is a square signal, is in the low state or logic level 0, that is to say with a voltage level of zero volts. The first N-type transistor N1 is in the off state, that is to say off, while the first P-type transistor P1 is in the on state. The supply voltage Vdd passes through the first P-type transistor P1 and is transmitted to the second zone. This signal is called intermediate signal Sint. This signal Sint, of logic state 1, is applied to the gates of transistors P2 and N3. In this case, the second P-type transistor P2 is in the off state and the third N-type transistor N3 is in the on state. Consequently, it is the mass Vss, that is to say the zero volt point or the logic state 0, which is connected to the output causing the control signal S4 of the delay circuit 8 to pass to the state low. Passing through the inverter 10, this control signal S4 is inverted and goes to the high state before being sent to the RESET input of the D flip-flop 2. However, this D flip-flop 2 is configured so that the function RESET is active in the low state, that is to say when a signal in the low state is sent to the RESET input of the switching means 2. As the inverted signal S4 is in the high state, the reset function is not activated.

[0032] When signal S1 goes high, transistor P1 ceases to be on and goes off, whereas, on the contrary, transistor N1 goes from off to on. Assuming that transistor N2 is also on, the role of this transistor N2 will be explained later, it is the ground potential Vss, that is to say the logic state 0, which is transmitted to the second zone of the delay circuit 8. However, the decoupling capacitor C1 is used so that the passage from the high state to the low state takes place gradually, that is to say with a time constant.

As long as the signal Sint has not crossed the switching voltage threshold of the transistors N3 and P2, the transistor P2 remains off and the transistor N3 remains on, the control signal S4 therefore does not change. However, when the voltage level of the signal Sint drops below the switching voltage threshold of the transistors N3 and P2, the switching of the transistors P2 and N3 takes place. Transistor P2 goes from off state to on state and transistor N3 goes from on state to off state. The control signal S4 thus passes from the low state to the high state. By action of the inverter 10, the signal sent to the RESET input of the switching means 2 is a signal in the low state. This low state activates the reset function of flip-flop 2 so that signal S1 switches instantaneously from the high state to the low state.

The consequence is rapid switching of transistor P1 which becomes on again so that signal Sint returns to the high state. When the voltage level of signal Sint exceeds the voltage threshold of transistors P2 and N3, the latter switch so that transistor P2 becomes blocked and transistor N3 becomes conductive. The control signal S4 then passes to the low state and, being inverted, it passes to the high state when it enters the RESET input of the D flip-flop 2. This high state of the signal applied to the RESET input of the flip-flop D 2 results in a stoppage of the reset function.

During the operation of this generator 1, the adjustment of the duty cycle α is carried out by the signal S3. Indeed, this signal S3 corresponds to the comparison of the signal S2, which is the filtered signal S1, with the signal E3 which is a reference signal whose voltage level is a reference voltage proportional to the supply voltage, such as the S2 signal by the way.

The operational amplifier is designed to supply, at output, the signal S3 whose voltage level is a voltage representative of the comparison between the signal S2 and the signal E3. The voltage level of signal S3 increases if signal S2 is higher than signal E3 but it decreases if signal S2 is lower than signal E3. This signal S3 is then sent to the gate of transistor N2 in order to adjust the duty cycle α.

Indeed, the principle used is that the comparison between the signal S2 and the signal E3 makes it possible to provide, at the output of the operational amplifier 6, a signal representative of this comparison acting on the second N-type transistor N2. The S3 signal is used to act on the channel of the second N-type transistor N2 so that this channel opens more or less depending on the voltage level of the S3 signal, i.e. according to the result of the comparison between signal S2 and signal E3. If signal S2 is greater than signal E3, the voltage level of signal S3 increases and, consequently, transistor N2 sees its channel open more significantly. This allows more current to flow. However, this greater opening of the channel is perceptible when the first N-type transistor N1 is also on, that is to say when the signal S1 goes high. This additional current arrival has an influence on the signal Sint since by passing more current, the discharge of the capacitor C1 is modified. More precisely, if more current passes through the second N-type transistor N2, the discharge of the capacitor C1 is faster. The signal Sint therefore crosses the voltage threshold of the transistors P2 and N3 more quickly. As the voltage threshold is crossed more quickly, transistors P2 and N3 also switch more quickly and the reset function is activated more quickly. This faster activation has the effect of reducing the duty cycle α of the output signal Sout. This result is the desired goal because if the signal S2 is greater than the signal E3, it is because the duty cycle α of the signal S1 is greater than the requested duty cycle.

On the contrary, if the duty cycle must be increased, the signal S2 is lower than the signal E3. The output signal S3 of the operational amplifier 6 will have a voltage level representative of this lower comparison. This lower voltage level results in a lower opening of the channel of transistor N2 and therefore a lower amount of current flowing through said transistor N2. The discharge of capacitor C1 is slowed down. The signal Sint therefore crosses the switching voltage threshold of the transistors P2 and N3 more slowly. As the switching voltage threshold is crossed more slowly, the transistors P2 and N3 also switch more slowly and the reset function is activated more slowly. This slower activation has the effect of increasing the duty cycle α, that is to say of increasing the high state of the signal S1 with respect to the low state. This is the desired goal because if the signal S2 is less than the signal E3, it means that the duty cycle α of the signal S1 is less important than the duty cycle α requested.

This comparison of the signal S2 and the signal E3 is continuous so that the purpose of this regulation loop is that the signal S2 and the signal E3 are identical in order to provide a signal S3 freezing the opening of the channel of the second transistor N-type N2.

It is therefore concluded that the delay circuit 8 is used to provide, at a specific time, a control signal S4 activating the reset. The assembly comprising the filter circuit 4 and the operational amplifier 6 is arranged to provide a setpoint signal S3 which modifies the precise moment when the delay circuit 8 sends the control signal S4 activating the reset. The moment at which the control signal must reset the D flip-flop 2 makes it possible to define the duty cycle α and is adjustable according to the difference between signal S2 and signal E3.

It will be understood that various modifications and / or improvements and / or combinations obvious to those skilled in the art can be made to the different embodiments of the invention described above without departing from the scope of the invention defined by the appended claims.

[0042] Provision may for example be made for the transistors of the delay circuit 8 to be bipolar or JFET type transistors.

Claims (7)

1. Signal generator circuit (1) intended to be powered by a supply voltage and comprising switching means (2) comprising a first input intended to receive a DC input signal (E1) whose voltage level is defined, a second input intended to receive a clock signal (Sclk) whose frequency and duty cycle are defined, and a third input for resetting, and providing at output, an output signal (S1, Sout) whose frequency is that of the clock signal and whose amplitude is that of the input signal, characterized in that the said circuit (1) further comprises regulation means (3) arranged to compare the output signal with a setpoint signal (E3) representative of a desired duty cycle and to supply a control signal (S4) connected to the third input of the switching means so as to activate the reset to modify the duty cycle of the output signal (S1). 2. Signal generator circuit according to claim 1, characterized in that the regulation means (3) comprise a delay circuit (8) connected to the output signal (S1) of the switching means (2) and configured to supply the control signal (S4) resetting the output signal (S1, Sout) of the generator circuit to zero when a high state of said output signal (S1, Sout) reaches the desired duty cycle. 3. Signal generator circuit according to claim 2, characterized in that the delay circuit (8) comprises a first zone comprising a first P-type transistor (P1) having its source connected to the supply voltage (Vdd) and its drain connected to the drain of a first N-type transistor (N1), the source of this first N-type transistor being connected to the drain of a second N-type transistor (N2) having its source connected to ground, the output signal (S1) being connected to the gate of the first P-type transistor and to the gate of the first N-type transistor, this first zone being connected to a second zone comprising a second P-type transistor and a third N, the second P-type transistor having its source connected to the supply voltage (Vdd) and its drain connected to the drain of the third N-type transistor which has its source connected to the ground (Vss) of the circuit, the gates of the second P-type transistor and the third d-transistor e N-type are both connected to the connection point of the drains of the first P-type and N-type transistors, the output (S4) of the delay circuit (8) being the connection point of the drains of the second P-type transistor and the third N-type transistor, the first and second zones being connected by a capacitor (C1) connected in parallel with the first and second zones. 4. Signal generator circuit according to claim 3, characterized in that the regulation means (3) further comprise a setpoint assembly (7) comparing the output signal (S1) of the switching means (2) to a signal of setpoint representative of the desired duty cycle (E3) in order to generate an adjustment signal (S3) sent to the gate of the second N-type transistor (N2) of the delay circuit (8) in order to delay or advance the reset of the output signal (S1) of the generator circuit (1) as a function of the reference signal representative of the desired duty cycle (E3). 5. Signal generator circuit according to claim 4, characterized in that the setpoint assembly (7) comprises a filter circuit (4) whose input is connected to the output signal (S1) of the switching means (2) and used to average said output signal (S1) of the switching means (2), and a comparator circuit (6) whose inputs are the output of the filter circuit (4) and the reference signal representative of the desired duty cycle (E3), said comparator circuit (6) supplying said adjustment signal (S3) whose voltage level, representative of the difference between the output of the filtering circuit and the setpoint signal (E3), makes it possible to modify the current flowing in the second N-type transistor (N2) of the delay circuit (8), 6. Signal generator circuit according to claim 5, characterized in that the filter circuit (4) is a low-pass filter. 7. Signal generator circuit according to claim 1, characterized in that the switching means (2) are a D flip-flop.