CH689217A5 - Piggy back chip mounting technique - Google Patents

Piggy back chip mounting technique Download PDF

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Publication number
CH689217A5
CH689217A5 CH01169/95A CH116995A CH689217A5 CH 689217 A5 CH689217 A5 CH 689217A5 CH 01169/95 A CH01169/95 A CH 01169/95A CH 116995 A CH116995 A CH 116995A CH 689217 A5 CH689217 A5 CH 689217A5
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Switzerland
Prior art keywords
chip
chips
active face
fixing
interconnection support
Prior art date
Application number
CH01169/95A
Other languages
French (fr)
Inventor
Clot Philippe
Original Assignee
Valtronic S A
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Publication date
Application filed by Valtronic S A filed Critical Valtronic S A
Priority to CH01169/95A priority Critical patent/CH689217A5/en
Publication of CH689217A5 publication Critical patent/CH689217A5/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/818—Bonding techniques
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    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

NOVELTY - The method used, fixing the first chip (2) active face onto the interconnection support(1) and fixing the non-active face of the second chip (3) to the first chip gives a greater degree of miniaturisation than previously available. DETAILED DESCRIPTION - DETAILED DESCRIPTION

Description

       

  
 



  La présente invention concerne un procédé de montage de deux puces électroniques superposées sur un support d'interconnexion. 



  A l'heure où les instruments et appareils électroniques deviennent de plus en plus performants, même sous des volumes de plus en plus réduits, et utilisent des circuits intégrés de plus en plus complexes, il est évident que les techniques de montage de ces derniers doivent suivre une évolution parallèle. Ainsi, dans de nombreuses applications, comme les calculatrices de poche, les téléphones portables, etc., il devient difficile d'utiliser des circuits intégrés en bottier classique. Une solution connue consiste à reporter directement les puces nues sur le support d'interconnexion (circuit imprimé, circuit couche épaisse ou équivalent).

   Les connexions entre les puces et le circuit imprimé peuvent être assurées par fil fin (bonding) ou par thermocompression de protubérances conductrices (bumps) préalablement déposées sur les puces directement sur le support d'interconnexion (TAB, Flip Chip). Récemment, il est également apparu des techniques de montage puce sur puce qui permettent une miniaturisation encore plus grande, mais qui sont souvent délicates à mettre en Öuvre. 



  La présente invention concerne un procédé particulièrement performant et fiable de montage de deux puces superposées sur un support d'interconnexion possédant des bornes de contact, chacune desdites puces comportant une face active munie de plages de contact et une face non active. Ce procédé est caractérisé par le fait qu'il consiste à fixer la face active de la première puce sur le support, puis à fixer la face non active de la deuxième puce sur la face non active de la première. 



  La fig. 1 représente à titre d'exemple un montage comportant deux puces assemblées selon le procédé faisant l'objet de l'invention. 



  Ce montage comporte un support d'interconnexion 1, par exemple un circuit imprimé multicouches. Dans cet exemple, les puces de circuits intégrés 2 et 3 sont montées sur la face supérieure du circuit imprimé 1. D'autres composants 4, par exemple des composants de type CMS, peuvent être montés sur l'une ou l'autre face du support 1. Celui-ci peut également comporter des moyens d'interconnexion permettant de le monter sur une carte mère, par exemple des protubérances (bumps) en étain 5 permettant son soudage par reflow. 



  La première puce de circuit intégré 2 comporte des protubérances en or 6 formées sur ses plages de contact (pads), comme cela se pratique dans la technique de TAB. Ces protubérances viennent en regard de bornes de contact correspondantes 7 du circuit imprimé 1. La puce 2 est donc montée de telle façon que sa face active soit tournée du côté du circuit imprimé 1. 



  Ce montage s'effectue de la manière suivante. 
 
   1. Une couche de colle anisotropique 8 est déposée à la surface du circuit imprimé 1. Cette couche peut être déposée par sérigraphie de manière à épargner les bornes de contact 7. 
   2. La puce 2 est ensuite déposée de telle manière que les protubérances 6 viennent en regard des bornes de contact 7. La connexion peut être assurée par thermocom pression ou toute autre méthode connue. 
   3. La rigidité mécanique de l'ensemble est assurée par séchage de la couche de colle 8. 
 



  Avec cette manière de faire, la face non active de la puce 2 est donc tournée vers l'extérieur. Il est ainsi possible d'utiliser cette surface pour fixer la  deuxième puce 3. Il suffit de déposer une couche de colle 9 sur cette surface, puis d'y déposer la puce 3, sa face active tournée vers l'extérieur. La puce 3 peut alors être connectée par bonding ultrasonique avec des fils minces 10 reliant ses plages de contact à des zones métallisées correspondantes 11 du circuit imprimé 1. Le tout peut être finalement recouvert d'une résine de protection 12, de type époxy noire, offrant les caractéristiques de dureté et d'opacité nécessaires à ce genre de sous-ensemble électronique. 



  Ce procédé de montage puce sur puce comportant trois couches, soit une couche "circuit imprimé - zone active de la première puce" permettant l'interconnexion entre ces deux éléments, une couche neutre où les deux puces sont collées dos à dos, et une troisième couche représentée par la zone active de la deuxième puce permettant la connexion de cette dernière au circuit imprimé par bonding, présente de nombreux avantages par rapport aux procédés connus. 
 
   a. Il est possible de monter, connecter, tester et protéger complètement la première puce avant de monter la deuxième. 
   b. De ce fait, lorsqu'on monte la deuxième puce au dos de la première, la surface active de cette dernière est entièrement cachée et ne peut donc pas être détériorée par une fausse manÖuvre. On peut même, dans certains cas, décoller la deuxième puce et la remplacer si nécessaire. 
   c.

   La surface de la deuxième puce peut être égale à la surface de la première puce. 
 



  Le procédé selon l'invention permet donc une miniaturisation extrême tout en garantissant une fiabilité maximum. 



  
 



  The present invention relates to a method of mounting two electronic chips superimposed on an interconnection support.



  At a time when electronic instruments and devices are becoming more and more efficient, even under increasingly reduced volumes, and use increasingly complex integrated circuits, it is obvious that the mounting techniques of these latter must follow a parallel evolution. Thus, in many applications, such as pocket calculators, mobile phones, etc., it becomes difficult to use integrated circuits in conventional shoemaker. A known solution consists in directly transferring the bare chips onto the interconnection support (printed circuit, thick film circuit or equivalent).

   The connections between the chips and the printed circuit can be ensured by fine wire (bonding) or by thermocompression of conductive protrusions (bumps) previously deposited on the chips directly on the interconnection support (TAB, Flip Chip). Recently, chip-on-chip editing techniques have also appeared which allow even greater miniaturization, but which are often difficult to implement.



  The present invention relates to a particularly efficient and reliable method of mounting two chips superimposed on an interconnection support having contact terminals, each of said chips comprising an active face provided with contact pads and a non-active face. This method is characterized by the fact that it consists in fixing the active face of the first chip on the support, then in fixing the non-active face of the second chip on the non-active face of the first.



  Fig. 1 shows by way of example an assembly comprising two chips assembled according to the process forming the subject of the invention.



  This assembly comprises an interconnection support 1, for example a multilayer printed circuit. In this example, the integrated circuit chips 2 and 3 are mounted on the upper face of the printed circuit 1. Other components 4, for example SMD type components, can be mounted on either side of the support 1. This may also include interconnection means making it possible to mount it on a motherboard, for example tin bumps 5 allowing its reflow soldering.



  The first integrated circuit chip 2 has gold protuberances 6 formed on its contact pads (pads), as is done in the TAB technique. These protrusions come opposite corresponding contact terminals 7 of the printed circuit 1. The chip 2 is therefore mounted in such a way that its active face is turned towards the side of the printed circuit 1.



  This assembly is carried out as follows.
 
   1. A layer of anisotropic adhesive 8 is deposited on the surface of the printed circuit 1. This layer can be deposited by screen printing so as to spare the contact terminals 7.
   2. The chip 2 is then deposited in such a way that the protrusions 6 come opposite the contact terminals 7. The connection can be ensured by thermocompression or any other known method.
   3. The mechanical rigidity of the assembly is ensured by drying the adhesive layer 8.
 



  With this way of doing things, the non-active face of the chip 2 is therefore turned outwards. It is thus possible to use this surface to fix the second chip 3. It suffices to deposit a layer of adhesive 9 on this surface, then to deposit the chip 3 there, its active face facing outward. The chip 3 can then be connected by ultrasonic bonding with thin wires 10 connecting its contact pads to corresponding metallized areas 11 of the printed circuit 1. The whole can finally be covered with a protective resin 12, of black epoxy type, offering the hardness and opacity characteristics necessary for this kind of electronic sub-assembly.



  This chip-on-chip mounting process comprising three layers, ie a “printed circuit - active area of the first chip” layer allowing the interconnection between these two elements, a neutral layer where the two chips are bonded back to back, and a third layer represented by the active area of the second chip allowing the connection of the latter to the printed circuit by bonding, has many advantages compared to known methods.
 
   at. It is possible to mount, connect, test and completely protect the first chip before mounting the second.
   b. Therefore, when the second chip is mounted on the back of the first, the active surface of the latter is completely hidden and therefore cannot be damaged by a false operation. We can even, in some cases, take off the second chip and replace it if necessary.
   vs.

   The area of the second chip can be equal to the area of the first chip.
 



  The method according to the invention therefore allows extreme miniaturization while guaranteeing maximum reliability.

Claims (8)

1. Procédé de montage de deux puces électroniques (2, 3) superposées sur un support d'interconnexion (1) possédant des bornes de contact (7), chacune desdites puces comportant une face active munie de plages de contact et une face non active, caractérisé par le fait qu'il consiste à fixer la face active de la première puce (2) sur ledit support, puis à fixer la face non active de la deuxième puce (3) sur la face non active de la première.     1. Method for mounting two electronic chips (2, 3) superimposed on an interconnection support (1) having contact terminals (7), each of said chips comprising an active face provided with contact pads and a non-active face , characterized in that it consists in fixing the active face of the first chip (2) on said support, then in fixing the inactive face of the second chip (3) on the inactive face of the first. 2. Procédé de montage selon la revendication 1, caractérisé par le fait que la première puce (2) est préalablement dotée de protubérances conductrices (6) agencées de manière à assurer la connexion électrique entre les plages de contact de ladite puce et les bornes de contact (7) dudit support d'interconnexion. 2. An assembly method according to claim 1, characterized in that the first chip (2) is previously provided with conductive protrusions (6) arranged so as to ensure the electrical connection between the contact pads of said chip and the terminals of contact (7) of said interconnection support. 3. 3. Procédé de montage selon la revendication 2, caractérisé par le fait que lesdites protubérances conductrices (6) sont en or.  Mounting method according to claim 2, characterized in that said conductive projections (6) are made of gold. 4. Procédé de montage selon l'une des revendications 2 et 3, caractérisé par le fait que la connexion entre les protubérances conductrices (6) de la première puce (2) et les bornes de contact (7) du support d'interconnexion (1) est obtenue par thermocompression. 4. Mounting method according to one of claims 2 and 3, characterized in that the connection between the conductive protrusions (6) of the first chip (2) and the contact terminals (7) of the interconnection support ( 1) is obtained by thermocompression. 5. Procédé de montage selon l'une des revendications précédentes, caractérisé par le fait que la fixation de la première puce (2) sur le support d'interconnexion (1) est obtenue par dépôt d'une couche de colle anisotropique (8). 5. mounting method according to one of the preceding claims, characterized in that the fixing of the first chip (2) on the interconnection support (1) is obtained by depositing a layer of anisotropic adhesive (8) . 6. Procédé de montage selon l'une des revendications précédentes, caractérisé par le fait que les deux puces sont fixées dos à dos au moyen d'une couche de colle (9). 6. Assembly method according to one of the preceding claims, characterized in that the two chips are fixed back to back by means of a layer of adhesive (9). 7. 7. Procédé de montage selon l'une des revendications précédentes, caractérisé par le fait que les connexions entre les plages de contact de la deuxième puce (3) et des zones métallisées correspondantes (11) du support d'interconnexion sont assurées par des fils conducteurs (10).  Mounting method according to one of the preceding claims, characterized in that the connections between the contact pads of the second chip (3) and the corresponding metallized areas (11) of the interconnection support are provided by conductive wires ( 10). 8. Procédé de montage selon l'une des revendications précédentes, caractérisé par le fait qu'une goutte de résine de protection (12) est finalement appliquée sur l'assemblage réalisé. 8. Mounting method according to one of the preceding claims, characterized in that a drop of protective resin (12) is finally applied to the assembly produced.  
CH01169/95A 1995-04-25 1995-04-25 Piggy back chip mounting technique CH689217A5 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CH01169/95A CH689217A5 (en) 1995-04-25 1995-04-25 Piggy back chip mounting technique

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Application Number Priority Date Filing Date Title
CH01169/95A CH689217A5 (en) 1995-04-25 1995-04-25 Piggy back chip mounting technique

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CH689217A5 true CH689217A5 (en) 1998-12-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1225630A1 (en) * 2001-01-19 2002-07-24 ELA MEDICAL (Société anonyme) Method for making hybrid electronic circuits for active implantable medical devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1225630A1 (en) * 2001-01-19 2002-07-24 ELA MEDICAL (Société anonyme) Method for making hybrid electronic circuits for active implantable medical devices
FR2819935A1 (en) * 2001-01-19 2002-07-26 Ela Medical Sa METHOD FOR MANUFACTURING HYBRID ELECTRONIC CIRCUITS FOR ACTIVE IMPLANTABLE MEDICAL DEVICES
US6898845B2 (en) 2001-01-19 2005-05-31 Ela Medical S.A. Method for manufacturing hybrid electronic circuits for active implantable medical devices

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