CH678669A5 - - Google Patents

Abstract

A battery-fed data recording device for high mechanical loads, particularly accelerations, is described. Analog signal (AI) or digital data (DI) are supplied via converters (103) or (118) to a clocked controller (104) and are read out via this controller and a RAM data memory (105) at an interface (108) after the dynamic loading. A tried use of the data recording device exists in the research and development of munition bodies and their safety systems; after the body has been fired, the device is retrieved and the data are then read out. <IMAGE>

Description

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description

The present invention relates to a data recording device for registering electrical signals in mechanically highly stressed bodies, in particular those which are subject to high accelerations and / or decelerations, the data of the signals being stored in a battery-powered signal memory before and / or during the mechanical stress and after the Stress on the body can be queried.

A preferred use of the device is also specified.

Numerous proposals have been implemented for data recording in dynamically stressed bodies and / or on such bodies. Data recording devices based on analog or digital signal carriers (tapes, rotating hard disks etc.) are generally known, but due to their mechanical drive systems they can only be used for relatively small loads. Furthermore, telemetriseli devices are known which are used in particular at higher accelerations; they require a relatively large amount of equipment and require corresponding maintenance when they are used.

It is therefore an object of the invention to provide an easy-to-use device for data recording which can withstand high mechanical stresses, in particular high accelerations and / or decelerations in a reliable manner.

This object is achieved in that a circuit arrangement aligned in the axis of the main mechanical stress, cast in a polymer and / or in a matrix is provided, which has at least one controller which is controlled by a clock generator and whose signal inputs via an analog / digital Converters and / or via a flip-flop circuit and that its output is combined on the one hand with a read-write memory and on the other hand with an interface for querying the recorded data.

The solution according to the invention allows data to be recorded and stored in the smallest dimensions and, after the data recording device has been recovered, it can be read out and evaluated over a longer period of time. It can be adapted to a wide variety of signal generators and signal types.

Further developments of the subject matter of the invention are described in the following dependent claims.

The data recording device according to claim 2 gives the advantage of a mechanically very compact unit, which is stable and yet easily dismantled can be connected to the body to be measured.

The baffle plate, claim 3, distributes the mechanical energy over a larger area and thus protects the circuit arrangement.

The circular configuration according to claim 4 is advantageous; it allows a simple redirection of the kinetic energy to stable housing parts of the stressed body.

The embodiment according to claim 5 results in a compact enclosing of the circuit arrangements.

The surface mounting of the components (SMD), claim 6, further increases the mechanical stability of the circuit arrangement and thus its resilience.

The structure of claim 7 results in small polar moments of inertia, largely prevents the formation of torsional stresses on the circuit board and thereby increases the vibration resistance of the system,

The structure of the oscillator, according to claim 8, reduces the compressive stresses acting on it, which is particularly important in the case of quartz oscillators for their frequency stability.

A simple source of food is given in claim 9; The installation of the mono cells, orthogonal to the axis, ensures reliable contacting and thus an uninterrupted power supply.

The configuration of the interface as a data connector is particularly practical. In addition to the simple reading of the data, there is also the possibility of connecting several circuit arrangements in cascade form.

Data recording devices operated synchronously with the same oscillator frequency, switched according to claim 11, serve to expand the memory (RAM expansion).

The asynchronous switching of the oscillators, cf. Claim 12, can be particularly advantageous if signals which differ in time are to be recorded.

With very high launch and / or impact accelerations, the RC oscillator according to claim 13 has proven to be particularly robust. Its inherently limited frequency stability remains largely unchanged even under high mechanical loads.

the use of the device according to claim 14 has proven particularly useful; In this way, complex, measured measurements with high sensitivity to interference can be easily eliminated.

The invention is explained below, for example, with reference to drawings. Show it;

1 is a data recording device installed in a floor,

2 shows a first baffle plate according to FIG. 1,

3 shows a connecting flange according to FIG. 1,

4 shows a carrier flange according to FIG. 1,

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5 shows a schematic diagram of the circuit arrangement in the data calibration device with an analog and a digital input,

6 shows a circuit arrangement of a data recording device intended for recording analog signals,

7 shows a circuit arrangement of a data recording device intended for recording digital signals,

8 is a detailed illustration of the controller shown in FIG. 7,

9 is a side view of a circuit board,

10 the circuit board FIG. 9 rotated by 90 °, viewed from above,

10 the circuit plate FIG. 9 rotated by 180 ° in a side plan view,

12 is a cascading of three data recording devices for memory expansion,

13 shows a cascading of three data recording devices for recording signals which are very different in terms of their timing, and FIG. 14 shows an oscillator for a data recording device for extremely high launch accelerations.

In Fig. 1, 1 denotes a data recording device which is installed in a floor 2, an artillery shell. A conventional double hood 3 is used for contacting and thus the impact ignition and forms the tip of an ammunition body 4, which is designed as a jacket and carries a baffle plate 5. A connecting flange 6 with threads connects the baffle plate 5 with the ammunition body 4 and the double hood 3. In the lower region of the ammunition body 4, a carrier flange 7 is used, which centers the data calibration device 1. An empennage 8 in the usual form is located in the end area of the storey 2, as is a measurement sensor 9, an igniter with a safety element 10 and an ignition generator 11 with the corresponding ignition electronics and a La-25 decenser etc.

In the present case of a projectile, the axis A-A corresponds to the main stress in the longitudinal direction of the body and also indicates the direction of the vector of the acceleration + a and the deceleration -a.

The flange-like configuration of the baffle plate 5 on the front side can be seen in more detail in FIG. 2. A Hal-30 flange 51 clamps the data calibration device in the manner shown in FIG. 1. Recesses 52 delimit this area. An edge-side cone 53 is adapted to the outer shape of the projectile 2. The peripheral external thread 54 is used for screwing with the central opening of the likewise conical double hood 3. On a front compression surface 55, the double hood 3 is crumpled up on impact.

The connecting flange 6 shown in half section, FIG. 3, has an inner cone 61, a first and a second external thread 62 and 64 and, on its largest diameter, has a cylindrical ring surface 63 adapted to the dimensions of the ammunition body. The thread 64 is with the internal thread 56 , Fig. 2, screwed according to Fig. 1.

4, there are several bores 72 in the carrier flange 7, which serve as passages for 40 measuring lines, not shown in FIG. 1 for reasons of clarity. The periphery of the flange 7 is designed as a truncated cone 71. A central rectangular mounting recess 73 is provided with sharp-edged corners 74 and completely encloses the data calibration device 1 on its lower end face.

The schematic diagram of the circuit arrangement of the data calibration device 1 can be seen in FIG. 5. Analog signals AI are fed here to a part of the device labeled I and digital signals DI to a part labeled II. The two parts are symbolically separated by a dashed line and usually correspond to two different types of data verification devices. The analog signals AI are converted to digital signals in an analog / digital converter 103 and supplied to corresponding inputs Dn of a controller 104 (control module). Likewise, Digi-50 tal signals DI are impedance-matched to the signal inputs Dn via a flip-flop 118 (Schmitt trigger) and fed to the controller 104. Control signals P are used to program the controller 104 before it is used. The controller is clocked by an oscillator 106. The digital signals D controlled in this way are combined at an interface 108 with a read / write memory 105 (RAM) and can be queried here.

55 The operation of a data verification device can be done in a very simple manner. The signals to be recorded remain available in the memory 105 for several hours since they remain electronically stored by means of an uninterrupted battery-powered power supply. The data verification device can thus experience extreme mechanical loads and can be read out after its recovery (crash, etc.).

60 A proven circuit arrangement for the recording and storage of analog signals is shown in FIG. 6. The power supply from the battery compartment 120 takes place in the manner shown above and is designed here for a voltage range from +2 volts to +6 volts and uses the known known clocked voltage regulator for voltage stabilization. The functional reliability of the circuit arrangement is therefore relatively independent of the state of charge of the batteries. In addition, 65 capacitors C are provided, which could bridge short interruptions in the supply.

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Via a 12-pin data connector 101, the analog signals are routed to an analog / digital converter 103 via an operational amplifier 102 connected as a so-called voltage follower. The data are then read into a read-write memory 105 under predetermined conditions, which are checked by a controller 104. The internal clock frequency for controller 104 is derived from a crystal oscillator 106; the input on controller 104 is labeled OSC. Data bus lines (data bus) 107 are provided for transmitting the data from the analog / digital converter 103 to the read / write memory 105 and from the data connector 101 to the controller 104. The read-in data can be read out again as desired via a 20-pin data connector 108. The clock frequency and the read / write conditions for the conversion of the analog / digital converter 103 are determined via the output A / D of the controller 104. The digitized data are then read into the read / write memory 105 via the outputs D of the analog / digital converter 103 and the likewise named inputs D. At the same time with the same clock frequency, the addresses are assigned via the outputs A of the controller 104 to the data read into the read-write memory 105. The main connections of controller 104 are identified as follows: —OSC oscillator signal input

- ECL input for an external clock signal

—ST inputs for determining the triggering on the positive or negative edge of the signals

- RE input for the reset

—Po / Pi programming of the internal clock signal

- CL output of the internal clock signal

—RF output to indicate that read-write memory 105 is full

- DP outputs / inputs for the readout conditions

-WE output for the enable to read the data (Write Enable)

- ROE output for the release of a memory expansion (RAM Output Enable)

7 shows the circuit arrangement for the recording and storage of digital data. The same reference numerals as in FIG. 6 were used for the same functional parts.

In contrast to the circuit arrangement according to FIG. 6, the data are read into the read / write memory 105 via the inputs Din and the outputs D0ut of the controller 104. Schmitt triggers (not shown) are connected between these inputs and outputs so that interference voltages in the digital signals are eliminated.

Controller 104 will now be explained in more detail with reference to FIG. 8:

The function blocks shown are an address controller 109, a status controller 110, a command sequence generator 111, a clock generator 112 and a read-out controller 113. The address controller 109 has an address counter 114, a start address memory 115 and an end address counter 116. The address counter 114 consists of three times six D-FIip flops with a Clear Direct and a Set Direct input, which are connected together to form an asynchronous dual counter. The outputs of the first six flip-flops are combined by a non-and circuit (NAND), which is connected via an exclusive-OR sound to the output of the first flip-flop of the second row at the input of this first flip-flop. The outputs of this second row of flip-flops are in turn combined with a NAND circuit, the output of which is fed to the output of the first NAND circuit of an OR circuit and in a manner similar to that of the second row at the input of the first flip-flop of the third Row is connected via an exclusive-OR circuit. The next row of D flip-flops is only activated when the first row is fully counted (2S = 64 or 212 = 4096). All outputs of the 18 D flip-flops are connected via an 18-wire signal line to the address outputs Ao to At? connected. With this address counter 114, 262144 addresses can thus be selected.

The start address memory 115 consists of 18 D-latch flip-flops, each with a Clear Direct input and a gate, which memory holds the start address when a load signal (L-SA = load start address) is applied to the gates.

The end address counter 116 is constructed similarly to the address counter 114, but is provided with a D flip-flop with Clear Direct. The outputs of the last three or the penultimate flip-flops are combined via a NAND circuit and form the signal FL (full) as soon as the first of these three or the penultimate flip-flops has responded.

The state control lio has two flip-flops connected in series, which simultaneously cause the control signal RS and the control signal L-SA with the overturning of the first flip-flop of the last three or penultimate in the end address counter 114. Thus, the overturning of the 15th / 16th / 17th or 16./17./18. Flip-flops the start address, which means that the data is stored with a memory depth of 16k or 32k x 8 bit before the start event. A control signal ST + or ST- is connected to two other series-connected flip-flops of the status control 110, as a result of which the reset signal RS for the end address counter 114 takes place.

The command sequence transmitter 111 has a series of five D flip-FIops with Clear Direct, which are connected as so-called Johnson counters, i.e. as a shift register with a return of the Q output of the last flip-flop to the D input of the first flip-flop, and serves as a fast counter / timer. With this counter and the clock signal CL or with the direct oscillator signal OSC, the control

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signals A / D RD, BOE, WE, CKF and A / D WR provided.

The signals A / D RD and A / D WR are the read and write signals for the analog / digital converter 103, which determine the clock of the analog / digital conversion and the transmission into the read / write memory 105. The control signal BOE (Buffer Output Enable) is provided in the event that 16-bit data or more are to be read in instead of 8-5 bit data. This signal BOE leads to two drivers 117, the outputs of which are connected to the tristate drivers of the digital outputs Do to D? are connected. The control signal WE (Write Enable) releases the data for reading into the read-write memory 105. The control signal CKF, on the command sequence generator 111, indicates that the measurement time has expired and, together with the control signal FL from the end address counter 116, gives this Control signal L-SA in state 10 controller 110.

The clock generator 112 consists of two Johnson counters which result in a division by 10 or a division by 100 of the input clock signal OSC. The sampling rate and the clock frequency can be set with the programming signals Po and Pi:

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If Po = Pi = 1, the clock frequency can be determined by an external oscillator ECL (input 25 ECI). With a Schmitt trigger 118, possible interference voltages or interference peaks in the oscillator signal are suppressed, so that a perfect square wave voltage is generated.

The read-out controller 113 essentially consists of an RS flip-flop with NAND gates, one of which is a tri-state gate, and consists of two D flip-flops coupled as shift registers with clear direct inputs. The signals IFC (Interface Clear), RFD (Ready for Data), DAC (Data Accept-30 ted) and DAV (Data Valid) are the usual control commands for an IEC / IEEE bus interface (details are given in the book "Semiconductor Circuitry" from U. Tietze and Ch. Schenk, (1980), see pages 580 to 585). The input signals IFC, RF (see above), RFD and DAC form, via the RS flip-flop, the control signal ROE (RAM Output Enable), FIG. 7, which is a control signal for an expansion of the read-write memory 105.

35 This control signal is also applied to the CD input of the D flip-flops, the CP inputs of which are supplied with the clock signal OSC. A logic one is present at the D input of the first flip-flop and the Q output of this flip-flop is connected to the D input of the following flip-flop. In this way, the known control signal DAV is generated for the IEC bus interface.

Schmitt triggers 118 are provided between the digital inputs Dio to DI7 and the digital outputs Do to D7 for the same reason as for the input of the external oscillator signal, so that square wave signals without interference spikes at the read-write memory 105, FIG. 7, concern. The possible interference signals, which are superimposed on the analog data signal, are eliminated in the analog / digital conversion.

Furthermore, individual drivers 117 are provided in order to guarantee perfect signal transmission. Furthermore, three AND gates 119 can also be seen in the diagram according to FIG. É which the IFC and the RF signal, or the CL and the L-SA signal, or the RF and the A / D Link signal.

The integrated circuit ADC 0820 from National Semiconductor, USA (see data sheet IM-B30N113 from November 1983) was used as the analog / digital converter 103, FIG. 10, 11, and the integrated circuit was used as the read / write memory 105 DPS 41 288 from Densepac, USA, the oscillator circuit MCSO from ETA, CH-Grenchen, was used as the quartz oscillator 50 106, and the controller-specific integrated circuit of the PA 50 000 series in CMOS technology from RCA, USA, was used as the controller 104 . The electronic components required for this, such as flip-flops and NAND and NOR gates etc., are given as standard cells and can be found in the manual AGL132 (1985).

55 The printed circuit board 1b, FIG. 9, with the axis A-A drawn in, is equipped on the surface shown with the electrical and electronic components known per se in their functions. The following can be seen: the 20-pin data connector 108, two block capacitors 125 and 126 for supplying the A / D converter, the read / write memory 105, network resistor 127, which serves as the pull-down resistor of the controller, the monocells 123 to 124 with its screw plug 121 in the battery 60-fold 120 and the contact surfaces 122 'to 124', a further block capacitor 128, here in the supply of the operational amplifier 102, a DC / DC converter 129 for generating 12 volts as a voltage increase reduced battery voltage, a choke coil 130 belonging to the 5 volt DC / DC converter 131, a further block capacitor in the supply to the read / write memory 105. The position of the polymer or the matrix 40 is also symbolically indicated by an arrow; Like the data connector 108, the data connector 101 65 is arranged flush on the circuit board 1 b.

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In FIG. 10, the circuit arrangement designated 1a of FIG. 9 is loaded from above. The following can also be seen here: the analog / digital converter 103, the crystal oscillator 106, the controller 104, a block capacitor 134 in the supply to the controller, one of the two network resistors 135, 136,

which serve as pull-up resistors for the controller, a choke 139 in the 12 volt DC / DC converter and the housing 100 shown partially. ^

11 shows the components already shown in FIGS. 9 and 10; also a white ~

tere block capacitor 133, which serves to smooth the reference voltage in the A / D converter

The locking screw 121 presses the monocells 122-124 against one another at their contact surfaces 122-124 ', see FIG. Fig. 9. This type of assembly results in a very reliable power supply, * since only minor lateral accelerations are to be expected here.

A drawn chrome steel standard profile serves as the housing 100. In it, the entire circuit arrangement is cast in a polymer and held in the sense of a matrix.

The cascading according to FIG. 12 is used above all with larger amounts of data. It is sufficient in itself to connect identical data recording devices 1 ', 1 ", 1"' to one another with their corresponding circuit arrangements 1a'-1a '". The characteristic inputs and outputs of each circuit arrangement are designated 31-36". All controllers are synchronized with each other by the same clock signal CL. The start signal S1 switches the input signal S2 from the input 36 of the first device V to its memory; if this is full, the input signal S2 is read into the memory 34 of the next device by the signal RF appearing at the output 35. Cascades of any size can be built up in the same way.

Different sampling rates are often desired when measuring physical quantities, since the temporal courses of the individual signals are quite different from one another. The cascading according to FIG. 13 enables this in a simple manner. In contrast to the cascading described above, the individual oscillators of the controllers are each individually controlled. This is done by simply programming the controller itself.

It has been shown that at very high launch and / or impact accelerations, a device clocked on the basis of quartz oscillators remains operational up to approximately 50,000 g. However, the high acceleration values cause charge shifts within the structure of the quartz crystal, which negatively affects the constancy of the oscillation frequencies. Surprisingly, it has been shown that an RC oscillator, especially in the case of relatively short-term measurements, gives better values, since its inherently thermally induced frequency instability is independent of the acceleration occurring.

A characteristic circuit arrangement 20, FIG. 14, is based on a commercially available Schmitt trigger 21 (TLC555 LinCMOS timer trademark from Texas Instruments, USA), which is fed back through capacitors and resistors 22-30. The resonant circuit frequency can be tuned within narrow limits with the resistors 27 and 28.

For most measurements, those from 1 to 24 MHz have proven to be the clock frequencies for quartz oscillators. The RC oscillator, FIG. 14, is designed for 1 MHz. This oscillator is also started when the supply voltage is applied; the output signal CL is fed to the controller 104.

The data recording device is advantageously provided with a casting compound from a cold-curing cast resin system (Araldit CY220 or hardener HY842, trademark of Ciba-Geigy, Basel)

poured out. Other casting compounds, for example with heat-dissipating additives and / or known additives of fillers and / or matrix materials, can improve the mechanical properties of the device depending on the intended use; In particular, microfine ground dolomite (Microdol, trade name of A / S Norwegian Tale) has proven its worth with proportions of 200-300% of the resin weight of the casting compound.

In addition to the use shown, further kinetic signal calibrations are conceivable, namely for evaluating impact tests (crash tests), investigations at exposed locations (environmental influences, etc.).

Claims (14)

Claims 1, data recording device for registering electrical signals in mechanically highly stressed bodies, in particular those which are subject to high accelerations and / or delays, the data of the signals being stored in a battery-powered signal memory before and / or during the mechanical stress and after the stress on the body queries-> bar, characterized in that a circuit arrangement (1a) which is aligned in the axis (AA) of the main mechanical stress and is cast in a polymer and / or in a matrix (40) is provided, which has at least one controller (104) which is controlled by a clock generator (106) is controlled and its signal inputs (Dn) are led via an analog / digital converter (103) and / or via a "flip-flop (118) and that its output (D) is connected on the one hand to a read / write memory (105) and on the other hand is combined with an interface (108) for querying the recorded data. (Fig. 1,5,10) 2. Data acquisition device according to claim 1, characterized in that the circuit arrangement (1a) is cast in a box-shaped housing (100) and that this is in the axis (A-A) 6 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 CH 678 669 A5 the main mechanical stress, in its end areas in flanges (5, 7) and held in the longitudinal direction (A-A). (Fig. 1,10) 3. Data acquisition device according to claim 2, characterized in that at least one baffle plate (5) is provided, which is upstream of at least one carrier flange (7). (Fig. 1) 4. Data calibration device according to claim 3, characterized in that at least one baffle plate (5) and / or a carrier flange (7) are circular and that at least one external thread (54) is provided on them. (Fig. 1.3). 5. Data acquisition device according to claim 2, characterized in that the housing (100) is a hollow profile with at least two flat and mutually parallel surfaces. (Fig. 10) 6. Data acquisition device according to claim 1, characterized in that the circuit arrangement (1a) has a circuit board (1b) and that the components (101 to 124 ') of the circuit arrangement (1a) on the surface of this circuit board (1b) or in this circuit board (1b) and that the components (101 to 124) are enclosed by a polymer (40) made of epoxy resin and a filler (FIGS. 9 and 10). 7. Data acquisition device according to claim 6, characterized in that the components (101 to 124 ') of the circuit arrangement (1a) are arranged on two opposite surfaces of the circuit board (1b), that the mass of the components (101 to 124') on one These surfaces are approximately equal to the mass of the components (101 to 124 ') on the other of these surfaces and that connecting lines between the components (101 to 124') are located on these surfaces of the printed circuit board (1b). (Figs. 9 to 11). 8. Data acquisition device according to claim 6, characterized in that the oscillator of the clock generator (106) is aligned in the axis (A-A) of the main mechanical stress and this is congruent with the axis of symmetry of the housing (100). (Fig. 11) 9. Data acquisition device according to claim 2, characterized in that a battery compartment (120) is provided in the housing (100), in which at least two battery mono cells (122, 123) are arranged one behind the other, and that their contact surfaces (122 ', 123') are orthogonal are aligned with the axis (AA) of the main mechanical stress. (Fig. 9,10) 10. Data acquisition device according to claim 1, characterized in that the interface (108) is designed as a data connector. (Fig. 9) 11. Data acquisition device according to claim 1 or 10, characterized in that at least two circuit arrangements (1a ', 1a ") are connected to one another in a cascade-like manner and synchronously with a single clock signal (CL), one indicating a full read-write memory (105) Signal (RF) of a circuit arrangement (1a ') is in each case routed to the start signal input (34') of the next circuit arrangement (1a ") and all the memory signal inputs (36, 36 ') are connected to one another. (Fig. 12) 12. Data acquisition device according to claim 1 or 10, characterized in that at least two cast-in circuit arrangements (1a ', 1a ") are cascaded and asynchronously connected to one another, a signal (RF) of a circuit arrangement indicating a full read-write memory (105) (1a ') is in each case led to the start signal input (34') of the next circuit arrangement (1a ") and all the memory signal inputs (36, 36 ') are connected to one another. (Fig. 13) 13. Data acquisition device according to claim 8, characterized in that the oscillator is designed as an RC oscillator (20). (Fig. 14) 14. Use of the data acquisition device according to claim 1 or 13 in storeys for recording ballistic and / or electrical data. (Fig. 1) 7