CH660270A5 - DECODER CIRCUIT, METHOD FOR THEIR OPERATION AND WIRELESS CALL RECEIVER. - Google Patents

Description

The present invention relates to a decoder circuit according to the preamble of claim 1, a method for its operation and a wireless call receiver with such a decoder circuit.

Such a circuit comprises a code recognition circuit in which a comparison must be made to determine whether a received code word corresponds to a stored code word, e.g. corresponds to an address code word. According to the prior art, this comparison can take place either in parallel or in series.

In the known parallel comparison, the principle of which is shown in FIG. 1

shows, a digital data word is stored in a register 1, while another similar digital data word with which the one data word is to be compared is stored in another register 2. For an N-bit data word, each register must have 1 and 2 N data latches. The bits thus arranged in pairs are compared simultaneously using N comparison elements 3, which elements can be exclusive-OR gates, and the number of deviations between the two words are counted using an error counter 4. With this principle, the comparison can be carried out very quickly, but there is the disadvantage that a large number of logic elements must be present, which means that comparison circuits according to this principle are not particularly suitable for integration on a single integrated circuit should contain other functions.

In the known serial comparison, the principle of which is shown in FIG. 2, two digital data words are input and compared bit by bit. Only one hold circuit 5, 6 is therefore required for each data word of N bits, furthermore only a single comparison element 7 and an error counter 8. In contrast, N clock periods are necessary in order to shift the data words. In the serial comparison, significantly fewer logic elements are required than in the parallel comparison, but it takes a longer time to carry out the comparison process.

It is an object of the present invention to provide a decoder circuit whose code recognition circuit requires fewer logic elements than the known circuits with parallel comparison, but works faster than the known circuits with serial comparison.

This object is achieved by the features mentioned in the characterizing part of the first claim. Advantageous developments of the invention, and a method for operating such a decoder circuit and a wireless call receiver with such a decoder circuit can be found in the further claims.

An embodiment of the invention will now be explained in more detail with reference to the drawing. The drawing shows:

3a shows the format of a code word used; 3b shows a synchronization code word with 32 bits; 3c shows an empty code word with 32 bits; and Fig. 4 shows the code recognition part of a decoder circuit. The comparison principle used in the present decoder circuit is a combination of the parallel and serial solutions, which enables a quick comparison of incoming data with predetermined words, without the need for a large number of logic elements. This comparison circuit has been specially designed for use as a code recognition circuit in a digital wireless paging receiver, but it can also be used for other purposes. A digital wireless pager must receive and process reliably broadcast digital signals, which signals may be subject to noise or phase jitter at the receiving location.

The following description is based on the use of the comparison circuit of the digital code in a wireless call receiver, in which a code in accordance with the POCSAG specification (British Post Office Code Standardization Advisory Group) is used. The code is based on a (31, 21, 2) -BCH code and the full description of the standard code format can be found in the above specification. The aforementioned BCH code is a cyclic code named after the inventors Bose / Chaudhuri / Hocquenghem with an error correction possibility, which has a block length of 31 bits, of which 21 bits are information bits and 2 errors can be corrected, the remaining 10 bits are check bits.

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A transmission consists of a preamble followed by sets of complete code words, the format of a code word being shown in Fig. 3a. Each set comprises a synchronization word (Fig. 3b), followed by 8 frames, each containing two code words (address and message). The call receivers are divided into 8 groups, each receiver being assigned one of the 8 frames and therefore only checking address code words in this frame. Therefore, the address code word of each paging receiver need only be transmitted in the frame assigned to these code words. Message codewords for any pager can be transmitted in any frame, but directly follow the associated address codeword. A message can consist of any number of codewords transmitted in succession and can comprise one or more sentences, but the synchronization codeword must not be shifted by message codewords. The end of the message is indicated by the next address code word or by an empty code word (FIG. 3c). In the absence of an address or message code word, an empty code word is transmitted.

Each code word is a digital code word with 32 bits (Fig. 3a). Each code word contains 21 bits of information, which correspond to coefficients of a polynomial that has expressions from x30 down to x10. The polynomial is divided by the generator polynomial x10 + x9 + x8 + x6 + x5 + x3 + 1 modulo-2. The 10 check bits correspond to the coefficients of the expressions from x9 to x ° in the rest of the polynomial that is present after performing this division. The complete block, consisting of the information bits, followed by the check bits, corresponds to the coefficients of a polynomial, which can be divided by the modulo-2 generator polynomial without any remainder. An additional bit is added to the 31 bits of the block to allow parity checking of the entire code word for an even number of bits.

Each transmission begins with a preamble so that the call recipients can achieve bit synchronization and to prepare them for achieving word synchronization. The preamble is a pattern of changes 101010 ... which are repeated over a period of at least 576 bits, i.e. for the duration of a sentence plus a code word. The present decoder circuit is used in the call receiver as a code recognition circuit for comparing the transmitted synchronization code word with a predetermined synchronization code word and for comparing the transmitted address code words with a predetermined address code word. The error correction option contained in the code is not used. Since the code recognition circuit must be part of the decoder circuit of the call receiver in a customer-specific integrated circuit, various boundary conditions must be observed for its design.

A call receiver can be switched on at any time or emerge from radio shadows, so that it is desirable that the call receiver can achieve bit and word synchronization with a minimal expenditure of time and can distinguish between real data and random noise. A circuit for bit synchronization and for data / preamble detection is in DE-Pat. No. 3,262,789. The present code recognition circuit is particularly, but not exclusively, suitable for use in a digital wireless call receiver with the aforementioned circuit. The data are transmitted as 32-bit words with a data rate of 512 bits / s, and, as already mentioned, an additional parity bit is added to the BCH code.

4, the principle of comparison of the present invention will now be explained in more detail. The circuit of FIG. 4, however, contains more elements than are necessary for the basic version. The incoming data are read into a feedback N-bit shift register, in the case of the call receiver into a 32-bit shift register, instead of reading into an N-bit hold circuit, as would be necessary with the parallel comparison principle according to FIG. 1. The feedback N-bit shift register of Fig. 4 consists of an (N-1) bit shift register 10 and a shift register 11 for a single bit. This division takes place for reasons which are explained below in connection with the use in a call receiver. The shift register, which has small elements which facilitate integration, is clocked at a multiple of the clock of the incoming data, so that the N data bits are shifted more than once in a single bit period. For the paging receiver, a 31-bit shift register is used together with a shift register for a single bit as the total shift register, which is clocked with a signal of 32 kHz, so that each word is shifted once in the first half bit period and advances by one position, so that a new data bit can be loaded at the beginning of the next bit period. Usually the shift register is not clocked during the second half bit period. This means that the content of the shift register is not influenced by the slight changes which are brought about by the bit synchronization which takes place in parallel in the decoder of the paging receiver, as will be described below.

The word in the shift register (10 + 11) is thus updated with every data bit and a running data word can be compared serially with a predetermined word by comparing the content of the register with a predetermined word generated by a code generator 14 which is also clocked at 32kHz. The comparison is carried out with the aid of a comparison element 12 and errors are counted in an error counter 13. The principle can be extended for the comparison of M given words if the clock frequency is made M times the incoming data rate, although this is not always possible.

For use in a pager, the basic circuitry, which has an N-bit shift register feedback, a source for predetermined words, a comparator and an error counter, has been brought into the form shown in Fig. 4, as will be described will enable the comparison of four predetermined (address) code words in order to enable one of four different time slots.

Since the data appears in 32-bit words, it is usually not necessary to make a comparison until after the 32nd bit has been received. The number of comparisons can be increased by continuing to shift the same word during the second 1/2 bit period and another two times during the subsequent bit period, whereby of course word switching and the loading of a new data bit must be suppressed during this time period. In order to be able to check the next 32-bit word, it is necessary to find the first bit at the right time, which was not loaded into the shift register. This is achieved by using a 2-bit data buffer 15 so that two bits can be loaded into the shift register at the same time, revealing the “lost” bit. With this principle, four comparisons can be carried out without increasing the clock frequency.

It is a feature of this circuit that, as a result of the properties of the (31, 21, 2) -BCH code, the eleven least significant bits in the decoder of the pager using this circuit need not be stored since the ten Parity check bits and the additionally added 32nd bit according to a predetermined polynomial by the code

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Generator 14 are generated. Furthermore, in this application, because the remaining 21 bits of the four given words differ only in their two least significant bits and because the most significant bit for an address code word is always the same ("0"), only a single 18-bit word can be saved to generate all four given address words. The code generator 14 can be replaced by other means which generate a predetermined word which is to be compared with another word. The generator 14 described, however, shows that the number of logical elements necessary for the generation of the predetermined (address) code words is minimal when using BCH codes. Therefore, the use of the present decoder circuit with comparison means together with the above code generating means leads to the number of logic elements being further reduced compared to the use of parallel comparison methods.

The present principle uses a serial comparison, which is generally slow. However, the comparison is carried out at a high clock frequency and requires only a single feedback 32-bit shift register instead of two 32-bit latches, as would be necessary in a parallel comparison according to FIG. 1, a shift register being simpler than a latch. The present circuit thus results in a rapid mode of operation with a reduced number of logic elements, so that the comparison circuit can be used particularly well for large-scale integration.

The mode of operation of the code recognition circuit according to FIG. 4 in the decoder of the call receiver can be seen from the following description of the mode of operation of the decoder. The decoder of the digital call receiver is designed as a customer-specific integrated circuit, which is used in the call receiver together with a further customer-specific integrated circuit, namely the receiver circuit.

The receiver circuit is a linear analog circuit which interacts with the digital decoder circuit of the paging receiver. The receiver circuit processes the incoming data signals from the antenna into a digital signal, which is offered to the digital decoder. The receiver circuit can e.g. be designed as described in GB Pat. No. 1517121, 2032737 and 2057820.

The data in the shift register are only shifted during the first half bit period and remain during the second half bit period. Bit synchronization is performed during this second half bit period and it is important that the data in the memory is not scrambled as this would make code recognition impossible. In order to achieve this, the algorithm of the bit synchronization requires that the information in the data memory is not clocked or shifted during the bit synchronization. In other words, there is a rest period in the data memory in which the data is entered but not shifted and cannot be influenced by the bit synchronization. 15 The data is therefore loaded into the memory at the required bit rate and rotates bit by bit, but then the clock signal is stopped so that the data is not influenced by the bit synchronization. The bit synchronization circuit therefore actually controls the clock of the data memory, so that the data memory and the bit synchronization circuit are closely linked to one another. Of course, this is only important with this type of feedback data storage. If the data is not shifted in such feedback memory at a high bit rate, 25 then changes in bit synchronization have no effect on the data.

Within the decoder, it is not necessary to carry out the bit synchronization over the entire duration of the sentence, and in fact the bit synchronization is stopped at the time of the address word comparison in order to enable circulation in the data memory and the comparison of four words in two bit periods.

The present comparison principle, which is a combination of the parallel and serial comparison methods according to the prior art, requires that the digital data be input into a feedback shift register, which is clocked at high frequency. As soon as a complete data word circulates in it, it can be output at the high clock frequency and compared serially with this clock frequency with a given word.

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Claims (6)

660 270 1. Decoder circuit with a code detection circuit in which an incoming N-bit data word is compared with a locally generated N-bit data word, characterized in that the code detection circuit has a feedback N-bit shift register with an (Nl) -Bit shift register (10) and a shift register (11) for a single bit and a 2-bit data memory (15), via which the incoming data word is loaded into the shift register, the whole in such a way that a word circulating in the shift register can be compared several times in succession in successive bit periods with the locally generated word. 2. Decoder circuit according to claim 1, wherein the shift register (10, 11) is clocked at a first clock frequency which is a multiple of the bit clock frequency of the incoming word, characterized in that the shift register is followed by a comparison element (12), and that means (14) are provided in order to apply the locally generated data word together with the circulating data word with the first clock frequency to the comparison element, so that the corresponding bits of the two words are compared with one another in series with the first clock frequency. 2nd PATENT CLAIMS 3. A method of operating a decoder circuit according to claim 1 for comparing an incoming N-bit data word with a similar, locally generated data word in order to detect differences between these two words, with a counter (13), characterized in that the one N -Bit data word is loaded into the feedback N-bit shift register, that the word loaded in the shift register is compared serially with the locally generated word with the first clock frequency, and that with the counter (13) the number of differences between the two words is counted. 4. The method according to claim 3, characterized in that a word loaded into the shift register and circulating therein is compared once in every half bit period in a number of successive bit periods with the locally generated word, and in that the word switching and the loading of a new data bit in the shift register is suppressed during the number of consecutive bit periods with the exception of the first half bit period. 5. The method according to claim 4, characterized in that the incoming data via a 2-bit buffer memory (15) are loaded into the shift register, which enables the simultaneous loading of two bits with retrieval of the first bit to be loaded in the incoming word. 6. Digital wireless call receiver with a decoder circuit according to claim 1 for the detection of the synchronization word and the address word assigned to the receiver, which receiver also has a bit synchronization circuit to which the incoming N-bit data words are also applied, the bit synchronization circuit during the first half bit period is inoperative, during which the incoming data is loaded into the feedback shift register.