CH597724A5 - - Google Patents

Info

Publication number
CH597724A5
CH597724A5 CH1582475A CH1582475A CH597724A5 CH 597724 A5 CH597724 A5 CH 597724A5 CH 1582475 A CH1582475 A CH 1582475A CH 1582475 A CH1582475 A CH 1582475A CH 597724 A5 CH597724 A5 CH 597724A5
Authority
CH
Switzerland
Application number
CH1582475A
Inventor
Heinz Kurek
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH597724A5 publication Critical patent/CH597724A5/xx

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/14Digital recording or reproducing using self-clocking codes
    • G11B20/1403Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Magnetic Recording (AREA)
CH1582475A 1974-12-20 1975-12-05 CH597724A5 (enrdf_load_stackoverflow)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19742460534 DE2460534B2 (de) 1974-12-20 1974-12-20 Schaltungsanordnung zur decodierung von von magnetschichtspeichern gelieferten lesesignalen

Publications (1)

Publication Number Publication Date
CH597724A5 true CH597724A5 (enrdf_load_stackoverflow) 1978-04-14

Family

ID=5934093

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1582475A CH597724A5 (enrdf_load_stackoverflow) 1974-12-20 1975-12-05

Country Status (8)

Country Link
AT (1) AT353515B (enrdf_load_stackoverflow)
BE (1) BE836875A (enrdf_load_stackoverflow)
CH (1) CH597724A5 (enrdf_load_stackoverflow)
DE (1) DE2460534B2 (enrdf_load_stackoverflow)
FR (1) FR2295514A1 (enrdf_load_stackoverflow)
GB (1) GB1518700A (enrdf_load_stackoverflow)
IT (1) IT1051045B (enrdf_load_stackoverflow)
NL (1) NL7514781A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
HU183139B (en) * 1980-05-14 1984-04-28 Magyar Optikai Muevek Electronic decoding circuit arrangement for systems with self-synchronization

Also Published As

Publication number Publication date
DE2460534A1 (de) 1976-07-01
FR2295514A1 (fr) 1976-07-16
FR2295514B3 (enrdf_load_stackoverflow) 1979-10-05
IT1051045B (it) 1981-04-21
AT353515B (de) 1979-11-26
DE2460534B2 (de) 1977-12-01
NL7514781A (nl) 1976-06-22
BE836875A (fr) 1976-06-21
GB1518700A (en) 1978-07-19
DE2460534C3 (enrdf_load_stackoverflow) 1978-08-03
ATA848075A (de) 1979-04-15

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Legal Events

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PL Patent ceased
PL Patent ceased