CH545561A - - Google Patents
Info
- Publication number
- CH545561A CH545561A CH1166772A CH545561DA CH545561A CH 545561 A CH545561 A CH 545561A CH 1166772 A CH1166772 A CH 1166772A CH 545561D A CH545561D A CH 545561DA CH 545561 A CH545561 A CH 545561A
- Authority
- CH
- Switzerland
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19712146392 DE2146392C3 (en) | 1971-09-16 | 1971-09-16 | Method for synchronization in data networks with concentrator devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH545561A true CH545561A (en) | 1974-01-31 |
Family
ID=5819790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1166772A CH545561A (en) | 1971-09-16 | 1972-08-07 |
Country Status (7)
| Country | Link |
|---|---|
| BE (1) | BE788893A (en) |
| CH (1) | CH545561A (en) |
| DE (1) | DE2146392C3 (en) |
| FR (1) | FR2153052B1 (en) |
| IT (1) | IT967365B (en) |
| LU (1) | LU66076A1 (en) |
| NL (1) | NL7212482A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2557339C2 (en) * | 1975-12-19 | 1982-12-16 | TE KA DE Felten & Guilleaume Fernmeldeanlagen GmbH, 8500 Nürnberg | Circuit arrangement for converting an anisochronous binary input signal into an isochronous binary output signal |
| DE3410188C2 (en) * | 1984-03-20 | 1986-10-23 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Method and circuit arrangement for clock correction in a digital data transmission device |
| FR2579047B1 (en) * | 1985-03-15 | 1992-04-30 | Cochennec Jean Yves | FREQUENCY TUNING SYNCHRONIZATION METHOD AND DEVICE FOR IMPLEMENTING THE METHOD |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3093815A (en) * | 1960-05-31 | 1963-06-11 | Bell Telephone Labor Inc | Pulse repeating system |
-
0
- BE BE788893D patent/BE788893A/en unknown
-
1971
- 1971-09-16 DE DE19712146392 patent/DE2146392C3/en not_active Expired
-
1972
- 1972-08-07 CH CH1166772A patent/CH545561A/xx not_active IP Right Cessation
- 1972-09-12 IT IT2907472A patent/IT967365B/en active
- 1972-09-14 NL NL7212482A patent/NL7212482A/xx not_active Application Discontinuation
- 1972-09-14 LU LU66076D patent/LU66076A1/xx unknown
- 1972-09-15 FR FR7232838A patent/FR2153052B1/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| NL7212482A (en) | 1973-03-20 |
| IT967365B (en) | 1974-02-28 |
| DE2146392A1 (en) | 1973-03-22 |
| DE2146392B2 (en) | 1977-11-03 |
| FR2153052A1 (en) | 1973-04-27 |
| DE2146392C3 (en) | 1978-06-29 |
| FR2153052B1 (en) | 1977-07-22 |
| BE788893A (en) | 1973-03-15 |
| LU66076A1 (en) | 1973-03-19 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |