CH518597A - Fehlererkennungsschaltung in Datenverarbeitungsanlagen und Datenübertragungseinrichtungen - Google Patents

Fehlererkennungsschaltung in Datenverarbeitungsanlagen und Datenübertragungseinrichtungen

Info

Publication number
CH518597A
CH518597A CH523670A CH523670A CH518597A CH 518597 A CH518597 A CH 518597A CH 523670 A CH523670 A CH 523670A CH 523670 A CH523670 A CH 523670A CH 518597 A CH518597 A CH 518597A
Authority
CH
Switzerland
Prior art keywords
detection circuit
error detection
processing systems
transmission devices
data processing
Prior art date
Application number
CH523670A
Other languages
English (en)
Inventor
Flinders Michael
Lycett Gardner Peter
Henry Hallett Michael
Wyn Jones John
Francis Minshull John
Graham Taylor Keith
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH518597A publication Critical patent/CH518597A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
CH523670A 1969-04-24 1970-04-09 Fehlererkennungsschaltung in Datenverarbeitungsanlagen und Datenübertragungseinrichtungen CH518597A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2090269 1969-04-24

Publications (1)

Publication Number Publication Date
CH518597A true CH518597A (de) 1972-01-31

Family

ID=10153715

Family Applications (1)

Application Number Title Priority Date Filing Date
CH523670A CH518597A (de) 1969-04-24 1970-04-09 Fehlererkennungsschaltung in Datenverarbeitungsanlagen und Datenübertragungseinrichtungen

Country Status (9)

Country Link
US (1) US3646516A (de)
JP (1) JPS504418B1 (de)
BE (1) BE748548A (de)
CH (1) CH518597A (de)
ES (1) ES378975A1 (de)
FR (1) FR2042945A5 (de)
GB (1) GB1265013A (de)
NL (1) NL7003739A (de)
SE (1) SE353408B (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7010586A (de) * 1970-07-17 1972-01-19
US3839717A (en) * 1972-01-28 1974-10-01 Identification Co Inc Communication apparatus for communicating between a first and a second object
US3990009A (en) * 1975-03-14 1976-11-02 Bell Telephone Laboratories, Incorporated Method and apparatus for uniquely encoding channels in a digital transmission system
GB1572895A (en) * 1976-03-04 1980-08-06 Post Office Data processing equipment
DE2612100A1 (de) * 1976-03-22 1977-10-06 Siemens Ag Digitale datenverarbeitungsanordnung, insbesondere fuer die eisenbahnsicherungstechnik
DE2729362C2 (de) * 1977-06-29 1982-07-08 Siemens AG, 1000 Berlin und 8000 München Digitale Datenverarbeitungsanordnung, insbesondere für die Eisenbahnsicherungstechnik, mit in zwei Kanälen dieselben Informationen verarbeitenden Schaltwerken
JPS5494850A (en) * 1978-01-11 1979-07-26 Nissan Motor Arithmetic processor
US4233682A (en) * 1978-06-15 1980-11-11 Sperry Corporation Fault detection and isolation system
US4453093A (en) * 1982-04-02 1984-06-05 Honeywell Information Systems Inc. Multiple comparison circuitry for providing a software error trace signal
US5128944A (en) * 1989-05-26 1992-07-07 Texas Instruments Incorporated Apparatus and method for providing notification of bit-cell failure in a redundant-bit-cell memory
US5200963A (en) * 1990-06-26 1993-04-06 The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration Self-checking on-line testable static ram
US5758065A (en) * 1995-11-30 1998-05-26 Ncr Corporation System and method of establishing error precedence in a computer system
JP4717617B2 (ja) * 2005-12-08 2011-07-06 富士通株式会社 連想メモリ制御装置及び方法

Also Published As

Publication number Publication date
DE2018001B2 (de) 1976-12-02
US3646516A (en) 1972-02-29
BE748548A (fr) 1970-09-16
GB1265013A (de) 1972-03-01
SE353408B (de) 1973-01-29
JPS504418B1 (de) 1975-02-19
DE2018001A1 (de) 1970-11-12
FR2042945A5 (de) 1971-02-12
NL7003739A (de) 1970-10-27
ES378975A1 (es) 1972-08-01

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Legal Events

Date Code Title Description
PL Patent ceased