CH504103A - Method of contacting the zone of a monolithic solid-state circuit - Google Patents

Method of contacting the zone of a monolithic solid-state circuit

Info

Publication number
CH504103A
CH504103A CH1733669A CH1733669A CH504103A CH 504103 A CH504103 A CH 504103A CH 1733669 A CH1733669 A CH 1733669A CH 1733669 A CH1733669 A CH 1733669A CH 504103 A CH504103 A CH 504103A
Authority
CH
Switzerland
Prior art keywords
contacting
zone
state circuit
monolithic solid
monolithic
Prior art date
Application number
CH1733669A
Other languages
German (de)
Inventor
Kraft Wolfgang
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19681811019 external-priority patent/DE1811019C3/en
Application filed by Itt filed Critical Itt
Publication of CH504103A publication Critical patent/CH504103A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658Vertical bipolar transistor in combination with resistors or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743Making of internal connections, substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
CH1733669A 1968-11-26 1969-11-21 Method of contacting the zone of a monolithic solid-state circuit CH504103A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19681811019 DE1811019C3 (en) 1968-11-26 Method for contacting a semiconductor zone located on the surface of a monolithic solid-state circuit

Publications (1)

Publication Number Publication Date
CH504103A true CH504103A (en) 1971-02-28

Family

ID=5714381

Family Applications (1)

Application Number Title Priority Date Filing Date
CH1733669A CH504103A (en) 1968-11-26 1969-11-21 Method of contacting the zone of a monolithic solid-state circuit

Country Status (4)

Country Link
CH (1) CH504103A (en)
FR (1) FR2024284A1 (en)
GB (1) GB1240256A (en)
NL (1) NL6917817A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58223345A (en) * 1982-06-21 1983-12-24 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
FR2024284A1 (en) 1970-08-28
GB1240256A (en) 1971-07-21
NL6917817A (en) 1970-05-28
DE1811019B2 (en) 1971-01-21
DE1811019A1 (en) 1970-05-21

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Legal Events

Date Code Title Description
PL Patent ceased