CH497748A - Schaltungsanordnung für die Durchführung der Addition und/oder Subtraktion einstelliger Dualzahlen - Google Patents
Schaltungsanordnung für die Durchführung der Addition und/oder Subtraktion einstelliger DualzahlenInfo
- Publication number
- CH497748A CH497748A CH1019369A CH1019369A CH497748A CH 497748 A CH497748 A CH 497748A CH 1019369 A CH1019369 A CH 1019369A CH 1019369 A CH1019369 A CH 1019369A CH 497748 A CH497748 A CH 497748A
- Authority
- CH
- Switzerland
- Prior art keywords
- subtraction
- addition
- circuit arrangement
- binary numbers
- digit binary
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Optimization (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4603568A JPS5531500B1 (enExample) | 1968-07-03 | 1968-07-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CH497748A true CH497748A (de) | 1970-10-15 |
Family
ID=12735769
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CH1019369A CH497748A (de) | 1968-07-03 | 1969-07-03 | Schaltungsanordnung für die Durchführung der Addition und/oder Subtraktion einstelliger Dualzahlen |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US3646332A (enExample) |
| JP (1) | JPS5531500B1 (enExample) |
| CH (1) | CH497748A (enExample) |
| FR (1) | FR2012226A1 (enExample) |
| GB (1) | GB1242027A (enExample) |
| NL (1) | NL6910108A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3723760A (en) * | 1971-11-29 | 1973-03-27 | Bell Canada Northern Electric | Transmission gating circuit |
| US4463439A (en) * | 1982-05-17 | 1984-07-31 | International Business Machines Corporation | Sum and carry outputs with shared subfunctions |
| FR2528596A1 (fr) * | 1982-06-09 | 1983-12-16 | Labo Cent Telecommunicat | Cellule d'addition binaire a trois entrees a propagation rapide de la somme, realisee en circuit integre |
| US4523110A (en) * | 1983-09-30 | 1985-06-11 | Mostek Corporation | MOSFET sense amplifier circuit |
| US4718034A (en) * | 1984-11-08 | 1988-01-05 | Data General Corporation | Carry-save propagate adder |
| US5995420A (en) * | 1997-08-20 | 1999-11-30 | Advanced Micro Devices, Inc. | Integrated XNOR flip-flop for cache tag comparison |
| US7085796B1 (en) * | 2000-06-08 | 2006-08-01 | International Business Machines Corporation | Dynamic adder with reduced logic |
| US7991820B1 (en) | 2007-08-07 | 2011-08-02 | Leslie Imre Sohay | One step binary summarizer |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL222924A (enExample) * | 1956-12-03 | |||
| US3022951A (en) * | 1957-05-14 | 1962-02-27 | Ibm | Full adder |
| US3100838A (en) * | 1960-06-22 | 1963-08-13 | Rca Corp | Binary full adder utilizing integrated unipolar transistors |
| US3196261A (en) * | 1963-01-09 | 1965-07-20 | David H Schaefer | Full binary adder |
-
1968
- 1968-07-03 JP JP4603568A patent/JPS5531500B1/ja active Pending
-
1969
- 1969-06-27 US US837240A patent/US3646332A/en not_active Expired - Lifetime
- 1969-07-02 NL NL6910108A patent/NL6910108A/xx unknown
- 1969-07-02 FR FR6922350A patent/FR2012226A1/fr active Pending
- 1969-07-03 GB GB33614/69A patent/GB1242027A/en not_active Expired
- 1969-07-03 CH CH1019369A patent/CH497748A/de not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| DE1933873B2 (de) | 1976-10-28 |
| US3646332A (en) | 1972-02-29 |
| DE1933873A1 (de) | 1970-01-08 |
| FR2012226A1 (enExample) | 1970-03-13 |
| JPS5531500B1 (enExample) | 1980-08-19 |
| GB1242027A (en) | 1971-08-11 |
| NL6910108A (enExample) | 1970-01-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PL | Patent ceased |