CH490515A - Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrate - Google Patents
Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrateInfo
- Publication number
- CH490515A CH490515A CH1636267A CH1636267A CH490515A CH 490515 A CH490515 A CH 490515A CH 1636267 A CH1636267 A CH 1636267A CH 1636267 A CH1636267 A CH 1636267A CH 490515 A CH490515 A CH 490515A
- Authority
- CH
- Switzerland
- Prior art keywords
- poly
- pattern
- electrically insulating
- monocrystalline substrate
- producing crystalline
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/04—Coating on selected surface areas, e.g. using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH1636267A CH490515A (en) | 1967-11-22 | 1967-11-22 | Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrate |
DE19681806578 DE1806578A1 (en) | 1967-11-22 | 1968-11-02 | Process for the production of crystalline deposits in the form of a pattern on an electrically insulating single-crystal substrate |
GB1250201D GB1250201A (en) | 1967-11-22 | 1968-11-05 | |
FR1592287D FR1592287A (en) | 1967-11-22 | 1968-11-18 | |
NL6816693A NL6816693A (en) | 1967-11-22 | 1968-11-22 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CH1636267A CH490515A (en) | 1967-11-22 | 1967-11-22 | Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
CH490515A true CH490515A (en) | 1970-05-15 |
Family
ID=4416688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CH1636267A CH490515A (en) | 1967-11-22 | 1967-11-22 | Process for producing crystalline deposits in the form of a pattern on an electrically insulating amorphous, poly- or monocrystalline substrate |
Country Status (5)
Country | Link |
---|---|
CH (1) | CH490515A (en) |
DE (1) | DE1806578A1 (en) |
FR (1) | FR1592287A (en) |
GB (1) | GB1250201A (en) |
NL (1) | NL6816693A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4477308A (en) * | 1982-09-30 | 1984-10-16 | At&T Bell Laboratories | Heteroepitaxy of multiconstituent material by means of a _template layer |
FR2572219B1 (en) * | 1984-10-23 | 1987-05-29 | Efcis | METHOD FOR MANUFACTURING INTEGRATED CIRCUITS ON AN INSULATING SUBSTRATE |
GB2183090B (en) * | 1985-10-07 | 1989-09-13 | Canon Kk | Method for selective formation of deposited film |
JPH0732124B2 (en) * | 1986-01-24 | 1995-04-10 | シャープ株式会社 | Method for manufacturing semiconductor device |
JPH0828357B2 (en) * | 1986-04-28 | 1996-03-21 | キヤノン株式会社 | Method of forming multilayer structure |
US5427630A (en) * | 1994-05-09 | 1995-06-27 | International Business Machines Corporation | Mask material for low temperature selective growth of silicon or silicon alloys |
-
1967
- 1967-11-22 CH CH1636267A patent/CH490515A/en not_active IP Right Cessation
-
1968
- 1968-11-02 DE DE19681806578 patent/DE1806578A1/en active Pending
- 1968-11-05 GB GB1250201D patent/GB1250201A/en not_active Expired
- 1968-11-18 FR FR1592287D patent/FR1592287A/fr not_active Expired
- 1968-11-22 NL NL6816693A patent/NL6816693A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
DE1806578A1 (en) | 1969-06-12 |
GB1250201A (en) | 1971-10-20 |
NL6816693A (en) | 1969-05-27 |
FR1592287A (en) | 1970-05-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PL | Patent ceased |