CH453428A - Schaltungsanordnung zur Feststellung des Empfangs einer Mehrzahl von Signalen in einer vorbestimmten Reihenfolge - Google Patents

Schaltungsanordnung zur Feststellung des Empfangs einer Mehrzahl von Signalen in einer vorbestimmten Reihenfolge

Info

Publication number
CH453428A
CH453428A CH330567A CH330567A CH453428A CH 453428 A CH453428 A CH 453428A CH 330567 A CH330567 A CH 330567A CH 330567 A CH330567 A CH 330567A CH 453428 A CH453428 A CH 453428A
Authority
CH
Switzerland
Prior art keywords
receipt
signals
determining
circuit arrangement
predetermined order
Prior art date
Application number
CH330567A
Other languages
English (en)
Inventor
Reszka Alfons
Original Assignee
Teletype Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teletype Corp filed Critical Teletype Corp
Publication of CH453428A publication Critical patent/CH453428A/de

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02Comparing digital values
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L15/00Apparatus or local circuits for transmitting or receiving dot-and-dash codes, e.g. Morse code
    • H04L15/24Apparatus or circuits at the receiving end
    • H04L15/26Apparatus or circuits at the receiving end operating only on reception of predetermined code signals, e.g. distress signals, party-line call signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CH330567A 1966-04-07 1967-03-07 Schaltungsanordnung zur Feststellung des Empfangs einer Mehrzahl von Signalen in einer vorbestimmten Reihenfolge CH453428A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US540921A US3399351A (en) 1966-04-07 1966-04-07 Sequence detection circuit

Publications (1)

Publication Number Publication Date
CH453428A true CH453428A (de) 1968-06-14

Family

ID=24157464

Family Applications (1)

Application Number Title Priority Date Filing Date
CH330567A CH453428A (de) 1966-04-07 1967-03-07 Schaltungsanordnung zur Feststellung des Empfangs einer Mehrzahl von Signalen in einer vorbestimmten Reihenfolge

Country Status (8)

Country Link
US (1) US3399351A (de)
BE (1) BE696692A (de)
CH (1) CH453428A (de)
DE (1) DE1512588A1 (de)
FR (1) FR1514593A (de)
GB (1) GB1160148A (de)
NL (1) NL6703274A (de)
SE (1) SE317704B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3566144A (en) * 1968-02-13 1971-02-23 Motorola Inc Code sequence detection
US3808544A (en) * 1972-03-28 1974-04-30 Nat Res Dev Sequential machines
US4096468A (en) * 1972-07-31 1978-06-20 Chrysler Corporation Solid state sequence logic circuit
US3860904A (en) * 1972-07-31 1975-01-14 Chrysler Corp Sequencing belt and seat warning system with vehicle start inhibit
US3899665A (en) * 1974-01-18 1975-08-12 Gte Automatic Electric Lab Inc Timing error detection circuit
US4023109A (en) * 1975-08-14 1977-05-10 The Van Epps Design And Development Co., Inc. Sequence control system with timed operations
US4054950A (en) * 1976-04-29 1977-10-18 Ncr Corporation Apparatus for detecting a preamble in a bi-phase data recovery system
US4218658A (en) * 1977-10-17 1980-08-19 Moeller Charles R Non-contemporaneous logic element and method for synthesizing a condition which represents a sequence
US4144448A (en) * 1977-11-29 1979-03-13 International Business Machines Corporation Asynchronous validity checking system and method for monitoring clock signals on separate electrical conductors
FR2539372A1 (fr) * 1983-01-13 1984-07-20 Alsthom Atlantique Systemes de modulation pour circuits de voie ferroviaires
US4698829A (en) * 1985-03-12 1987-10-06 Pitney Bowes Inc. Monitoring system for verifying that an input signal is toggling at a minimum frequency
US5590159A (en) * 1995-02-07 1996-12-31 Wandel & Goltermann Technologies, Inc. Digital data sequence pattern filtering

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2984789A (en) * 1958-08-13 1961-05-16 Bell Telephone Labor Inc Pulse monitoring circuit
US3028552A (en) * 1960-04-20 1962-04-03 Ibm Frequency shifting clock
US3189835A (en) * 1961-05-01 1965-06-15 Anelex Corp Pulse retiming system
US3097340A (en) * 1961-05-31 1963-07-09 Westinghouse Electric Corp Generating system producing constant width pulses from input pulses of indeterminate height and duration
US3287650A (en) * 1964-01-29 1966-11-22 William J Achramowicz Pulse train generator employing triggered self-recirculating pulse-circuit and counter producing synchronizable but independent output pulsetrain of selectable length

Also Published As

Publication number Publication date
GB1160148A (en) 1969-07-30
DE1512588A1 (de) 1969-02-20
US3399351A (en) 1968-08-27
BE696692A (de) 1967-09-18
SE317704B (de) 1969-11-24
FR1514593A (fr) 1968-02-23
NL6703274A (de) 1967-10-09

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