CH443427A - Process for manufacturing electrical components or assemblies - Google Patents

Process for manufacturing electrical components or assemblies

Info

Publication number
CH443427A
CH443427A CH749663A CH749663A CH443427A CH 443427 A CH443427 A CH 443427A CH 749663 A CH749663 A CH 749663A CH 749663 A CH749663 A CH 749663A CH 443427 A CH443427 A CH 443427A
Authority
CH
Switzerland
Prior art keywords
assemblies
electrical components
manufacturing electrical
manufacturing
components
Prior art date
Application number
CH749663A
Other languages
German (de)
Inventor
Karl Dr Siebertz
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH443427A publication Critical patent/CH443427A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physical Vapour Deposition (AREA)
CH749663A 1962-07-20 1963-06-17 Process for manufacturing electrical components or assemblies CH443427A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1962S0080503 DE1165700C2 (en) 1962-07-20 1962-07-20 Process for manufacturing components or assemblies

Publications (1)

Publication Number Publication Date
CH443427A true CH443427A (en) 1967-09-15

Family

ID=7508916

Family Applications (1)

Application Number Title Priority Date Filing Date
CH749663A CH443427A (en) 1962-07-20 1963-06-17 Process for manufacturing electrical components or assemblies

Country Status (5)

Country Link
CH (1) CH443427A (en)
DE (1) DE1165700C2 (en)
FR (1) FR1378052A (en)
GB (1) GB978984A (en)
NL (1) NL294779A (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7413977A (en) * 1974-10-25 1976-04-27 Philips Nv APPLICATION OF A CONDUCTOR LAYER PATTERN WITH PARTS LOCATED AT A MINIMUM DISTANCE, ESPECIALLY IN THE MANUFACTURE OF SEMI-CONDUCTOR DEVICES.
US4100313A (en) * 1975-10-28 1978-07-11 Rca Corporation Process for forming an optical waveguide
JPS54103552A (en) * 1978-02-01 1979-08-15 Hitachi Electronics Pattern formation method
US4469719A (en) * 1981-12-21 1984-09-04 Applied Magnetics-Magnetic Head Divison Corporation Method for controlling the edge gradient of a layer of deposition material
US4536419A (en) * 1983-03-10 1985-08-20 Hitachi, Ltd. Method for forming tapered films
EP0118576B1 (en) * 1983-03-11 1987-12-02 Hitachi, Ltd. Method for forming thin films
DE102017105374A1 (en) * 2017-03-14 2018-09-20 Aixtron Se Device for depositing a structured layer on a substrate and method for setting up the device
DE102017105379A1 (en) 2017-03-14 2018-09-20 Aixtron Se Substrate holder arrangement with mask carrier
WO2019129364A1 (en) * 2017-12-29 2019-07-04 Microsoft Technology Licensing, Llc Fabrication process using vapour deposition through a positioned shadow mask

Also Published As

Publication number Publication date
FR1378052A (en) 1964-11-13
GB978984A (en) 1965-01-01
NL294779A (en)
DE1165700C2 (en) 1964-09-24
DE1165700B (en) 1964-03-19

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