CH429246A - Schaltungsanordnung zur Bestimmung der Parität einer Summenbitgruppe - Google Patents

Schaltungsanordnung zur Bestimmung der Parität einer Summenbitgruppe

Info

Publication number
CH429246A
CH429246A CH237864A CH237864A CH429246A CH 429246 A CH429246 A CH 429246A CH 237864 A CH237864 A CH 237864A CH 237864 A CH237864 A CH 237864A CH 429246 A CH429246 A CH 429246A
Authority
CH
Switzerland
Prior art keywords
parity
determining
circuit arrangement
bit group
sum bit
Prior art date
Application number
CH237864A
Other languages
English (en)
Inventor
Richard Geller Alan
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH429246A publication Critical patent/CH429246A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
CH237864A 1963-02-27 1964-02-26 Schaltungsanordnung zur Bestimmung der Parität einer Summenbitgruppe CH429246A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US261351A US3287546A (en) 1963-02-27 1963-02-27 Parity prediction apparatus for use with a binary adder

Publications (1)

Publication Number Publication Date
CH429246A true CH429246A (de) 1967-01-31

Family

ID=22992913

Family Applications (1)

Application Number Title Priority Date Filing Date
CH237864A CH429246A (de) 1963-02-27 1964-02-26 Schaltungsanordnung zur Bestimmung der Parität einer Summenbitgruppe

Country Status (6)

Country Link
US (1) US3287546A (de)
BE (1) BE644448A (de)
CH (1) CH429246A (de)
DE (1) DE1281193B (de)
FR (1) FR1383524A (de)
NL (1) NL140636B (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3287546A (en) * 1963-02-27 1966-11-22 Ibm Parity prediction apparatus for use with a binary adder
DE1524268B1 (de) * 1966-06-04 1970-07-02 Zuse Kg Anordnung zur Fehlerermittlung in Rechenwerken
US3531631A (en) * 1967-01-11 1970-09-29 Ibm Parity checking system
US3555255A (en) * 1968-08-09 1971-01-12 Bell Telephone Labor Inc Error detection arrangement for data processing register
US3699323A (en) * 1970-12-23 1972-10-17 Ibm Error detecting and correcting system and method
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection
US4224680A (en) * 1978-06-05 1980-09-23 Fujitsu Limited Parity prediction circuit for adder/counter
US4879675A (en) * 1988-02-17 1989-11-07 International Business Machines Corporation Parity generator circuit and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT557030A (de) * 1955-08-01
US3036770A (en) * 1958-08-05 1962-05-29 Ibm Error detecting system for a digital computer
GB862281A (en) * 1958-10-22 1961-03-08 Ncr Co Parity bit generator
US3078039A (en) * 1960-06-27 1963-02-19 Ibm Error checking system for a parallel adder
US3287546A (en) * 1963-02-27 1966-11-22 Ibm Parity prediction apparatus for use with a binary adder

Also Published As

Publication number Publication date
NL6401868A (de) 1964-08-28
FR1383524A (fr) 1964-12-24
NL140636B (nl) 1973-12-17
BE644448A (de) 1964-06-15
DE1281193B (de) 1968-10-24
US3287546A (en) 1966-11-22

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