CH422047A - Process for synchronizing the encryption and decryption of messages displayed in pulses - Google Patents

Description

  

  Method for synchronizing the encryption and decryption of messages displayed in the form of pulses. The invention relates to a method for synchronizing the encryption and decryption of messages in the form of pulses, in which the message clear pulses are mixed with key pulses on the transmitting side.

       transmitted using a modulation and recovered on the receiving side by mixing with identical key pulses and in which these are transmitted and received by means of identical rules <b> ever </B> one.

       Key pulse generator generated key pulse sequences have a pseudo-random character, the key pulse sequences being determined by the initial states of the key pulse generators',

   which initial states are generated using at least one secret basic key and preferably at least one additional key and where the encryption and decryption of the messages displayed in the form of pulses and the sequence of the key pulse generators are controlled by a clock at the send and receive sides.



       Known systems that work according to this method consist of a clear information clear pulse converter, a key pulse generator and a cipher mixer on the transmission side.



  The clear information / clear pulse converter converts the information into a binary coded clear pulse sequence. This clear pulse sequence is fed into the cipher mixer, which is fed simultaneously from the key pulse generator with a key pulse sequence in binary form. In the cipher mixer, the clear pulses are encrypted with the key pulses, this being preferably carried out by modulo-2 addition.

   The cipher pulse sequence thus obtained (mixture of the clear pulse sequence with the key pulse sequence) is transmitted to the information receiver (receiving end) using a suitable type of modulation. On the receiving side, analog devices are necessary, which, however, sometimes work in reverse in their function.

   These are: demodulator, deciphering mixer, key impulse, generator and clear impulse clarification donor.



  The received, demodulated cipher pulse sequence as well as the key pulse sequence of the receiving-side key pulse generator are fed to the deciphering mixer, which recovers the clear pulse sequence from these two pulse sequences.

   Identical key impulses must of course be used for encryption and decryption, <b> d </B>. H. the key pulse generator on the sending and receiving side must work in key synchronization.

   The clear pulse sequence emitted by the decryption mixer is converted back into the original information form by the Marimpul, s-Klarinfo, rmations- ivandler.



  The key pulse generators used in such known methods are identically constructed devices of mechanical, electromechanical and / or electronic type. They have a large number of key formation elements that can be changed in their state and mutual assignment, for example cam disks, permutation switches and / or electronic elements, etc.

   The key impulse is therefore dependent on the structure and interaction of the individual elements and on the position of these elements at the start of the message transmission. This so-called initial state must be set at the transmitter and receiver before the transmission begins, whereupon the transmission and reception-side key pulse generators then deliver identical key pulse sequences with synchronous start and sequence.

   The key pulse sequences have a pseudo-random character; H. similar statistical distribution of the key impulses as correct ;: random sequences, but determined and machine-made.



       Normally, the initial states of the key pulse generator are determined by a secret basic key as well as by a (non-secret) additional key which, for example, changes from transmission to overload.

   B. not encrypted before each transmission is transmitted :. However, it can also be used without an additional key, i.e. H. be managed with a secret basic key alone, provided that it is changed sufficiently often.



       Suitable bowl pulse generators are described in detail in, for example, Patent Nos. 392,617 and 402,937.



  In the case of methods of the present type, as already mentioned: a precise key synchronization of the sending and receiving-side keys: limpull generators are required, i.e. H. On the sending and receiving side, the same key pulses must be sent to the cipher mixer or decipher mixer at the same time.

   Strictly speaking, the key pulse generator on the receiving end must run after the signal (cipher pulses) from the cipher mixer on the transmitter side to the decipher mixer on the receiver side for the duration of the signal (cipher pulses). This lag occurs automatically, however, since the signals which are used to produce the key synchronization of the key pulse generators also have this transit time.



  Previously known methods or devices for encrypted message transmission use additional synchronization independent of the transmitted information content to maintain the key synchronization between the sending and receiving side key pulse generators. <B> impulses. </B>



  In one of these known methods, the so-called start-stop system, start pulses are used for synchronization (as so-called synchronization pulses). The clear information follows each start impulse as a finer one:

      or larger number of information pulses (information bits). The time span between the last information bit and the next start pulse is known as the stop pulse. This method is used, for example, in the known telex transmission.

    In the case of encrypted transmission, these start pulses can be used to synchronize the key pulse generators.



  For each start pulse, the key pulse generator on the sending and receiving side must then emit a number of key pulses - corresponding to the number of bits in the KTar pulse combination (key pulse combination), with which the clear pulses are encrypted. Start and stop impulses are transmitted unencrypted.



  According to the prerequisite, the sending and receiving side key pulse generators have been brought into the same initial state before the message transmission begins. Thus, on the sending and receiving side, for each start impulse from the two key impulse generators, one identical key impulse combination is generated, which is used for encryption or decryption.

         In the same way, the key pulse generators on the sending and receiving side are advanced by one or more steps by each start pulse.



  This known method has several disadvantages. Falling interference or fading on the transmission path can trigger the key pulse generator on the receiving end at the wrong time and switch on or off.

   prevent the correct triggering and further shading. In such a case, the key pulse combinations used for encryption and decryption are no longer identical, and encrypted transmission is therefore impossible without prior correction of the states of the key pulse generators on the sending or receiving side.

   Another disadvantage is that the position of the start and stop pulses and, of course, the position of the information pulses can be determined relatively easily by unauthorized persons.

   On the one hand, this makes it easier for unauthorized people to decipher the secret message and, on the other hand, it gives them the opportunity to disrupt the synchronism of the key pulse generators on the transmission and reception side by interspersing start pulses on the transmission path and thus make encrypted transmission impossible.



  According to another known proposal, the so-called synchronous system, transmitter and receiver -3nit are each equipped with a clock of the same frequency as possible, with which the run (advance) of the key pulse generators and the encryption and decryption are controlled.

    At the start. During the transmission, the key pulse generators on the sending and receiving sides are initially set to the same initial state:. It then follows during:

  an initial phase synchronizing the receiving-side clock with the transmitting-side and simultaneously switching on the receiving and isendeis @ eit'gen key pulse generator so that both emit identical key pulse sequences. During the transmission, the clocks switch the key:

  The pulse generators continue to run, with the identical key pulse sequences on the transmitter and receiver side being used to encrypt and decrypt the clear pulse combinations.

   The clear! Pulse combinations must be entered in the cipher mixer or decipher mixer with the same rate as the key pulse combinations. In telex operation z.

   B. the frequency of the clock generator can be selected so that between RTI ID = "0002.0215" WI = "7" HE = "4" LX = "1879" LY = "2493"> two successive clock pulses (synchronizing pulse:

  e) the combination of 5 information bits (clear information) of a letter is sent. It is clear that in this case the clock frequency must be at least as large as the fastest sequence of letters on the teletype.

   In addition, this usually requires a buffer synchronous memory, which is connected upstream of the cipher mixer on the transmission side and feeds the clear pulse combination with the correct phase position into the cipher mixer.

    The unencrypted synchronization pulses are used to maintain synchronism during transmission. For this purpose, in a circuit that is as insensitive to interference as possible, the phase position of the transmitted synchronization pulses in the receiver is compared with that of the receiver-side clock and any phase difference is compensated for.

   With this the key tracking of the sending and receiving side key impulses is guaranteed for a certain period of time in the event of disturbances or interruption of the transmission path, but this method also has the disadvantage

      that unauthorized persons can easily trigger an entry into the pulse synchronism or the correctly synchronized receiver-side clock from its originally correct phase position by interspersing synchronization pulses with a frequency slightly deviating from the transmitted synchronization pulses. can move away, making encrypted transmission impossible.

   Furthermore, the position determination of the information pulses between them is facilitated by the recognizability of the periodically emitted synchronization pulses.



  The described disadvantages of the known methods or devices are avoided according to the invention in that, for step synchronization of the transmitting and receiving-side key pulse generators, part of the key pulse sequence generated by the key pulse generator of the transmitter is transmitted to the receiver and there with the

      Key pulse generator on the catch side generated key pulse sequence over an interval of several pulses, for example by pulsed modulo-2 addition or the like arithmetic operation, a comparison value sequence and with this at least.

       a correlation factor is formed, which assumes an optimal value at step synchronism, and that the mutual relative position of the two key pulse sequences is continuously changed and a further correlation factor is formed for each of these positions, the resulting sequence of correlation factors for controlling the Step synchronization is used.

    



  The main idea of the present invention is therefore to use the correlation properties of random sequences, known per se, to synchronize the encryption and decryption.

   This is explained in detail below. The main advantage of the method according to the invention is that the synchronization takes place directly with the key pulse sequences having pseudo-random character and not by means of special periodic synchronization pulses. This fundamental difference compared to the known state of the art ensures perfect friend-foe recognition.

        tion. In particular, it is not possible for unauthorized persons to disturb the entry into the key synchronization or to pull the receiver away from the correct phase position after this synchronization has been established.

   By avoiding special, unencrypted, transmitted synchronization pulses and the resulting recognition of associated clear pulse combinations, the encryption strength can be increased.



  The method according to the invention and a system operating according to this method are explained in more detail below with reference to the drawing, for example. There are shown: FIG. 1 the basic structure of a system operating according to the new method, its block diagram, FIG. 2 diagrams, two types of modulation (b, c) for the transmission of the cipher pulse sequence (a), FIGS. 3 to 5 different reciprocal positions of the <I> (a) </I> and on the receiving side <I> (b)

   Key impub sequence in diagram representation, FIGS. 6 to 8 diagrams to explain the correlation principle applied according to the invention, FIGS. 9a and 9b time plans for two entry possibilities in the step synchronism, FIGS. 10 to 12 diagrams for Explanation of the automatic step synchronization, FIG. 13 shows a device for performing the step synchronization according to the invention,

         14 to 17 four basic constellations of the signals that can occur in the step synchronization according to FIG. 13 in the form of diagrams, FIG. 18 shows a complete system for implementing the method according to the invention and a block diagram,

         19 diagrams to explain the mode of action of the step synchronization device designated Sy I in FIG. 18, FIG. 20 a further variant of the step synchronization device Sy I of FIG. 18, FIG. 21 diagrams to explain the mode of action of the circuit arrangement according to Fig. 20.

    The interaction of the various parts of a system for encrypted message transmission in synchronous operation with the correlation synchronization according to the invention will first be explained on the basis of the block diagram in FIG. Such systems are used for encrypted transmission of binary coded information, e. B. data, speech in pulse code modulation, telex signals, etc.



  The clear information to be transmitted is fed to the cipher mixer 2 by the clear information clear pulse converter 1 in the form of a binary-coded clear pulse sequence. At the same time, the cipher mixer 2 is fed with e.inez key pulse sequence from the key pulse generator 4. The cipher mixer 2 mixes the clear pulses with the key pulses, this preferably being done by means of mod'ulo-2 addition.

        The cipher pulses or cipher pulse sequences generated in this way reach the modulator 3. In the modulator 3, the cipher pulse sequence is converted by the type of modulation suitable for the transmission, e.g. B. amplitude modulation, frequency modulation, etc.



  These two types of modulation mentioned are shown as examples in FIG. Line a represents a piece of a cipher pulse train in binary form,

   how ie is output from the cipher mixer 2. In line b, the same cipher pulse sequence is amplitud'en- modulated and in line c is shown frequency-modulated. In the case of amplitude modulation, the binary L corresponds to an alternating voltage with the frequency f and the amplitude ü and the binary 0 corresponds to the voltage 0.

    With frequency modulation, an alternating voltage of constant amplitude is sent out continuously, but the frequency is changed. For example, let the binary 0 be the frequency f <I> o </I> and the binary <I> L </I> assigned the frequency f 1.



  The transmitted signal (cipher pulse sequence) reaches the demodulator 6 on the receiving side, which again sends the cipher pulse sequence in the form of binary direct current pulses to the deciphering mixer 7.

       At the same time, the deciphering mixer 7 is paged with the same key pulse sequence as the cipher mixer 2 on the transmitting side, which is generated by the receiving-side key pulse generator 9.

   In the decryption mixer 7, the decryption of the received cipher pulse sequence takes place and the clear pulse sequence recovered in the process is fed to the clear pulse clear signal converter 8, which converts it back into the original information form.



       The system works in synchronous mode, i.e. the sequence of the key pulse sequence of the transmitting and receiving side key pulse generators is controlled by a clock 5 and 10 respectively. The clock generator 5 on the transmitting side normally runs at a constant clock frequency,

          while the clock in the synchronization unit 10 of the receiving side has to be brought into the key synchronization and afterwards has to be synchronized.

   For this purpose, during the correlation synchronization of the synchronization unit 10, the transmitted key pulse sequence on the transmission side is supplied via line 11 and the self-produced, reception-side key pulse sequence is supplied via line 12,

      which uses these two criteria to independently establish the final balance.



  The key pulses of the key pulse generator 4 on the transmitter side and the clear pulses of the clear signal / clear pulse converter 1 must be in phase. The phase position of the key pulses is determined by the clock 5.

   It is therefore necessary that the clear pulses are fed into the cipher mixer 2 with the same phase position. This he follows in a system according to the block diagram of FIG. 1 in that the Marimpulse of Klarsi'gnal- Klarimpulswandlers 1 are called by the clock generator 5 from.

   In cases where this variant is not possible, a so-called buffer synchronous memory is connected between the clear signal / clarin converter 1 and the cipher mixer 2.

   This saves the clear signals or MärimpAwandler emitted clear pulses for a short time and sends them - controlled by the clock generator 5 - with the correct phase position to the cipher mixer 2.

      The entry into the key synchronization occurs in the career synchronization in two phases.



  After completion of the first phase, which is referred to as step synchronization, the key pulse generator on the sending and receiving side each run on its own clock, whereby. the two key pulse sequences can have a maximum shift of one bit length b with respect to one another, "which is referred to as a step phase shift or also a step phase error.

       These ratios will be explained in more detail below with reference to FIGS. 3 and 4.



  Fig. 3 shows in lines a and <I> b </I> a transmitting and receiving key pulse sequence, which are step-synchronized.

   The step phase shift v between the two final pulse trains is smaller than the bit length b (also called the step length or pulse length).

       The numbers above the individual key pulses are intended to indicate after which step of the key pulse generator from a specific, set initial state, this key pulse has been delivered. 4 shows two key pulse sequences that are not step-synchronized.



  To establish the step synchronization RTI ID = "0004.0235" WI = "27" HE = "4" LX = "1159" LY = "1592"> (step synchronization), the correlation factor between the synchronization information content of a part of the sending and receiving side key pulse sequence is used. The properties of this <RTI

   ID = "0004.0250"> Correction factor and the application for controlling the step sequence are described in detail below.



  During the second phase, the so-called step phase synchronization, subsequent to the step synchronization, the still existing step phase error between the sending and receiving key pulse sequences is corrected. With two key pulse trains which are step-phase-synchronized,

   there is no shift between the send. and key pulse sequence at the receiving end. The latter case is shown in FIG.



  To establish the step phase synchronization (step phase synchronization), the correlation function value between the time functions of a part of the sending and receiving end final pulse sequences is used during correlation synchronization, which will be discussed in detail later.



  Due to the inaccuracies of the clocks, albeit small ones, the key pulse sequences on the sending and receiving sides are shifted again over time. This phase shift is also corrected by the step phase synchronization.



  While the information is being transmitted, the transmission-side key pulse sequence is not available on the receiving side and '. thus a step phase error that may arise during the transmission of information cannot be corrected either.

   However, since very precise clock generators, preferably quartz-controlled clock generators, are used on the sending and receiving side, it is easily possible to transmit information during a certain time without step phase synchronization. During the natural and - if necessary - artificially generated breaks in the transmission of information, only the transmission <RTI

   ID = "0005.0028"> side key pulse sequence transmitted, and the receiving station has time to correct the step phase errors that have arisen in the meantime.



  Subsequently, the correlation properties of random sequences or pseudo-random sequences will be discussed, under which; The term includes the key pulse sequences of key pulse generators, as used in correlation asynchronization.



  The correlation factor r of two identical and temporally coincident random sequences is one, whereas this factor tends towards zero in the case of non-identical or temporally inconsistent sequences. The same applies to so-called pseudo-random sequences. By this one understands sequences with a similar static distribution like correct random sequences,

    but determined and machine-made.



  Strictly mathematically, the correction factor is formed from two successive values according to the appropriate formula:
EMI0005.0069
    Here v = x <I> - x </I> and w = y <I> - y, </I> where x and y are the arithmetic mean values of the sequences x and y. For electrical signals, x and y are dile DC components.



  However, only this is of technical importance! Short-term correlation, in which the interval in which the mean value is formed has a finite size. The formula for the correlation factor thus takes the following form:
EMI0005.0086
    With the application of the correlation principle used here, the values are in binary form.

   You can therefore only adopt two states, the binary zero = 0 and the binary one = L. If one evaluates the two states 0 and L with -1 and '+ 1, then both value sequences - assuming random character - have no direct current component (x and y = 0) and the effective value
EMI0005.0098
    is equal to one.

   In this case, the above formula is reduced to the following form:
EMI0005.0102
    As stated above, the correlation factor of two identical sequences is one. This case is shown in FIG. With two uncorrelated sequences, the correlation factor r tends towards zero, as FIG. 7 illustrates.



       If there is the value - if x and y follow as time functions, then the formula (1) changes into the integral form,
EMI0005.0116
    this special formula again only applies to binary signals with a random character and the two states evaluated with + 1 and -1.



       If, y (t) is delayed with a variable, the correlation function yp (z) results:
EMI0005.0127
    With identical time functions, i.e. x - y, the autocorrelation function y (a) according to FIG. 8 results, which has a maximum value with zero shift (z = 0) and is symmetrical,

    The properties of the correlation factor of two value sequences (formula 1) as well as the correlation function (formula 2) described above are used in the described correlation synchronization for executing the step and step phase synchronization.



  In the case of synchronous transmission, as is the case with the subject matter of the invention, the key pulse generators are incremented by a separate clock generator on the transmitting and receiving side with practically the same clock frequency. The period duration of this clock frequency corresponds to the clear pulse length. At the beginning of <RTI

   ID = "0005.0163"> connection establishment thus the task is to bring these two key pulse generators into step synchronization.



       The creation of step synchronization is basically possible in two ways. In both variants, the key pulse generators on the sending and receiving sides are first brought into the same initial state.

   Starting from this initial state, according to the first variant, the clock generators are switched on at the same time in both key pulse generators and one obviously obtains key pulse generators working in step synchronism.

       For example, the receiver clock is switched on before the sender clock. By appropriate selection of the running speed of the receiving-side key pulse sequence, it can always be achieved

   that both key pulse generators will be in the same position at a later point in time. The key impulse sequences intersect in their course.

   In the example assumed above, the receiver clock should be slower than that of the sender. On the receiving side, suitable means are used to determine when this intersection takes place and at this time = point the receiver clock frequency is suddenly switched to that of the transmitter - t. From this moment on, both key pulse generators are in step synchronism.



  The time sequence for the ratios assumed above is shown in the diagram in FIG. 9a. In this diagram, the sequence of the key impulse sequences is plotted on the ordinate axis S over the time axis t.

   The line: SE symbolizes the sequence of the receiver key pulse sequence and the dashed line SS the sequence of the transmitter key pulse sequence. The receiver clock generator and thus the receiver key pulse wave SE begins to run at time t1.

   The transmitter clock generator and thus the transmitter key pulse sequence SS begins to run at time t2. According to the illustration, the receiver clock initially runs more slowly than the transmitter clock. The:

          two lines <I> SS </I> and SE cross at the time <I> t4. </I> At this point in time, the frequency of the receiver clock is suddenly brought into agreement with the frequency of the transmitter clock.



       The constellation before the step synchronization, as shown in Fig. 9a, is referred to as the receiving side before running. In this case, the key pulse generator on the receiving side, counted from an initial state that is the same for both key pulse generators, is in a higher number of steps than the key on the transmitting side before the crossing time t4 is reached:

  pulse generator. In Fig. 9a, for. B. at time t3 the sending-side Scblüsszlimpulsgenerator in the 16th step, while the receiving-string key pulse generator is in the 30th step.



  The reverse case, i.e. H. Continuing on the receiving side is shown in FIG. 9b. In this case, there is the key pulse generator on the receiving end, counting an initial state that is the same for both key pulse generators, before reaching the crossing point.

       t4 in a lower number of steps than the key pulse generator on the transmitter side. In Fig. 9b, for. For example, at the time ts the key pulse generator on the transmitter side is in the 42nd step, while the key pulse generator on the receiver side is in the 27th step.



  With the synchronization according to the invention, the step synchronization takes place according to the second variant, because by means of the correlation, the synchronization time can be clearly detected even in the case of defective transmission-side key pulse sequences.

   This detector works as described below. An interval - the so-called correlation interval zo - consisting of the last n bits, dm the sending or receiving end, is continuously recorded from the sending and receiving end key pulse sequences on the receiving end.

       Receive interval memory, preferably in front of the sliding register, stored and calculated from this the correlation factor according to formula (1). The calculation of this correlation factor takes place in such a way that the information of the same bits of the sending and receiving side correlation interval - so-called value pair - is compared (multiplied) with one another.

            and the correlation factor r is formed by the subsequent summation of this comparison result of all n value pairs. This factor will hover around zero as long as the two intervals are not identical.

   But at the moment when two identical intervals are stored ', <b> d </B>. H. Both key generators are in the same position, the correlation factor r rises abruptly to one.

   With this criterion, i. H. at the. When the correlation factor r rises above a certain, predetermined value, the so-called threshold value <I> SW, </I> the clock generator at the receiving end is switched to the transmit clock frequency. The two key generators continue to run synchronously from this point on.

      After the step synchronization has been established, a step phase shift of a maximum of 1/2 bit can still exist between the two key pulse sequences, since the two clock generators have not yet been synchronized in this regard. This phase error is corrected by means of the jerk phase synchronization, which is described in detail below.



  The size of the threshold value SW depends on the degree of disturbance in the transmission at which the step synchronization should still work properly. If the maximum permissible error rate for correct running-in is q, then are <I> k = q - </I> ra bits disturbed in the correction interval, where k can only be an integer.

   In this case, the correlation factor reaches the value:
EMI0006.0217
    If (k + 1) bits are disturbed, there should be no more run-in. The threshold value SW is thus determined as follows:
EMI0007.0001
    On the other hand, if the threshold value is lower, the probability of a step in a random sequence increases.

   This so-called false run-in probability Wr is calculated
EMI0007.0008
    However, by appropriate choice of the correlation interval length n (bit), any error rates and error rate probabilities are possible.

   Two numerical examples are intended to show this even more precisely, whereby the selection of an extremely high error rate is intended to demonstrate how a run-in into the step synchronism can be made insensitive to interference.



   <I> Example 1 </I> Interval length n = 40 Error rate = 20% k = 8
EMI0007.0024
     <I> Example 2 </I> Interval length n = 60 Error rate = 20% k = 12
EMI0007.0027
    From these two examples it can be seen, among other things, that by increasing the correlation interval length n from 40 to 60 bits, the incorrect entry probability despite the same error rate from 10-4 to 1,

  82 - 10-E sinks.



       The requirement for friend-foe recognition is met by the fact that the key pulse sequence is used directly for entering the step synchronism. This means that an entry is only possible to a counter station that delivers the correct pulse sequence.

   To do this, it is necessary that the key pulse generators assume the same initial state at both stations. The initial state can be generated, for example, by mixing a secret basic key with at least one additional key.

   Another way in which the additional key does not have to be transmitted is the mixture of the secret basic key with an additional date-time key.



  As already mentioned, there can still be a step phase shift of a maximum of 1/2 bit after the step has been run in between the sending and receiving side clock. Furthermore, due to the, albeit very small, inaccuracy of the clock generator over time, a step phase shift can result. These step phase errors of different origins must be corrected.

   This is done in both cases by means of step phase synchronization, as will be explained in more detail below.



  In the described correlation synchronization, the properties of the autocorrelation function (correlation function) shown in FIG. 8 in the range from −1 b to are used for step phase synchronization <I> + 1 b (b </I> = bit length), which has a maximum when there is a phase match (a = 0).

       If the time functions of the key pulse train produced by the transmitter are corrected on the receiving side with the key pulse train generated on the receiver side, a function value is obtained according to the autocorrelation function,

      which depends on the amount of the step phase shift. By shifting the phase of the clock at the receiving end such that the function value reaches its maximum, the step phase error between the transmitter and the receiver clock is made zero.

    In this case, the received key pulses produced on the transmission side exactly match those on the receiving side in terms of phase.



  The advantages of the correlation principle are the friend-foe recognition and the insensitivity to statistically distributed disturbances.



  The friend-foe recognition, i.e. H. not reacting to hostile impulse trains that aim to slowly pull the receiving station out of the step phase synchronization in order to make the transmission of messages impossible, analogous to step synchronization, by using the correct key in order to exert any influence on the step phase synchronization pulse train must be available.

   Since the key pulse sequence is secret, any influence of unauthorized persons on the step phase synchronization is definitely prevented.



       Sbatistically distributed disturbances in the received final pulse train have the effect that the correlation function value can no longer rise to the value one, since the two correlated pulse trains are no longer (100%) identical.

   However, the disturbances do not change the character of the auto-correlation function, <b> d </B>. H. the maximum of this function is always zero at the shift phase shift and the decrease to -1 b and + 1 b remains linear. Only by choosing a sufficiently long integration time is to avoid that the statistical fluctuations of the correlation function value caused by disturbances are kept within sufficiently small limits.

   These fluctuations must be so small that the maximum of the autocorrelation function can be determined with the desired accuracy. In FIG. 8, the auto-correlation function is shown in dashed lines with an average error rate of 25%.



  In the description of a circuit for step phase synchronization, the need for interference will be discussed again with the aid of the figures.



       If the step phase synchronization is to be carried out automatically, since the autocorrelation function - except for the zero point - is ambiguous, the sign of the deviation or the direction of the correction must be determined.

   This is possible for the 2nd time if, for example, the! Received key pulse train - generated on the transmitter side - correlated with two mutually shifted key pulse trains on the receiver side.

       These two key pulse sequences should be symmetrical to the key pulse sequence used for decryption and should preferably have a shift of +1/2 bits and -1/2 bits.

   10 shows three such identical key pulse sequences at the receiving end, where the key pulse sequence of line a is used for deciphering and the other two pulse sequences b and c are required for the phase synchronization. The latter have a phase shift of -1/2 bit or

   +1/2 bit to the pulse sequence of line a. As already mentioned above, the receiving-side key pulse sequences b and c of FIG. 10 are correlated with the received, transmitting-side generated key pulse sequence, and the correlation function values obtained are dabsi,

      those in Figs. 11 and 12 with 1P1 and. V2 are designated, the difference is formed. This difference is, as will be shown with the aid of the following examples, a suitable criterion for the automatic control of the step phase synchronization.



  If the receiving-side key pulse sequence used for decryption (line cc in Fig. 10) is in phase with the received, transmitting-side generated key pulse sequence, the

          both correlation function values ypi and 7p2 are equal and '. thus the difference is zero. These, are plotted in Fig. 12, where the abscissas er, <I> b </I> and c denote the phase positions of the three receiving-side key pulse sequences.



  In Fig. 11 the relationships for lagging receiver clocks, i.e. H. positive step phase shift, shown. As can be read from this figure, the correlation function value ipi is greater than the correlation value y) 2 and so the difference is positive.



       If the receiver clock is leading, <b> d </B>. H. negative step phase shift, as can be readily seen, the relationships are reversed, and thus the difference is negative.



  The criteria for controlling the pulse synchronization are summarized as follows: 1. Pulse synchronous% musi-y @ 2 <I> = 0 </I> (phase shift zero) 2. Receiver clock lagging Vi-zp2> 0 (positive step phase shift) 3.

       Receiver clock leading Vi - 1p2 <0 (negative step phase shift) The two values V1 and w2 are known to be integrals (compare formula 2). Since the difference between two integrals is equal to the integral of the differences, the difference can also be formed before the integration.

   If a fixed integration time is also introduced, the integral can be viewed directly as a normalized mean value. Taking these two aspects into account, the circuit for pulse synchronization shown in FIG. 13 is constructed, which is also used in the block diagram of FIG. 18 and is subsequently described.



       According to the exemplary embodiment shown in FIG. 13 of a circuit for performing the step phase synchronization according to the invention, the two correlation multipliers 806 and 807 on the one hand via the line 805 with the same transmission-side key pulse sequence and on the other hand via the lines 113 and 804 with one each <RTI

   ID = "0008.0205"> Key pulse sequence supplied on the receiving side. In the pulse-synchronized state, the two key pulse sequences on the receiving end have a phase shift of -1/2 bits and +1/2 bits with respect to the transmitting-end key pulse train arriving on line 805. This state is in the diagram in FIG. 14

      recorded, with the lines cc, <I> b, c </I> reproduce the key pulse trains on lines 805, 113, 804. Figures 15-17 show three more RTIID = "0008.0228" WI = "24" HE = "4" LX = "1280" LY = "1976"> constellations. 14 to 17 show the two binary states of the pulse trains of lines a to e, corresponding to the evaluation useful for the correlation,

   again denoted by +1 and -1.



  The correlation multipliers 806, 807 carry out the multiplication of the two key = pulse sequences fed in.

   The product sequences thus formed are shown in lines d and e of FIGS. 14 to 17, respectively. These product sequences reach the differential amplifier 808 via the line 820 or 821, where a new sequence is formed according to the difference between the two product sequences.

   This new pulse sequence is shown in line f of FIGS. 14 to 17, respectively. The new pulse sequence, best referred to as the difference sequence, is integrated in the integrator 809.

       With a defined, constant integration time, the value of the integral corresponds to the difference in the correlation function values between the transmit-side and one receive-side key pulse sequence, and is therefore a measure of the step phase error of the two clock generators participating in the connection.

   This error signal is shown in line h of FIGS. 14 to 17 in each case. The error signal h reaches the "threshold value detector" via line 822 <B> 812, Where there is a comparison with a predetermined threshold value SW which is supplied to the threshold value detector by an 'adjustable threshold value generator 811'.

   The threshold value detector 812 switches the two outputs 813 and 814 according to the following control criteria:
EMI0009.0023
  
    Step phase <SEP> error signal <SEP> states <SEP> the
 <tb> shift <SEP> h <SEP> lines
 <tb> 813 <SEP> 814
 <tb> positive <SEP> <I> h <SEP> SW <SEP> L <SEP> 0 </I>
 <tb> <I> 0 <SEP> SW <SEP>> h> -SW </I> <SEP> 0 <SEP> 0
 <tb> negative <SEP> <I> h <SEP> L- <SEP> SW <SEP> 0 <SEP> L </I> The size of the threshold <I> SW </I> is determined by the requirement that the correlation with any received random pulse may not result in a correction of the step phase position of the clock on the receiving side.

   In this case, the error signal h fluctuates around the value zero, and the threshold value should be chosen so large that it is practically never reached. This case is shown step by step in the time schedule of FIG.



  In the case of the minimal step phase shift that is still to be corrected, however, the error signal h must reach the threshold value SW. Through the integration, the error is continuously added, so that by choosing - a correspondingly long integration time, the error signal h can be achieved for any small minimum step phase error.

    This is also the case if the transmission-side key pulse sequence was disturbed on the transmission path, because the proportion of disturbances in the error signal is zero on average. The timing diagrams of FIGS. 15 and 16 show the case with positive and negative step phase shift, respectively.



  The integration time is determined by periodically setting the initial condition zero of the integrator 809. This is done by a pulse on line 810, which is shown in FIGS. 14 to 17 in each case in line, g. Shortly before a new initial condition is set, the integrator 809 is read or the decisions of the threshold value detector 812 are blanked.

   The gates 816 and 817 are opened by a periodic pulse on the line 815, so that an aE due correction signal on the line 813 or 814 via line 818 or 819 carries out the corresponding correction of the receiving-side clock with known means.

   A pulse on line 818 causes a negative shift in the phase of the receiver clock, whereas a pulse on line 819 causes a positive shift.

    In FIGS. 14 to 17, the read pulse on line 815 is in line i and the resulting correction pulses on lines 818 and 819 are in lines <I> k </I> and <I> l </I> shown.



  It should be noted that in the above-described arrangement according to FIG. 13, the step phase shift is not recorded quantitatively and the correction takes place in constant cuts. The correction of a larger step phase shift, e.g.

   B. after the step is thus carried out in several successive measurements and correction steps until the entire step phase shift is corrected.



  A step phase synchronization, as described with reference to FIG. 13, can regulate a step phase shift of up to 11/2 bits. This area is larger than necessary, because after the step in there is a step phase shift of maxianal 1 / _q bit and with a writing phase shift:

  If more than 1 bit, no more messages can be transmitted.



  The step phase synchronization according to FIG. 13 only works when the transmission-side key pulse sequence is transmitted. If, on the other hand, messages are to be transmitted in encrypted form, the key pulse sequence on the sending side is not permanently available on the receiving side.

   However, since the clock generators have to be very precise (crystal-controlled), it is easily possible to transmit messages for a certain time without the step phase synchronization having to work.

       During the natural and, if necessary, artificially generated transmission pauses, the subsequent synchronization of the small step phase shift that occurred during the message transmission takes place. At the end of the description, an arrangement will also be discussed which allows a step phase correction even during the transmission of information.



  The fng. 18 shows two stations working together as transmitters and receivers which are equipped with a synchronization device working according to the method according to the invention. At both stations there is a K'1! Arinformation clear pulse converter 1 or B.

   By means of this converter is <b> the </B> Clear information converted into clear pulse sequences (transmitter) or vice versa (receiver). As mentioned earlier, the clear pulses must have the same phase position as the key pulses. For this purpose, in the example described, the clock pulses of the transmitter-side clock generator 40 are fed to the clear information clear pulse converter 1 so that it can emit the clear pulses in the correct phase position.

   The possibility of using the buffer synchronous memory was also referred to earlier.



  The output 71 of the send! Ice-side converter 1 @spenst the clear pulses in a cipher mixer 16, the output 17 of which is connected to the transmission path indicated by the arrow 100, which for example <b> one </B> can be cable, wire or radio connection.

   The transmission path ends on the receiver side in the decryption mixer located there <B> 160, </B> its output <B> 171 </B> feeds the converter 8.

   For the purpose of encryption, key pulse trains are supplied to mixers 16 and 160 by key pulse generators 10 and 110, which are mixed in the transmitter-side mixer 16 with the clear pulse trains generated by the transducer 1.

   After the transmission of the pulse sequences encrypted in this way via the transmission link 100, clear message pulses are again produced in the mixer 160 by mixing with the identical key # pulse sequence generated by the key pulse generator 110, which control the converter 8.



  Each of the key pulse generators 10 or <B> 110 </B> can be controlled via the lines 31, 21 or 131, 121 by a basic key generator 30 or 130 and at least one additional key generator 20 or 120.

   Through the combined use of these key generators, a new key start position can be produced even if a single basic key is used with every verbimd'angs- recording.

   A so-called random key can be used as an additional key. and; or a date-time key can be used.



       Each station is equipped with a clock generator 40 or 900. Each of these clock generators has a frequency generator (902), the frequencies of all these generators agreeing as precisely as possible. At least the clock of the receiving sta- tüon continues with an impulse litter

   Suppression stage 903 and a delay stage 905.



  At least at the receiving station there is a synchronization device Sy.



  Typically, each station eats, set up to both serve as. Sender as. also as. Receiver (optional) can be used. All stations are then set up in the same way, with each station naturally also having the same synchronization device and the same clock generator.



  According to the illustration, the synchronization device Sy consists of two parts Sy I and Sy 1I. The part Sy I is used to control the step infeed, i.e. H. for step synchronization.

   The part Sy 1I is used to correct the step phase or to maintain synchronization, d. H. for step phase synchronization.



  In accordance with a preferred variant of the invention, the part, Sy I, of the synchronization device consists essentially of three shift registers 200, 300 and 400 (send and receive interval memories), two correlators 500 and 600, two threshold value detectors 701 and 703,

       a threshold value generator 700 and two amplifier stages 702 and 704. In accordance with the arrangement shown in FIG. 13 and described in detail above, the part Sy II consists of two correlation multipliers 806 and 807, a differential amplifier 808, even integrator 809,

       a threshold value detector 812 and a threshold value generator 811. Two delay circuits 801 and 802 and a memory stage 803 are connected upstream of this arrangement to provide the necessary key pulse sequences in the desired phase position.



  Each of the stations is equipped with a command unit 50 or 150, which controls the sequence of the various individual phases. In order not to disturb the clarity of the block diagram, the control lines between the command unit and the individual parts of the device are not shown, but are marked as such by the designation S. The corresponding arrow indicates the direction of the signal flow - to or from the command unit.



       Details and mode of operation of the device shown in the block diagram of FIG. 18 are described in detail below. To set the initial status: a date-time key is used.



       When generating the initial state of the Schlüsszlimpulsgeneratoren 10 and 110 according to the date-time key method, at regular intervals, e.g. B. every minute, a new additional key is generated according to the date and time. In the present embodiment, therefore, the additional key generators 20 and 120 are each equipped with a clock.



  On the transmission side, the date / time key is transmitted to the key pulse generator 10 via line 21. Each time the date / time key is changed, the additional key generator 20 signals this change to the command unit 50 via the line 22.

   As long as the device is in the idle state, the command unit 50 causes the new initial state to be set in the key pulse generator 10 via the line 11; H. the mixing of the date-time key on the line 21 with the secret basic key which is transmitted from the basic key generator 30 via the line 31.



       So that practically no conclusions can be drawn about the secret basic key from the key pulse sequence that is sent out at a later point in time, the key pulse generator 10 is advanced by a certain number of steps, so-called distance steps, after the setting process. This is done by

   that the command unit 50 via the line 51 and the gate 52 releases the clock. The clock pulses come from the clock generator 40 and are sent to the key pulse generator via line 41, gate 52 and line 53 <B> 10 </B> headed. The number of distance steps can be fixed or variable. These steps are counted by the key pulse generator 10.

   The end is signaled via the control line 12 to the command unit 50, which in turn locks the gate 52 again via the line 51 and thus stops the sequence of key pulses.



  In a preferred variant with a variable number of distance steps, the number of steps is derived from the secret basic key / or date-time key, which changes periodically.



  The distance steps must not reach the transmission path 100. The command unit 50 therefore blocks the gate 14 via the line 54 during the setting process and the distance cabinet is running. Thus, no information reaches the device from which the secret basic key could be obtained relatively easily.



  If there is no transmission, d. H. the device is in the idle state, so this setting process is repeated each time the date / time key is changed. , If a message is now to be transmitted in encrypted form, the transmission side is switched from plain to syn-crypto. This is done by means of a switch 60,

   which via the line 61 of the control unit 50 issues the command to trigger the synchromesh phase.



  However, there is a condition for the run-in that the same initial status has been set for both key pulse generators.

   This condition Aest - due to the inaccuracy of the clocks on the sending and receiving side - is not necessarily met while the date-time key is changed. A run-in command must therefore be blocked or delayed for a short time during the additional key change.



  Assuming that the clocks are adjusted once a day and the accuracy is at least 10-5, the maximum difference between the clocks is calculated as: Att = 2 - 24.3600 - 10-5 = 1.73 sec. The actual blocking time however, it has to be a little larger so that a run-in triggered shortly before the start of the blocking period can still take place safely.

    and at the end of the blocking period the new correlation interval is already set on the receiving side. As a guideline, the blocking time for higher clock frequencies can be assumed to be 1 3 seconds.



  In response to the run-in command triggered by switch 60, command unit 50 initiates the step synchronization phase immediately or, if the blocking time has happened by chance, after the same has elapsed. Via the line 51, the gate 52 is opened again, so that the key pulse generator 10 is rhythmically switched on with the clock frequency of the clock generator 40.

   The key pulse generator thus emits the key pulse sequence on line 13, which contains the correction interval at a certain interval and can subsequently also be used for encryption if the requirements are less stringent. The key pulse train reaches the transmission link 100 via the gate 14, the mixer 16 and the line 17. H.

         During the step synchronization and the subsequent step phase, ensynchronization, which will be discussed in detail below, no clear information can get into the mixer 16,

   the gate 56 is blocked by the command unit 50 via the line 55 during this time. This time begins with the transmission of the final pulse sequence and ends with the expiry of a delay element which is triggered by a second pulse on the control line 12, which pulse signals the transmission of the last bit of the correlation interval.

   The delay time is selected so that the maximum possible step phase error can be corrected on the receiving side (step phase synchronization).



  The connection is now ready for encrypted transmission in synchronous mode. The clear impulse sequence flows via the line 71 and the gate 56 into the cipher mixer 16. There the clear impulse sequence is transmitted; mixed with the key pulse sequence (encrypted) and the cipher pulse sequence reaches the transmission path via line 17: 100.



       This is followed by the description of the receiving side of the block diagram of FIG. 18, again beginning with the setting of the initial state of this key pulse generator.



  As already explained in detail, in the case of step synchronization, the beginning and the running speed of the two key pulse sequences are selected in such a way that they intersect at a later point in time. As an example, the variant according to FIG. 9a was written with the slower receiver clock.

   In this variant, the receiver take is zero in the borderline case, i.e. H. After keying in the correlation interval Zo of n bits into the receive interval memory, the key generator must be stopped again, i.e. H.

   the key pulse generator on the receiving end is stopped in advance. The block diagram in FIG. 18 is designed for this special case.



       Controlled by the clock of the additional key pulse generator 120 and the command unit 150, the analog setting process of the initial state of the key pulse generator 110 and the execution of the distance steps take place on the receiving side at the same time as on the transmitting side.

   In contrast to the transmission side, this process process is not interrupted after the last distance step, but the correlation interval is then produced. This process is controlled by the fact that after the first pulse on the line 112, i. H. after the last distance step, the command unit 150 does not interrupt the process, but allows it to run west on this line until the second pulse.

   The steps between the last distance step and the last bit of the correlation interval are thus also counted by the key pulse generator 150 and can in turn be fixed or variable, e.g.

   B. derived from the secret basic key and date-time key or any device that supplies a random number. The only condition is that at least n steps (length of the correlation interval Zo) must be taken.



       During the entire process described above, the sequence of key pulses thus generated is passed via line 113 to the first stage 201 of shift register 200 (reception interval memory). Via line 252 the command is:

  unit 150 - also during the entire process - the gate 250 free, so that the clock pulses on the line 906 via the gate 250 and the line 251 to all stages of the shift register 200 and the entire key pulse sequence up to this,

  - at the point in time the shift register 200 is keyed. However, since the shift register 200 only has a storage capacity of n bits according to the prerequisite, only the last n bits, i.e. H. the correlation interval Zo, the Sch'Tüssel impulse sequence is stored.



  It should also be added that the clock pulses on line 906 have a delay of 0.5 bit compared to the clock pulses on line 904. The individual key pulses are thus always keyed into the shift register 200 in the middle between two steps of the key generator 150.

   The delay is generated by stage 905 of clock 900.



  As long as there has been no entry into the cut synchronism, the product donation and storage of the correlation interval Zo are repeated with each change of the date and time key, so that the key pulse generators for producing the correlation interval always have the same initial state on the sending and receiving side go out.



  In addition to the periodic generation of the correlation interval, the correlation factor between the last h received bits and the shift register 200 is formed in a stored manner - bits of the correlation interval produced at the receiving end. It is thus a for the received pulse train. Memory (transmission interval memory)

          necessary, for which a shift register is also used in our example. The shift pulses must have the same clock frequency. like the clock generator 40 on the transmission side, with which the transmission-side key pulse sequence is generated.

   However, since the clocks can have any phase relationship before entering step synchronism, it is possible that the shift pulses coincide with the bit end or bit beginning of the received pulses and therefore the keying into the first stage of the shift register is not clearly determined.

   For this reason, two shift registers (transmission interval memory) are used in the present exemplary embodiment, the shift pulses of which are mutually offset by half a bit period, so that at least one shift register correctly stores the pulse sequence received. These are shift registers 300 and 400,

   the shift pulses on the lines 904 and 906 by the delay stage 905 are shifted by half a Bitpieriod'e against each other. The pulses arriving from the transmission path 100 reach the stages 301 and 401 of the shift registers 300 and 400 via the line 117, where, as already stated above, the last n bits received are always stored.



  In FIG. 19, the relationships are plotted for the special case mentioned above. Line a represents any key pulse sequence received via line 117.

   Line b shows the shifting pulses arriving via line 904, which happen at random (as shown)

          coincide with the end of the bit or the start of the bit of the received key pulse sequence. Line c shows the partially incorrectly stored pulse sequence in shift register stage 301.

   The relationships for the shift register 400 are recorded in lines d and e, from which it can be seen that the received pulse sequence was correctly stored in the shift register stage 401.



  Since the received key pulse sequence has to be stored twice, two correlators are also required. These are the correlators 500 and 600 which form the correlation factor between the key sequences stored in the shift registers 200 and 300 or 200 and 400.



  Each corrector consists of n multiplication levels corresponding to the two <I> each n </I> Bits consist of the key pulse sequences and a stage for averaging (summing). In the case of the correlator 500, these are the multiplication stages 501, 502, 503 ..., which are transferred from the associated shift register stages 201 and 301,

   202 and 302 <B> ... </B> are fed. The products of the n multipliers are over the lines <B> 551, </B> 552, 553. .., fed to the middle 1 value formation of the stage 598, which emits the correction factor r1 at its output on the line 599.



  Correlator 600, whose output sends correlation factor r2 to line 699, is constructed in exactly the same way.



  As long as the received pulse sequence is any random sequence or an interval of the key pulse fcoIge before the receiving-side correlation interval ZO stored in the receiving interval memory 200, the two correlation factors are, as shown above,

   around zeroRTI ID = "0012.0222" WI = "13" HE = "4" LX = "1513" LY = "2222"> commute. But if the n bits of the correlation interval Zo were received by the key pulse sequence on the transmission side and;

  thus correctly stored in at least one of the two shift registers 300 and 400, the correlation factor of at least one of the two correla (gates r1, r2 rises abruptly to one).

   The increase in the correlation factor above a given threshold <I> SW, </I> which is determined by the maximum permissible error rate, is, as also shown above, as the intersection of the sequence of the send and:

          Key pulse waveforms on the receiving end (compare FIG. 9a) are detected and used as a signal for switching the key pulse generator 110 on again.

  * This detection takes place for one correlator each in the threshold value detectors 701 and 703, which are fed on the one hand with the predetermined threshold value from the threshold value generator 700 and on the other hand with the correlation factor of the two correlators 500 and 600.

   The threshold value detectors emit a pulse at their outputs as soon as the correlation factor exceeds the threshold value. This pulse is amplified in the subsequent stage 702 or 704 and arrives via dxs line 705 or

   706, the gate 707 as well as 708 and the signal line 711 in the command unit 150, which in turn opens the gate 152 again via the line 151 so that the key pulse generator 110 was forwarded with the clock frequency of the clock 900. From this moment on, the key pulse generators 10 and 110 on the transmitting and receiving sides are in step synchronization (step-synchronized).



  After the step synchronism has entered the gate 708 is blocked by the command unit 150 via the control line 709, so that the step synchronicity part Sy I can no longer exert any influence on the command unit 150.



  As already mentioned several times, a step phase error of a maximum of 1/2 Bf can still exist after the step in. A step phase error also occurs over time due to the imprecision of the clock. These two step phase errors - of different origin - are corrected by means of the step phase synchronization.



  In the exemplary embodiment of FIG. 18, the same device Sy 1I is used for step phase synchronization as is shown in FIG. 13. This facility has been discussed in detail above. At this point only the provision of the necessary key pulse sequences in the desired phase position and the continuation of the correction signals need to be described.



  The two correlation multipliers 806 and 807 must, of course, be fed with the key pulse sequence on the transmit side and one on the receive side.

   The key pulse trains on the receiving side have got eggs in the pulse-synchronized state. Phase shift of -1/2 bit and + 1 / "bit to the transmitting side. The constellation of these three pulse trains are generated by means of the two delay stages 801 and 802 and the storage stage 803.



  The received key pulse sequence is passed directly to the correlation multiplier 806 and the delay stage 802 via the line 113. The delay stage has a delay time of about 1/2 bit. As a result, the key pulse sequence on line 113 is keyed into memory stage 803, delayed by 1 bit by the clock pulse on line 904.

    The memory stage 803 feeds this key pulse sequence on the receiving end, delayed by 1 bit, into the correlation multiplier 807.



  So that all key pulse sequences finally have the correct phase position, the key pulse sequence on the transmission side, which is transmitted via the line, must still have the correct phase <B> 117 </B> is fed, are delayed in the delay stage 801 by half a bit. This delayed pulse sequence reaches the two correlation multipliers 806 and 807 via line 805.



  The recovery of the correction signals, which are emitted in the form of pulses via the two lines 818 and 819, is based on the above! the Mg. 13 has been described in detail. It is merely a reminder here that pulses are periodically emitted on line 818 as long as the clock generator on the receiving side has a positive step phase shift. In the event of a negative shift phase offset, analog pulses are output on line 819.



  These correction signals cause a corresponding correction of the phase position of the clock pulses on the lines 904 and 906 in the combined coaster, litter and suppressor stage 903 of this clock generator 900.



       While the message is being transmitted, the cipher pulse sequence received flows via line 117 into mixer 160, where it is mixed with the key pulse sequence from line 113 and the resulting cipher pulse sequence is fed to converter 8 via line 171.



  Machine-generated key pulse sequences are always periodic. From the point of view of encryption technology, however, a period-free key pulse sequence is preferable.

   Such a period-free key pulse sequence can be generated with a system according to FIG. 18 in that a period-free date-time key, which is generated by the clocks of the additional key generators 20 and 120, is continuously transferred to the key pulse generators 10 and 110 on the sending and receiving side can act.



  A further possibility for determining the correlation factor between two pulse sequences is an arrangement according to FIG. 20, which is then described.



       The mode of operation of this device is basically the same as that of the synchronized system Sy I in FIG. 18. However, in order to reduce the number of multipliers, this device variant works in sequence. Furthermore, the total can be done digitally.



  Shift registers again serve as memory for the n bits of the correlation interval. These are the three shift registers 220, 320 and 420.



  The correlation interval 11 generated at the receiving end is stored in shift register 220 each time the date / time key is changed, in a manner analogous to that when using the synchronizer!

   The key pulse sequence reaches the line 113, the AND gate 290, which was opened by the command unit 150 (FIG. 18) via the line 293, and the OR gate 292 to the stage 221 of the shift register 220.

   By clock pulses with the same frequency as the pulses with which the key pulse generator is switched, but a phase shift of +,! J bit, the keying Zn the shift register 220 takes place. The shift pulses arrive from the line 232 via the OR gate 231 and the line 230 to all stages of the shift register 220 at the same time.



  For exactly the same reasons as in the embodiment of FIG. 18, the received pulse train is keyed into two shift registers with a phase shift of half a bit. The pulse received via line 117 is added to this;

          on the one hand via the gates 390 and 392 to the shift register stage 321 and on the other hand via the gates 490 and 492 to the shift register stage 421. Due to the 1-bit phase-shifted clock pulses on the lines 904 and 906, the received pulse train is shifted with the same phase stored in shift registers 320 and 420.

   The above-mentioned gates 390 and 490 are opened by the command unit 150 (Fig. 18) via a control line 393 and 493 at the correct time - shortly before the clock pulse belonging to the shift register,

   so that the information on line 117 can get into disk registers 320 and 420 as described. The same control lines cause the gates 391 and 491 to separate the feedback lines 399 and 499 from the shift register inputs,

      so that the input of the received impulses cannot be disturbed from this side.



  The temporal relationships can be seen from the time schedule in FIG. Lines b and c show the clock pulses on services 904 and 906 with a phase shift of i%, bits, but any phase position to the received key pulse sequence, which is shown in line a.

   Lines d and e represent the control pulses on the control lines 393 and 493, which briefly switch line 117 to the shift register inputs during the clock pulses.



       The last n bits of the received pulse train are thus permanently stored in the two shift registers 320 and 420.



  As already mentioned, the in Fi'g. 20 the embodiment of the correlation factor: r formed in sequence. Each of the two correlators therefore has only a single multiplication stage 590 or 690 (not n as in the example according to FIG. 18).

    A counter 791 or 792 is connected downstream of each of these two multiplication stages. To form the correlation factor, all n bit pairs are successively switched to the multiplication stage and the numbers +1 and -1 are counted in the subsequent counter and the difference is formed.

   In the embodiment according to FIG. 20, this is a counter, the counting direction of which is controlled by the multiplier forwards at + 1 and backwards at -1. For each correlated bit, a pulse is given from the outside, which is then counted in the counting direction controlled by the Muluplakator.

   Because the correlation factor has to be formed twice for each .emp captured pulse of the transmit-side key pulse sequence, only a time span is available that is less than half the bit period of the received pulses.



  The sequential connection of all bit pairs (pairs of values) of the correlation interval to the single multiplier per correlator takes place in that the shift registers 220, 320 and 420 via the feedback lines 299,

   399 and 499 are interconnected to form a ring and the entire information content stored in the shift register is scanned once in a circle by n shift cycles.

    All bit pairs come once into the last stage of their shift register (stages 229, 329 and 429), where the correlation multipliers 590 and 690 are connected: and with dien. Counters 791 and 792 together form the two correlation function values.



  The n shift clocks are fed from line 782 via gates 231, 331 and: 431 and lines 230, 330 and 430 to the three shift registers. These shift clocks are shown in FIG. 21 in line f.



  From this figure it can also be seen that the control lines 393 and 493 (lines <I> d </I> and e) the shift registers during the <I> n </I> Shift clocks are interconnected in the ring.

   The shift register 220 with the correlation interval produced at the receiving end is, with the exception of the production of a new correlation interval, always interconnected in the ring and the correlation interval is constantly scanned around in a circle,

      at the end of a series of shift clocks on line 782 the same bits are again stored in the same stages.



  Before starting a count, the counters 791 and 792 are set to zero by a pulse on the control line 783. The phase position of this pulse is off. Line g of FIG. 21 can be seen.

   The following n shift clocks on the line 782 reach the two counters 791 and 792 via the delay stage 784 with a delay that corresponds to approximately half the period of the pulses on the line 782, where they are controlled according to the control of the multipliers 590 and 690 can be added or subtracted.

   At the end of the count, the counters emit the correlation factor of the intervals stored in the shift registers in digital form to the threshold value detector 794 and 795, where the comparison with the threshold value fed in by the threshold value generator 790 takes place.



  The entire process described above, i.e. H. the sampling of a new received pulse in one of the two shift registers 320 and 420 as well as the formation of the new correlation factor in sequence is repeated until the correlation factor has reached the predetermined threshold value, d. H. until the send-side correlation interval is stored in one of the two shift registers 320 and 420.

   This is the point in time when the key pulse generator at the receiving end is switched on again, which is brought about by an output signal from one of the two threshold value detectors 794 and 795. This output signal comes through gates 798, 799 and control line <B> 781 </B> in the command unit 150 (Fig. 18),

       which in turn releases the clock pulses for advancing the key pulse generator (command unit and key pulse generator are not shown in FIG. 20).



  From this point on, the key generators participating in the connection are step-synchronized.



  The relationship between threshold value, error rate, length of the correlation interval and the failure probability are exactly the same as in the embodiment according to FIG. 18 and were explained in detail above.



  Soles with a system according to FIG. 18 telex signals, which normally consist of a start pulse; consist of five information impulses and a stop impulse of one and a half times the length and normally occur arrhythmically, are encrypted and synchronized by means of correlation synchronization,

   they have to be converted into the clock pulse on the one hand and into constant pulse length on the other hand using suitable means.



  As mentioned above in the description of the correlation synchronization, the step phase synchronization is normally not possible during the transmission of information, because for this purpose the key pulse sequence on the transmitter side must be available on the receiver side.

   Obviously, this is not the case during the transmission of information. However, since the clear information is available on the receiving side after deciphering, it is possible, please include this clear information and the receiving-side key pulse sequence to generate a receiving-side cipher pulse sequence which has the phase position of the receiver clock.

   By forming the correlation function value between this receiving-side cipher pulse sequence and the transmitted, transmitting-side cipher pulse sequence, which was delayed by the time required to form the receiving-side cipher pulse sequence (so-called process constant), the receiver clock can then be phased again - even during the information transmission .

       Here, however, the possibility of so-called friend-foe recognition is lost, i.e. H. The step phase synchronization responds to any received pulse train - including hostile ones - as long as it can follow its clock frequency.

 

Claims (1)

PATENT CLAIM A method for synchronizing the encryption and decryption of messages displayed in the form of a pulse, according to which message the clear pulses are mixed with key pulses on the sending side, transmitted using a modulation and recovered at the receiving end by mixing with identical key impulses and in which these key impulse sequences are generated on the sending and receiving end according to identical rules by means of a key impulse generator and have a pseudo-random character, The key pulse sequences are determined by the initial states of the key pulse generators, which initial states are generated using at least one secret basic key and the V - r and decryption of the messages presented in the form of a pulse and the sequence of the key pulse generator laboratories send and are controlled on the receiving side by a clock generator each, characterized by d'ass for step synchronization of the transmitting and receiving-side key pulse generators (4, 9) a part of the key pulse sequence generated by the key pulse generator of this transmitter is transmitted to the receiver and there with the key pulse sequence <RTI generated by the receiving side key pulse generator ID = "0015.0130"> over an interval, from several pulses sen a comparison value sequence and with this at least a correlation factor (r) is formed, which mmmt an optimal value with step synchronism, and d'ass the mutual relative position of the two key pulse sequences continuously changed and a further correlation factor is formed for each of these positions, the sequence of correlation factors obtained thereby being used to control the step synchronization. SUBClaims 1. The method according to claim, characterized in that the comparison value sequence is formed by pulsed modulo-2 addition and the correlation factor is formed by summing this comparison value sequence. 2. Method according to patent claim, d'ad'urch characterized, d'ass the continuous change of the mutual relative position of the two keys! - pulse sequences is interrupted as soon as the correlation factor (r) reaches a predetermined threshold value according to the amount or exceeds. 3. Method according to dependent claim 2, characterized in that before entering the synchronism step, the transmitting and receiving-side clocks (5, 10) have clock frequencies that differ from one another and the correlation factor (r) is formed periodically with a frequency which is at least as large as the higher of the two clock frequencies. 4. The method according to dependent claim 3, characterized in that at the start of transmission the receiving-side key pulse generator (9) lags behind the transmitting-side key pulse generator (4) and the receiving-side clock frequency is greater than the transmitting-side clock frequency before entering the step synchronism. 5. Method according to dependent claim 2, characterized in that the lead of the receiving-side key pulse generator (9) is stopped and the transmitting-side key pulse generator (4) runs with a certain clock frequency and that the sequence of this key pulse generator on the receiving side is started with the same clock frequency as the transmitting side as soon as the correlation factor (r) reaches or exceeds the predetermined threshold value. 6th Method according to dependent claim 5, characterized in that the correlation interval for the step synchronization is stored on both the sending and receiving sides before the connection is established; . 7. The method according to dependent claim 5, characterized in that the number of steps after which the receiving-side e key pulse generator (9) is shut down by the secret basic key and or at least one additional key! is made dependent. B. The method according to sub-claim 5, characterized in that between the synchronous switching on of the receiving-side schiüsseiimpuisgene- generator (9) and the beginning of the message overmüttL Jung. Distance is switched on whose length (in .bit) is made dependent on the secret basic key and / or at least on an additional key. 9. The method according to patent claim or one of the preceding subclaims is characterized by the fact that in order to form the correlation factor (r) on the receiving side, the part of the receiving-side key pulse sequence effective as a correlation interval is stored in at least one memory, hereinafter referred to as receiving interval% peichar, is input and that also on the receiving side, the part of the received transmitting-side key pulse sequence effective as the correlation interval is stored in at least one further memory, referred to below as the transmitting interval memory, with approximately the same memory capacity. 10. Method according to dependent claim 9, characterized in that at least two transmission interval memories (300, 400) are provided on the reception series, in which the transmitted: send these soapy conclusions pulse trains with different phase shifts and that between the. Information content of the receive interval memory (200) on the one hand and the first and second and possibly further transmission interval memory on the other hand, a correlation factor (r) is formed, when the threshold value is reached or exceeded at least one of these correlation factors, the sequence of the receiving-side key pulse generator (9) is matched to the sequence of the transmitting-side key pulse generator (4). 11. The method according to dependent claim 10, characterized in that the reception interval (200) and transmission interval memory (300, 400) shift registers (201, 202, 203..., 301, 302, 303..., 401, 402, 403 <B> ... </B>) can be used. 12. The method according to dependent claim 1, characterized in that the modulo-2 addition takes place simultaneously for all pulses of the interval. 13. The method according to dependent claim 1, characterized in that the Mod'ulo-2 addition takes place for all pulses of the interval one after the other. 14th Method according to patent claim, characterized in that the key pulse generators (4, 9) on the transmitting and receiving sides are advanced a certain number of steps from the set initial state before the start of the step synchronization. 15. The method according to dependent claim 14, characterized in that the number of said steps is made dependent on the initial state of the key pulse generators. 16. The method according to dependent claim 14, characterized in that the number of steps recorded is made dependent on the secret basic key and / or at least one additional key. 17. The method according to any one of the dependent claims 7, 8 or 16, characterized in that one of the additional keys is generated by a random generator and transmitted from the transmitter to the receiver. 18th Method according to one of the dependent claims 7, 8 or 16, characterized in that one of the additional keys is identical on the sending and receiving sides. Rules of date and time is derived, with preferably no transmission being made between sender and receiver. 19th Method according to dependent claim 18, characterized in that the date and time are converted to binary and this binary character sequence is used as an additional key pulse sequence. 20th Method according to claim, characterized in that, for step phase synchronization at the receiver, a comparison value function is formed from the step-synchronized key pulse sequences over an interval of several pulses by multiplying the two key pulse sequences and this is each integrated over the interval, wherein the value of these integrals represents a correlation function value (zp) which has a maximum in the case of step phase synchronism, and that by continuously shifting the phase of the key pulse generator (9) or Clock generator (10) a sequence of correlation function values is obtained, which represents the correlation function and: this sequence is used to control the step phase synchronization. 21st Method according to dependent claim 20, characterized in that to determine the direction of the step phase weakening of the key pulse generator (9) or Clock from the key pulse generator (4) on the transmitter side or the clock transmitter (5) on the receiver side between the transmitter side and the receiver side and between mini: At least one sequence of correlation function values (7p1, 71v2) that is phase-shifted towards the transmission end and the receiving sequence of key pulses are formed, and a direction-selective signal for controlling the step phase synchronization is generated from these sequence of correlation function values. 22. The method according to dependent claim 20, characterized in that to determine the direction of the step phase deviation of the receiving-side key lamp pulse generator (9) or clock (10) from the transmitting-side key pulse generator (4) or Clock generator (5) on the receiving side between the receiving side and the transmitting side as well as between at least one phase shifted to the receiving side and the transmitting side key pulse sequence at least one sequence of correlation function values (71> 1, 71> 2) is formed and 'from these correlation function value sequences. Signal for direction-selective control of the step phase syn- chronisWon. is produced. 23. The method according to dependent claim 21, characterized in that two Sch'lüs each phase-shifted by half a step length to the transmission side: pulse sequences are used, one of which is before and the other is trailing, and that the difference values (y> 1 - 1ys) of the two correlation function value sequences are used to control the step phase synchronization (FIGS. 11, 12 ). 24. The method according to dependent claim 22, characterized in that two key pulse sequences are used which are phase-shifted by half a step length on the receiving side, one of which is leading and the other trailing, and that the difference values (71> 1-1p2) of the two correlation function value sequences are used to control the step phase synchronization (FIGS. 11, 12). 25th Method according to dependent claim 23 or 24, characterized in that the difference value sequence (y) '= 2pl - qps) is obtained in that the two correlation functions (7p1 [-'], 71> s [Z]) in a differential amplifier (808) are continuously subtracted from one another and a sum value (y ") is obtained from the difference value sequence (y '[zj) by integrating the difference value sequence in a single integrator (809) over an interval, which sum value is used to control the step phase synchronization (Fig. 13). 26. The method according to dependent claim 25, characterized in that the control of the clock phase of the receiving-side clock (10) only occurs when the amount of the sum value (v ") reaches or exceeds a predetermined threshold value (SW) (Fig. 14-17 ). 27. Method according to dependent claim 20, characterized in that the step phase synchronization is only carried out before the start of the information transmission and during the transmission pauses, whereas during the actual information transmission, the encryption and decryption and the sequence of the key pulse generators (4, 9) Sending and receiving side by a preferably before quartz-controlled clock (5, 10) ge controls. 28. The method according to dependent claim 20, characterized in that on the receiving side the clear impulse sequence to be recovered with the receiving side key: elampe pulse sequence is again encrypted and in this way a receiving-side cipher pulse sequence is generated with the phase of the receiver clock (10) and by correlating this @ receiving-side cipher pulse sequence with the transmitted transmit-side cipher pulse sequence: , which was delayed on the receiving side by a runtime-dependent constant, the step phase of the receiving-side clock is also synchronized during the information transfer. 29 Method according to patent claim, characterized in that the position of the key pulse generators (10, 110) is changed after they have been switched on synchronously as a function of the secret basic key (30, 130) and / or at least one additional key (20, 120) becomes (Fig. 18). 30. The method according to claim, characterized in that the initial states of the key pulse generators (10, 110) using a secret basic key (30, 130) and an additional key (20, 120) determined by the date and time can be set and that after synchronization of the key pulse generators, the information pulses, preferably generated by means of a noise generator, are transmitted to form a further additional key. and is used on the receiving side to generate a second initial state of the key-up generator.