DE2160132A1 - Method and device for encrypted message transmission - Google Patents

Description

GRETAG AKTIENGESELLSCHAFT, REGENSDORF (SWITZERLAND) "

Case 8 7 - 7287 / GTD 36l / R 3. ΟβΖ. 1971

"üt UTSCHLAN ¹ D

Method and device for encrypted message transmission .

The invention relates to a method for encrypted message transmission, in which one mixes the message clear impulses with key impulses on the transmitting side and off recovers the message clear impulses from the cipher thus formed on the receiving end by mixing it with identical key impulses, the key pulse sequences being sent and received in matching key pulse generators according to identical rules from a secret basic key and a term derived from the date and time generated.

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In a known method of this type, the rules for the formation of the key pulse sequences are chosen so that they are dependent on the initial state of the key pulse generators, which initial state in turn is determined by the basic and additional keys. Since a new initial state of the key pulse generator is set for each new message transmission, it is impossible - even for authorized third parties - to enter an existing connection. This is a disadvantage especially in multi-subject extension networks . ■■■■■ "

The invention avoids this disadvantage and is characterized in that the rules for the formation of the key pulse sequences are chosen so that the latter only depend for a limited period of time on the state of their terms at the beginning of this period and that the current state of the ones contained in all memory cells of the key pulse generator Information is constantly ψ influenced by the term derived from the date and time, at least during the message transmission.

In the method according to the invention, the initial state of the key pulse generators is no longer set, but rather continuously influences the current status of the memory cell information of the with the term derived from the date and time Key pulse calculator, so in a certain way, sets the initial state of the key pulse generator constantly

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the rules for the formation of the key pulse sequences are chosen so that the latter only lasts for a limited period of time The condition of your threshing floor at the beginning of this period. This means that the output information from the key pulse generator at a certain point in time only from that which lies within a certain period of time before this point in time Input information dependent and on all of the longer past Input information is independent »An authorized third party can easily integrate into an existing encrypted message transmission occur j he only has to wait for one of the times at which the at the exit of the Key pulse sequence occurring on the transmitting side of the key pulse generator is independent of the secret and additional key states prior to these times and is in which the current status of the key pulse generator was influenced by the term derived from the date and time. In practice, this is simply done in such a way that the third party switches on his recipient at any point in time, which then automatically connects to the existing connection at the next possible point in time.

The invention also relates to a device for implementation of the new method, with a preferably electronic clock and with a key pulse generator, which with a control pulse sequence formed from the secret basic key and the term derived from the date and time can be fed, characterized in that the final pulse

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generator ^{is programmable in such a way} that each key pulse at the output of the key pulse generator is unaffected by that part of the control pulse sequence which in each case by the so-called transit time before the relevant key pulse. and that the processing time switches from a larger to a smaller value at time intervals that are dependent on the secret key for a specific period of time.

A preferred embodiment is characterized in that that the clock is switched as a clock generator for the key pulse generator.

In the following the invention is illustrated in the figures with reference to Embodiments explained in more detail; show it:

1 shows a block diagram of an encryption device, FIG. 2 shows a detail of FIG. 1,

Fig. 3-6 each shows a diagram to explain the mode of operation of the synchronization of two encryption devices,

FIGS. 7, 8 each show a detailed variant of FIG. 1,

9, 10 each show a diagram to explain the mode of operation of the synchronization of two Encryption facilities,

Fig. 11,12 each a detail variant of Fig. 1, Fig. 13,14 each a diagram for explaining the in

Fig. 12 illustrated synchronization stage and

Fig. 15

-20 · each a detailed variant of Fig. 1.

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According to FIGS. 1 and 2, there is a clear text / clear pulse converter 9 at each cipher station, which converter converts the plain text message into clear message impulses (sender) or vice versa (receiver). This converter can

be a teletype, for example. The output of the sending side Converter feeds the message clear impulses

a line 147 into a mixer 8, the output of which with the Transmission line 148 is connected, which for example can be a cable, wire or radio connection. When using the cipher station shown as a recipient

the transmission path 148 'opens into the mixer 8,

the output of which feeds the converter 9 via a line 102. For the purpose of encryption, the mixing device 8

Key pulse sequences supplied by an encryption device, which in the transmitter-side mixer with the clear text-clear pulse converter 9 generated message clear pulse sequences are mixed. After receiving the encrypted pulse trains on line 148 *, the message clear pulse trains are again mixed with identical key pulse trains produced and converted into plain text by the receiving side plain text / clear pulse converter.

The encryption device essentially consists of a key pulse generator 5 and a synchronization stage

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The key pulse generator 5 has the task of producing as long a key pulse sequence as possible, which so should be constructed so that the variation between successive elements or element groups is as random as possible is. The key pulse generator consists essentially of a number of memory locations, which by a secret Basic key influenceable electronic circuits L can be connected to one another. The basic secret key is usually constant over a long period of time. The current status of the key pulse generator, where current status means the status of the information of all memory cells is through a variable additional program, the so-called Additional key determined.

The key pulse generator 5 has two inputs and two outputs: one input is connected via a line 140 to ψ the output of a modulo-2-mixer 18, the other input is connected via a line 7 with a date-time storage. 1 The two outputs of the key pulse generator 5

are connected via a line 81 to the mixer 8 ¹ , or via a

Line 82 can be connected to synchronization stage 6. The modulo 2 mixer 18 for its part has two inputs, one of which is connected to a number memory 2 via a line 154

via a line and with the date-time memory 1 and another · with a

Secret key storage 3 is connected. The date-time

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Memory 1 is used on the one hand for the additional key memory output of the additional key via the line 154 and on the other hand as a clock for the key pulse generator 5 and for the secret key memory 3 - line 7. The date-time memory 1 is essentially an electronic watch,

which their respective information, according to the day (T), Month, year, hour, minute and second (see) at certain intervals, e.g. every second, to the modulo 2 mixer 18 gives up. It is obvious that this output signal of the date / time memory 1 is due to its complete freedom from periods excellent as an additional key for mixing with the program of the secret key memory 3. Of the

Number memory 2 is used to store a subscriber or Address number, shown as a three-digit number H (hundreds), Z (tens), E (ones) and has the purpose of

Use of the same secret key on the same date

and the same time in different transmission networks To make the key stimulus program different for the different participants. While the additional key is constantly

changes, the subscriber number in the number memory 2 is usually constant for a specific message transmission. The subscriber number can be entered manually in the number memory 2 via a line (not shown). Entering the Date-time information in the date-time memory 1 is usually done automatically. To increase the variability of the

Additional information - additional date / time key and partial

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subscriber number - can a separate memory (not shown) be provided for non-secret additional information, which is switched so that the delivery of its output signal in

Dependent on the date-time additional key and / or on

the participant number. In addition, the secret key store 3 with the date-time memory 1 and / or with

the number memory 2 be connected so that depending on the content of the date, time and / or the number memory t select certain parts of the contents of the secret key memory

are nable. The secret key memory 3 can for example be an electronically retrievable "Random Access Memory" (RAM), which can continuously transmit the stored information in sequence to the modulo-2 mixer. The output signal of the mo-

dulo-2 mixer 18 and thus the input information of the key pulse generator 5 is therefore dependent on the secret key,

the additional date-time key, the subscriber number and possibly additional information. Because of these

Information only the secret key is secret, and since the

current status of the key pulse calculator in brief Time intervals through the additional date-time key

is newly determined in each case, an authorized participant who one with the key pulse generator of the respective Transmitter has an identical key pulse generator and which knows the non-secret additional information into a existing encrypted messaging occur, if

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far only its key pulse generator has the property that the key pulse sequences occurring at its output only for a limited period of time from the pulse trains fed into the input at the beginning of this period depend. A key pulse generator of this type is described, for example, in Swiss patent application no. 12592/70 (Case 87-G 342). The period of time during which a certain input information becomes the output information of the key pulse generator determined, for example, in the order of 10 seconds or seconds Minutes. A third participant can enter an existing connection with the delay time of this time span. In the case of the key pulse generator described in the cited patent application, the period of time during which an input pulse the output pulses are influenced in by the secret key dependent points in time can be switched from a larger to a smaller value for a specific period of time. Third parties can enter an existing connection during these periods of time. On the other hand is at This key pulse generator also requires the longest possible time to influence the output sequences by the input sequences and thus for high encryption strength Fulfills.

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As already mentioned, the date-time memory 1 is an electronic clock. The clock source of this clock is a quartz oscillator 13, which is followed by a fast reducer part 12 and a slow reducer part 11. The quartz oscillator 13 outputs a clock frequency of, for example, 1 MHz, corresponding to a clock period T ₀ of 1 μs, to the input of the high-speed reducer part 12. In the fast scaling part, which essentially consists of frequency scaling circuits 14 and 15 connected in series, the clock frequency is first scaled down to the clock frequency with the clock period T. This frequency is fed via the line 7 to the individual stages of the date / time memory 1, the key pulse generator 5 and the secret key memory 3 and serves as the clock frequency for the entire encryption device. In the step-down circuit 14, which according to the illustration has 18 binary steps, the clock frequency is stepped down to approximately 4 Hertz with the period T corresponding to the number of step-down steps. This frequency is fed to the slow reducer part 11 via a line 149 and is initially stepped down to 1 Hz in a two-stage reducer 22. _{The clock signal T ßG} available at the output of the reducer 22 accordingly has a period of 1 second. This 1-second clock signal T is used to drive the actual clock, the logic of which is adapted to the customary date-time information -second (see), minute, hour, day (T), month, year. The . Numbers for the date and time are binary coded, with 4 binary digits being provided for each number. When specifying the seconds, the quarter seconds are specified in addition to the whole seconds, for which two additional binary digits are sufficient. A coaster (not shown)

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logic in the technology used for electronic clocks ensures that the transmissions take place from seconds to minutes, etc. This electronic watch is through a store 26, which memory is also the number memory 2 forms and next to the storage locations for the date and time information 12 more memory locations for storing the binary coded number information H (hundreds), Z (tens) and E (ones). Just like the two memories 1 and 2, the entire encryption device works with it binary coded signals. For the sake of saving lines, all of the information in memories 1 and 2 is assigned to the Modulo-2 mixer 18 is not entered in parallel, but in sequence. For this purpose, there is a kind of parallel-series conversion of the Information available on the coasters 26 and 22 is required. This conversion takes place by means of a shift line Drivable date-time shift register 19, which just as many Has stages like the two reduction parts 26 and The information of a binary level of the reduction parts 26 and 22 is each step of the date-time shift register 19 guided. The transfer of the information of the individual binary levels of the scaler parts 26 and 22 into the binary levels of the date-time shift register 19 takes place once after a transfer from the fast coaster part 12 into the slow coaster part 11, according to the illustration every 1/4 seconds by means of a not shown, to the output of the fast Coaster part 12 (clock period T) connected setting line. During the period of 1/4 see the information is in the Reducer parts 26 and 22 constant and the information in the

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The date / time shift register 19 is continuously shifted around in a circle by the shift line 20 connected to the clock period T via a return line 25 and at the same time fed to a modulo-2 mixer 21. Since the ratio of the two clock periods T: T is approximately equal to 1: 250 ¹ OOO, and the length of the date-time shift register 19 is approximately 60 steps (10 steps

Details for the seconds, 8 steps each for the minute, hour, Day, month, year plus 12 levels for the number information plus 2 levels for the transfer from the coaster part 22) is, the information of the date-time shift register is used during 1/4 see 19 250,000: 60, i.e. roughly 4,000 times unchanged, out to the modulo-2 mixer 21.

In a preferred embodiment, the binary levels the divider parts 26 and 22 and the stages of the date-time shift register 19 including the necessary counter carry circuits designed as an integrated circuit, whereby the relative There is no need for expensive cross-connections between coasters and shift registers.

W With the shift line 20, in addition to the date / time shift register 19, a feedback shift register 16 is also driven. As shown, this shift register has twenty stages and has a tap 152 at the third stage, which is fed to a modulo-2 mixer 17, the latter feeding the mixed product of the information from this tap 152 and the output 151 of the feedback shift register to its input 153 . Such a shift register with η shift register stages provides a so-called

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"Pseudo-Noise" sequence (PN sequence) with the period duration of approximately 1 million clock pulses. The PN sequence has the characteristic property that, with the exception of the Total periodicity is practically equivalent to a statistical pulse train. The PN sequence of the feedback shift register 16 also reaches the modulo-2 mixer 21 via its output 151 and is processed with the program of the shift register 19 mixed. The output signal of the modulo-2 mixer 21 results in the additional key, which is fed to the modulo-2 mixer 18 via the line 154. In the example shown the period of the PN sequence of the feedback shift register 16 is about 1 second, whereas the memory content of the date-time shift register 19 changes every 1/4 second, which means that during the period of the PN sequence the slow reducer part 11 has been connected upstream three times and with certainty at the beginning of the new expiry period of the PN sequence is changed.

Since from the clock T both the binary scaler 14 and the feedback Shift register 16 are driven "in parallel" and since an η-stage shift register has a cycle period of 2 -1

η clocks and an η-level binary scaler 2 clocks per period

has, the clock of the feedback shift register 16 must be once per cycle period in order to maintain synchronism be suppressed.

The binary scaler 14 can, in addition to its function as a fast scaler part, also be used to obtain clock cycles of different periods.

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pulses can be used. As will be explained below, these time pulses are used for the synchronization between the transmitting and receiving stations. If two taps for obtaining such clock pulses are spaced apart by the number Z binary levels, then the corresponding clock periods differ by a factor of 2 * According to the illustration, the period of the clock pulses T _{G is} four times as large as that of the clock pulses T, the period of the clock pulses T four times as large as that of the clock pulses T, the period of the clock pulses T eight times as great as that of the clock pulses T "and the period of the clock pulses T eight times as great as that of the clock pulses T. These different clock pulses form a grid which is ideal for synchronization.

For all applications in which this grid is not used can be, the binary scaler 14 can be dispensed with and the feedback shift register 16 can be used directly be connected as a step-down circuit between the quartz oscillator 13 and the input 149 of the slow step-down part 11, wherein the fed-back shift register sends a ballast pulse to the slow reduction part for each of its cycle sequences 11 supplies.

Since, as already stated above, message pulses, which .bei the transmitting station with a certain key pulse sequence

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have been encrypted can only be correctly received if the corresponding cipher is deciphered at the receiving end with the same key pulse sequence, there is an exact synchronization required between sender and receiver. Since the key pulse trains depend on the date and time, This synchronization consists in principle in the sending and receiving side clocks taking into account the transmission time to equate. The synchronization stage 6 consists of a time comparison device 61, an OR gate 63 and a memory 62. In addition, the date-time memory a time correction device 4 is connected upstream, the input of which is connected to the output of the OR gate 63. In the time comparator facility 61, which via a switch 23 to the key pulse generator 5 or connected to the date / time memory 1 is, the time difference between the received signal fed into the time comparator device via a line 132 and the key pulse generator 5 - line 82 - or its own clock line 128 - detected. The former is therefore possible because the key pulse program depends on the time. The time comparison can be based on nested in the received signal Time pulses take place or by correlation of the received signal with the key pulse program, etc. The determined The time difference can be used, for example, to

own clock from the time comparator device 61 via the line 22 and the OR gate 63, the line 129 and the time correction device 4 to be adjusted. The determined time difference can also be transferred to the time difference memory 62 via the line 131 entered and stored in this, so that after a message with this memory value, the previous Clock adjustment again via the OR gate 63, '

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the line 129 and the time correction device 4 can be canceled and the clock after the communication has ended is returned to its original gait position.

Fig. 3 shows a basic example for the synchronization between the sending and receiving station with the help of a grid of nested in the actual message impulses Synchronization pulses of different period durations or frequencies. In the following remarks, Valence of the impulses spoken, in this context, the value is proportional to the period and is in the Fig "marked by the line height of the individual pulses". As line a, which shows a time pulse grid received by the receiver represents, it can be seen, possess the actual

ten pulse N
Message J with the period T has the lowest valency, the next higher valency are the so-called word pulses W ₁ with the period T, with one word pulse for every four information pulses. The next higher valence * have the so-called block pulses BL with the period duration T and the so-called block group pulses BG ₁ with the period _{duration T G} finally have the highest valency. There is a block pulse for every four word pulses and a block group pulse for every four block pulses. In line b, the time pulse pattern generated by the receiver is shown. The time difference between the received signal and the self-generated signal is At. The following are used for clock synchronization at the receiving end

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Steps to be taken: First, the time pulses of the lowest value, i.e. the message pulses N, _ZU r are brought into congruence. For this purpose, the self-generated time signal is _{shifted by fractions of the period T n} , namely by the difference Δτ. This brings the clock on the receiving side to the position of line c. The word pulse division is then corrected from line c to line d, the self-generated signal being shifted by 3 information lengths. This means that Δ T = O. Next, the difference Δ Τ of the block

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impulses corrected by shifting by 3 word impulse lengths. This takes you to line e and the difference is corrected

Δ T cter block group pulses by shifting 3 block pulse lengths T. Line f, as its own corrected clock position, is thus synchronized in time with line a as the received signal. The readjustment of the clock on the receiving end can be carried out, for example, in such a way that the binary coaster 14 (FIG. 2) additional impulses can be entered at the corresponding levels. Of course it is possible to determine the valence of each To characterize time pulses of the synchronization pulse pattern by different durations instead of different amplitudes.

Another example of synchronization between broadcast and receiving station with the help of a synchronization pulse grid is shown in FIG. Line a shows the clock pulse raster of the crystal oscillator 13 (Fig. 2) with the period T, line b shows the clock pulse grid of the key pulse generator with the period T. Line c shows the so-called information

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, tion bit clock pulse grid with the period length T and line d the information clock pulse grid with the period Τ _Ώ . This period T should correspond to the bit length of the actual message pulses. Line e shows a short sequence of message pulses 101. The time scale is shortened in line f in order to be able to display a larger number of pulses. The signal in this line is structured as follows: Between every 2 word pulses W (recorded in line g) there are 6 message pulses each, for example message pulses 101110 for the first word on the left, 001011 for the second word, 100010 for the third word, 010111 for the fourth word etc. Before each word pulse W, a bit length is free for the information for the block pulses. This block pulse information is led down from line f to line h by means of arrow lines. Before the first word on the left, this information is selected equal to 1, before the second word also equal to 1, before the third word 0, before the fourth word 0. Then the sequence of block pulses (line h) repeats itself periodically 11001100 etc. With this periodic Information can be used to determine the block boundaries - line i - by changing the block pulses 00 to the block pulses 11. Line j finally shows the block group pulses BGj. The readjustment of the clock on the receiver side in the event of time deviations is carried out according to the method described above (FIG. 3). With regard to the period duration of the individual synchronization pulses, it should be noted that, quite generally, the period duration of the synchronization pulses of the highest valency in the examples of FIGS. 3 and 4 must be greater than twice the maximum expected clock deviation between

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see sender and receiver. In this case, failure to transfer

synchronization of the sending and receiving clocks every periodic Time pulse of the clock on the receiver side between two periodic pulses of the clock on the transmitter side, namely in in each case so that the distance of the receiving-side time pulse to the one adjacent transmitting-side smaller and to the other is greater than the time pulse period. Since this period is greater than twice as stated above maximum expected clock deviation is a receiving-side Time pulse always to coincide with that of the two adjacent transmit-side time pulses from which it is less far away. With the accuracy of quartz-controlled watches that can be achieved today - maximum deviation per day 0.1 seconds - one can assume that the clock deviations are not greater than + 5 seconds will be.

The synchronization methods discussed so far have the disadvantage that to correct the. Clock differences at least that Time of clock deviation is required. The following describes methods with which time differences in a significant shorter than the time difference corresponding time can be corrected.

A first such method is shown in FIG. 5: According to line a, the actual message pulses N are nested between the periodic word pulses W. A block pulse bit is nested in front of each word pulse W ₁ - similar to line f of FIG. 4. In contrast to, for example, FIG. 4, however, the block pulses are not only shaped and arranged in such a way that the block and block group boundaries can be detected with their help, but also contain information at the same time. In line b, the block pulses identified by their respective binary characters 0 or 1 are shown. 16 block pulses each form a block, the block boundaries are marked by the sequence of four 0 and four 1 and shown in line c by dashed pulses BL. As can be seen in line b, the information within a block consists of a sequence of six transmitted three times in each block

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Binary characters. Each of these sequences corresponds to a decimal number with two / one places after the comma: The sequence 011001, which appears three times in the left half of line b, corresponds to the number] () ^/ 4 _f, the sequence 011010 shown in the right half corresponds to the number 6 2, These numbers mean the lüinerstelle plus the quarter of the second display of the clock (date-clock time memory 1, Fig. 2). Since, as explained in the description of FIG. 2, the additional date / time key is fed to the key impuls generator 5 every quarter of a second via the modulo-2 mixers 21 and 18, a new time value is also created every quarter of a second the sequence of block pulses shown in line b is transmitted three times each. The three-time transmission serves to protect against interference. The block time T - line a - is also selected to be 4 seconds. The reason for this is that a delay time of 4 seconds is normally just allowed and not annoying - for example during a telephone call. A delay time of 1 second would, on the other hand, be safe for a telephone call, 50 ms would be unnecessarily short. 4 seconds is a "manipulation time" that is just allowed. On the receiving side, only the block boundaries have to be determined and then the received seconds values are compared with the seconds values of your own clock and your own clock is corrected. The correction can be made directly in every position of the clock coaster with practically no time delay. The correction of a time deviation of 5 seconds, for example, can easily take place ^{within V 4 seconds.}

- In Fig. 6 a variant of FIG. 5 is shown in which

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the block boundaries are not marked by a specific sequence of block pulses as in FIG. 5, but rather by the transmitted time information itself. According to FIG. 6, within a block T_. _T the time and seconds are transmitted three times redundantly as block pulses BL. As in FIGS. 4 and 5, the block pulses are in each case nested in front of the periodic word pulses (not shown). The block length T is

1/4 second again, so with the two-digit binary number after the decimal point. To mark the block boundaries, the third of the redundant clock times is reversed Sequence as well as in inverted form. This means that, for example, the first digit of the time is 7 1/4, i.e. the character 0 is inverted to 1 and placed in the last position, etc.

7 shows a first exemplary embodiment of the time comparator device 61 of the synchronization stage 6 (Fig. 1). The device shown in the figure is suitable for determining on the block boundaries marked in the manner described in FIG. 6 and essentially consists of three shift registers 30, 31 and 32, from three comparators 27, 28 and 29, from an inverter 39 and from an inverted AND gate 38. The time pulses of the Line 132 received signals arrive with a shift clock T switch corresponding to the word pulse clock T (FIG. 3) 35 and 36 and 37 in the position shown and switch 34 open - into the three shift registers 30, 31 and 32. Each Shift register has to accommodate a six-digit binary number. Ihl 6 levels. After each clock pulse from T are briefly

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the switches 15, 36 and 37 thrown, the switch 33 is

2 0 9 8 2 G / (ι b 5 6

closed xsxid the switch 34 is open for exactly 6 clock pulses of a fast _{shift clock T c} , v / elcher 'is at least six times as fast as the shift clock T * The information in each shift register is then completely shifted around the circle with the shift clock T and is then back at the original location. This happens before the next clock pulse T arrives at the corresponding input terminal. During the revolution around the circle, the content of the shift register 30 is compared with that of the shift register 31 in the comparator 27, the content of the shift register and the content of the shift register 32 inverted by means of the inverter 39 in the comparator 29, as well as the content of the shift register 31 and the inverted content of the shift register 32 in the comparator 28. It should be noted that for the shift clock T the shift direction in the shift register 32 is reversed. This reversal of the shift register corresponds to the reverse order of the third number (FIG. 6), whereas the inverter 39 corresponds to the inverters for the inversion of the time information (not shown). If an inequality is found during a full cycle when comparing one of the 3 comparators, the binary character 0 is present at the output of this comparator and the binary character 1 is present at the inverted output 40 of the AND gate 38. This 1 causes the entire procedure to start with the next clock pulse T_ is repeated until all outputs of the comparators remain at 1 when the information in the shift registers circulates, so that a 0 appears at 40. This 0 is the character for the block boundary. The determination of the block boundary

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if this is necessary, the individual bits of the number do in format ion to be able to classify them in their correct positions. The for Determination of the block limit required number of shift clock pulses T, which is the time difference between send and block boundaries on the receiving side, expressed in terms of the number of words (clock period T), can, for example, be in one Counter 700 can be determined. Dasu is a switch 134, which is closed with the first shift clock T and when the occurs Binary character 0 on line 40 is opened. The clock at the receiving end is corrected using the number found of shift clock pulses according to the method described in FIG. 3.

8 shows a second exemplary embodiment of the time comparator device 61 (Fig. 1), in which the determination of the time difference between transmitter and receiver by so-called pulse templates he follows. According to FIG. 8, a feedback via a modulo-2 mixer 41 is used to generate these pulse templates four stage shift register 400 used. This shift register is used to create a 15-bit PN pulse template generated. The individual bits of this impulse template are as in the examples of FIGS. 4 to 6 each in front of one

Word pulse placed. The respective pulse template is transmitted redundantly three times within a block. An impulse template of 15 bits is known to have the property that, when correlated with the same pulse template in different phase positions, in 14 phase positions the correlation value - 1 and in the fifteenth the correlation value +15 results. So she is for Determination of the phase position on the transmit and receive side is good suitable. The length of the pulse template therefore corresponds to also the block length T. Which occur in time with the word impulses-

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BATH

The individual bits of the pulse templates pass from the receiving line 132 into a shift register 42 and are inserted into this with the shift clock T corresponding to the word pulse period T ". During the insertion, the feedback of the shift register 42 via the switch 43 is open. Between every two clock pulses T_, with the switch 43 closed, it is pushed around once in a circle _{at a high clock frequency T g.} The shift register 400 is driven at the same clock frequency T ". As a result, the pulses of the pulse templates and, on the other hand, the information of the shift register 42 shifted around in a circle come clock-synchronously to a correlator 44. This shift register has 15 stages and can thus store a full pulse template. Of course, the pulse templates at the transmitting station are produced with an identical pulse template generator (shift register + modulo-2 mixer). If the phase position P of the information stored in shift register 42 does not match that generated by the pulse template generator, the correlator determines the correlation value -1. If this is the case, switch 43 is opened again and a new shift clock pulse T shifts the information in shift register 42 by one Level further. Then the switch 43 is closed again and the information with the high clock frequency T _{0 is} pushed around once in a circle and the correlator 44 again determines the correlation value. _{The number of clock pulses T T} required up to the point in time at which the correlator 44 determines the maximum correlation value becomes the same

- - ■ »

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r. 25 τ ₄

Manner as determined in the example of FIG. With the occurrence of the maximum correlation value / the synchronization process completed. With this method, nu * "time differences correct which are smaller than the block length. Of course, there is no need for the maximum correlation value to have its maximum value, but it only has to have a certain threshold value (at a correlation value of 15 for example exceed the threshold value 10) in order to cause the end of the synchronization procedure.

In Fig. 9 is a similar method for determining the time difference between sending and receiving station is shown schematically

The method used in the device of FIG. 8 is like that in Imit which, however, can also correct time differences which are greater than the block length. 9 shows a sequence of block pulse bits which are nested in the transmitted message in the manner already described several times before each word pulse. In contrast to FIG. 8, however, the individual blocks with the block period T__ not only consist of an impulse template IS, but also an additional indication of seconds, as shown in the illustration 6 1/4, 6 1/2, 6 3/4 etc. The block length T_ here is, for example, 1/4 second. The device required to determine the time difference between transmitter and receiver is identical to that shown in FIG. The block boundaries are determined in the manner described under FIG. The methods of correcting the time are described below.

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In Fig. 10 there is also a similar method for determining the clock time difference between sending and receiving station

The method used in the device of FIG. 8 is shown schematically as that of I with which, however, similar to the method described in FIG _{, three different pulse templates IS 1, IS 2} and IS ₁ are sent out one after the other in a repeating cycle. The three pulse templates IS 1, IS 2 and IS 3 together form a block group Tp

that shown in FIG

based on the time difference! this pulse shown schablo'nengruppen containing the device shown in Figure 8 substantially for each pulse template, so depending on a feedback via a modulo-2 mixer 41 shift register as a pulse template generator and each one with a slow or fast shift clock T _T or T _c drivable sliding

J-I O

register 46, 47 and 48 and one correlator 44 each. Each of the shift registers 46, 47 and 48 has a number of stages corresponding to the number of bits of a P pulse template and each serves to receive one of the three pulse templates. The mode of operation is similar to that of the "device" shown in FIG. 8, ie the memory contents of the shift registers 46, 47 and 48 are compared in the associated correlator with the associated pulse template. When the first maximum correlation value occurs in one of the three correlators, the clock time difference is determined The duration for this time difference determination is therefore at most the length of one of the three pulse templates.

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Pig. 12, another embodiment shows a ¹ means for synchronization between the transmitting and receiving station. This type of synchronization can be referred to as correlation synchronization and is described in principle in Swiss patent specification No. 422 047. A pseudo-statistical pulse signal contained in the transmitted message signal is used for synchronization, the sequence of which is fully determined by the date and time. The pseudo-random impulse signal can be:

- the key impulse program itself.

In this case, the correlation synchronization at the receiving end takes place in transmission pauses, i.e. when the key pulse program is not "covered" with plain text, or by means of a plain text detector.

a pseudo-statistical and secret key-dependent pulse signal additionally generated by the key pulse generator. This pulse signal can either be transmitted in a separate communication channel or, as described above, in In the form of time pulses nested in the message signal are transmitted.

- a non-secret, but date and time dependent, pseudo-statistical pulse signal.

The first two methods mentioned have the advantage that the pseudo-statistical pulse signal is also dependent on the secret key and it is very difficult for unauthorized persons to enter synchronism.

209826/0656

The device shown in FIG. 12 differs essentially from the devices described above through a shift register 77 for storing the pseudostatist! received over the line 132 "see pulse signal and by a shift register 80 for storing the pseudo-random generated by its own key pulse generator 5 Pulse signal. Both shift registers are connected to a correlator 76, which correlator is used to compare the memory contents the two shift registers is used.

To explain how this facility works, it is assumed that that the pseudo-random pulse signal either by the key pulse program or by an additional generated program of the key pulse generator 5 is formed, It is also assumed that the pseudo random pulse program when it arrives on line 132, the actual message pulses have already been released. For the better To understand how it works, a numerical example will now be given: The pseudo-random received on line 132 Pulse signal, which has a pulse period of 10 ms, for example, is fed into shift register 77. The pseudo-random pulse signal generated by its own key pulse generator 5 is fed into the shift register 80. Since the sending and receiving side clocks initially differ by the time difference (e.g. a few seconds) this time difference must be determined by a search process as quickly as possible. The received signal

2Q9826 / 0668

arrives at a constant speed and, in addition, cannot accelerate due to the given transmission channel capacity on the other hand, the generation of the pseudo-random pulse signal of the receiving device can be accelerated. will. The principle process for the initial synchronization (or equalization of the sending and receiving-side clock) when establishing a connection, where the relative clock settings can still deviate from each other, for example a few seconds, is that the clock on the receiving end is reset by at least the entire expected time difference the clock on the receiving side is definitely in a position that lags behind the clock on the transmitting side. From here you will now be the receiving side Clock and the receiving-side key pulse calculator let run at increased speed, whereby after a certain time that the clock position on the receiving side is reached which corresponds to the transmitting side. The process of this Scanning is as follows: It is assumed that all stages of the On the receiving side shift register 77 are occupied. For example, if this has 64 levels, the fill time is at the selected period of the impulses thus 0.64 seconds. This time is compared to the desirable manipulation time of about 1/4 second too long. However, this can easily be done by reducing the number of stages in the shift register 77 to, for example 32 steps or by increasing the clock frequency of the pseudo-random pulse signal. After the first time Recipients entering the connection check their own clock

209826/0656

-30-7

has reset the expected time difference, a between the quartz oscillator 13 and the coaster 12 is arranged Switch 71 moved into the position shown, whereby the clock pulses of the crystal oscillator on a stage 165 of the Binary scaler 14 are coupled, which is 8 scale stages from the original connection of the crystal oscillator

is offset. As a result, the clock 2 runs = 256 times faster and so does the key pulse computer 5 (line 7). That about the Line 82 delivered program of the key pulse calculator, * which in normal operation also has pulses of 10 ms period supplies, also runs 256 times faster, which shortens the pulse period to about 40 ils. The shift clock for the two shift registers 77 and 80, which is taken from the stage 163 of the binary scaler 14, the switch 72 is in the position shown, also has a clock period of 40 us: the oscillator 13 supplies one Clock frequency of 1.64 MHz. When the switch 71 is in the position shown, this leads directly to the eighth reduction stage of the binary coaster 14 and passes up to stage 163 on the binary coaster another 6 coaster stages, so it is still 2 = 64 times reduced, which is a clock frequency of 1.64 MHz: 64 = * 25,000 Hz and thus a clock period of corresponds to approx. 40 f | s. These 40 microsecond shift pulses arrive when the switch 134 is in the position shown, only on the shift register 80 and not on the shift register 77. The contents of the shift registers 77 and correlated with each other. This is done by using a

209826/0666

fast cycle of about 0.6 / is cycle period the entire Shift register contents are shifted around once in a circle via the now closed feedback contacts 78 and 79. the Shift registers have 64 shift register stages, that means 64 clock steps are required for a full "in-circle shifting" and these should be carried out within 40 ais, from which the 0.6 pjus clock period results. This clock period corresponds to the oscillator frequency of 1.64 MHz. The "pushing around in a circle" happens in that the switch 72 switches to the line 164 and the switch 134 to the line 162, switches 78 and 79 are closed and switch 54 is opened. The correlation therefore takes place in sequence with a single correlator 76. Der.Korrelator 76 acts so that it during the 64 correlation steps, the individual corresponding Comparing bits of the contents of the shift registers 77 and 80 with each other, if they agree with + 1 and if Mismatch is evaluated with - 1 and these 64 values are arithmetically enumerated. If the times do not match, the Correlation value can be small and, on average, fluctuate around zero. If there is an exact phase match of the information in the shift registers 77 and 80, the correlation value is 64 in the ideal case (no disturbances). In practice, temporal Correspondence already found when overwriting a threshold value below 64, for example between 50 and 60. The size of this threshold value is chosen so that, on the one hand, accidental false runs are as rare as possible and that, on the other hand, the facility also works in the event of transmission disruptions. Will the chosen threshold at a first Correlation value determination not reached, then under Reset the switches 72,134,78 and 79 a new 40- ^ us pulse of the vom Key pulse generator 5 output pseudo-statistical

209826 / 0SE6

Pulse program shifted into shift register 80. Then, with this new value, as described above, by once ⁿ in circles around Slide ¹¹ is a further correlation value is determined, etc. The procedure is continued until one of the threshold correlation value is exceeded, and then by a thereby triggered pulse, the switch 71 in its normal position - Connection between oscillator 13 and 1st stage of the binary scaler 14 - set back and the clock is driven at normal speed 40 tis of the synchronization phase increased 256 times to approx. 10 ms of the normal run. From now on, the switch 134 remains in the position connecting the line 162 to the switch 72, whereby the 10 ms pulses are also fed to the shift register 77 and the received pulses are inserted at normal frequency. During the synchronization phase, the time difference memory 62 counts the number of 40 f sharp clock pulses which occurred from the beginning of the clock reset until the correlation value was reached. This number of clock pulses corresponds to the clock deviation on the transmitter and receiver side in pulse lengths of the pseudo-random pulse signal. This storage value in the time difference memory 62 can be used to reset the clock to the original running value after the transmission or connection has been canceled. Should it be found to be necessary, the synchronization can be continuously checked by the correlator 76 in normal operation with a normal cycle after the run-in has been completed, since the inputs of the correlator are constantly on the one hand on the received signal and on the other hand on the

209826/0656

Output of the key pulse generator. The time to search For example, a clock difference of 5 seconds is extremely small. 5 seconds contain 500 of the 10 ms long pulses of the pseudo random pulse sequence. These 500 impulses need 500 in the high speed of the synchronization phase. 40 iis, which corresponds to 20 ms. So in 20 ms it will be full range of clock deviation of 5 seconds searched. If this clock deviation were one minute, the search would be possible in about 1/4 seconds? this shows that even with a one-minute clock deviation, the clock equation can take place within 1/4 second and even, according to the very favorable correlation method, with a very large Safety.

The synchronization process described is shown in FIG. 13: The time t is plotted on the X-axis, and the time t * of one's own clock is plotted on the Y-axis. At time t ,. your own clock is set back to the clock position T, * by the maximum clock deviation, for example by 5 seconds. Then it runs through twice the possible clock deviation 2Δτ up to the point T _n *. In Fig. 11, it is assumed that max δ

men that in this run for some reason, e.g. because of strong interference, the synchronism did not come about. At time t ₂ ^{, the clock is set back by 2} AT to T *, after which the correlation search process is carried out again at high speed. At point T ₄ * (time t-) the correlator responds and switches its own clock to normal speed. The time difference Δ T determined and recorded in memory -62 is also shown. In the point

20982670656

-T ₅ * (time t.) The connection is canceled and the storage value ΔT of the time difference memory 62 is used to reset the own clock to the original normal run - point T *. In principle, large differences in time of day only need to be compensated for when the connection is established for the first time. As soon as your own clock has been calibrated, this clock setting can be stored in special memories, as described below, so that when a new connection is established, a search range of, for example, only 0.1 or 0.5 seconds can be easily managed , because, for example, a quartz of

—Fi
10 see. Accuracy only shows a rate deviation of 0.5 seconds in 5 days. With a search width of only 0.5 seconds in the synchronization phase, the time for entering synchronism is also extremely short and is around 10 to 20 ms.

As from the example with 10 ms bit length of the pseudostatisti- " seeing pulse signal can be seen clock deviations of + 30 seconds within about 1/4 second with ease be brought to exact synchronism. Such a deviation corresponds approximately to the deviation which a quartz-controlled electronic clock with an accuracy of 10 "see within a whole year. So you can run such a clock for a year without having to readjust it. It is therefore advantageous to run the watch part on a battery, even while the encryption device is in storage.

209826/0666

The key pulse calculators used for the encryption facility are, as mentioned above, those whose storage time is limited. This property of limited storage time the key pulse calculator is for the inventive Encryption device is of particular importance, since only then does the type of synchronization described with reference to FIGS. 12 and 13 become possible is made possible. Because when you reset the clock, the key pulse calculator should also be reset so that it can of the reset position also the "correct", the reset Clock emits the corresponding key pulse program. A reset of the key pulse calculator is not, however possible. It is therefore necessary that the key pulse calculator be activated in a sufficiently short time after the clock has been reset issued the information previously saved.

In order not to have to rely on an extremely short storage time of the key pulse computer 5 for the clock synchronization, it can also be stopped instead of resetting the clock. The diagram shown in FIG. 14 then results for the search process. At time t, the clock is stopped for as long as it corresponds to the maximum expected time deviation Λ Τ max. Then (time t 1) a search is carried out at increased speed, as has been described with reference to FIG. 13. If there is no synchronization in the search area Λ Τ *, then at time t_ the clock up to time t. stopped by 2 Δ T max. According to the illustration, synchronization occurs at time t _5. With this method, the storage time of the key pulse computer 5 can also be several minutes or longer, but the synchronization takes place in fractions of a second. 209826/0656

A correlation synchronization device is shown in FIG. 15, which has certain similarities with the embodiment shown in FIG. 12, but whose clock cannot be reset. The synchronization device consists essentially of three feedback shift registers 42, 620 and 610, of which the shift register .42 can be connected to the receiving line 132 via a switch 54 and the shift registers 620 and 610 can be connected to the key pulse generator output 82 via a switch 55. The shift registers 42, 620 and 610 are also connected to a correlator 59. The pseudo-random pulse signal received on line 132 (for example again with a bit length of 10 ms) is stored in shift register 42 and the pseudo-random pulse program generated by its own key pulse generator 5 is stored in shift registers 620 and 610. Again, in the manner described above, "in the circle -Shifting "of the memory contents of the two shift registers (with switches 57 and 58 closed) in the correlator 59 searched for maximum agreement. The time segment corresponding to the maximum time difference to be expected on the transmission and reception side (that is, for example, 5 seconds) is stored in the shift register 620. The clock at the receiving end is advanced by half the expected time difference (i.e. by 2.5 seconds, for example), so a pulse signal can be picked up at the input of the shift register 620 which corresponds to the time advancing by 2.5 seconds. In the middle of the shift register 620, at the tap S, a pulse program could be picked up which ^{corresponds to the "normal 1} 'time, and at the output of the shift register 620 the pulse program, which is 2.5 seconds of the normal time

209826/066 6

corresponds to the lagging time. The shift register 620 can understood as a delay line or "time potentiometer" where from the input to the output pulse signals of different time slots can be picked up, namely in the time domain, which corresponds to the maximum expected time difference. Since the synchronization at the receiving end is the own clock is advanced by 2.5 seconds and accordingly with certainty precedes the received signal and there also the Time comparison is at the output of the delay line shift register 620, is the section contained in the shift register 42 of the pseudo random pulse signal is certain to be contained somewhere in the delay line shift register 620. The one shown Circuit now allows this to be determined in a very short time and with a high clock frequency, but with the clock in continues to run at its normal speed. The synchronization process is as follows:

It is assumed that the pulse length of the pseudo-random Pulse signal on line 132 as well as that of the key pulse generator on line 82 is 10 ms. Further it is assumed that the shift registers 42 and 610 are each implemented with 32 stages and the shift register 620 with 480 stages. Of the The memory content of the shift registers 610 and 620 together with 512 levels thus corresponds to a time of 512 * 10 ms = 5 seconds. It is now assumed that all the shift registers are filled with information from the pseudo random pulse signal be. For the entire search process, switches 54 and 55 remain open, whereas switches 57 and 58 together, respectively

209826/0650 '

, - 38 -.

be closed when the switch 63 is opened and vice versa. First, with fast clock T (switch 53 in the right position) with switches 57 and 58 closed, the information of the shift registers 42 and 610 is once "shifted around" and the correlator 59 determines the total correlation value of the shift register contents. The clock frequency of the clock T ₁ is, for example, 2 MHz, which corresponds to a clock period of O ₁ 5 / xs . If the determined correlation value is less than a certain threshold value, the switch 53 is briefly switched to the clock source T (switch 53 in the middle position), the frequency of which is at most equal to T / 32, for example 62.5 kHz, corresponding to a clock period of 16 ns is. With the switch 63 closed, the contents of the shift registers 610 and 620 are shifted together by one step "in a circle" with this clock T , then the switch 53 switches again to the high-frequency clock T, after which the information im shifted by one step Shift register 610 again the correlation value with the content of the shift register 42 is determined. This procedure, namely diverse character ^H in circles around pushing "and obtain the correlation value, and shifting the information in the shift registers' 610 and 620 by one stage is continued until the correlation value exceeds a certain threshold value. If this is the case, then the time matching the two compared pulse signals found and the synchronization tracking process is complete. from the beginning of the synchronization process until the moment of its completion, the 16- ^ is -Verschiebertakte der.Taktquelle T "with a closed switch 52 by means of a

2098267065Θ

Counter. 49 of the time difference memory 62 is enumerated. in the

the
Counter 49 is now the number of shift steps corresponding to the sending and receiving side time difference stored. A maximum of 512 shift steps are to be carried out for the entire search process, corresponding to the number of stages of the shift registers 610 and 620 together. The maximum time for this is 512 * 16yus _f, i.e. approx. 8.2 ms. The entire synchronization of time differences of up to 5 seconds can be carried out in 8.2 ms. Since this time of 8.2 ms is shorter than the pulse length of the pseudo-random pulse signal of 10 ms, the switches 54 and 55 can remain open during an entire search process. The pseudo-random pulse signal (line 82) emitted by the key pulse generator 5 can either be generated specifically for synchronization purposes and / or a separate key pulse program with the same bit rate can also be output to the shift register, or the pseudo-random pulse signal can be formed by the key pulse program. Since the key pulse program bits must be available at the correct time determined by the synchronization process for the decryption at the receiving end, the information stored in the counter 49 of the time difference memory 62 is also used after the synchronization process to retrieve the correct key pulse bits from the shift register 620 and with them the Carry out decryption. This takes place in that when switch 55 and switch 63 are open and switch 53 is switched to clock T and switch 52 is closed, the shift register contents of delay shift register 620 ¹¹ are "shifted in a circle"

20982 6/06 56

the number determined in the counter 49 runs back to zero and when the zero level is reached via an OR gate 51 and an AND gate 67, the bit located there is sent to the memory location 69 is emitted as a sought key pulse bit. The memory location 69 is connected to the mixer 8 via the line 81 (Fig. 1) connected. This bit corresponds to that, determined by means of the counter 49, time point which corresponds to the received Signal corresponds in time. During the countdown of the counter 49, a second counter 50 is counted up so that the

w determined number is again stored in the counter 50 after the counter 49 has been reset. After the key pulse bit sought has been output, switch 55 is closed and the new bit of the pseudo-random pulse sequence is shifted into the shift register. Then the "correct" bit in the clock T (clock period 16yus) is output again with the time difference number stored in the counter 50, etc. When sending, the program taken from position S in the middle of the delay shift register 620 is sent out which corresponds to the "normal time" ent—

k speaks. This facility has the advantage that neither clock nor the key pulse generator have to be run faster than normal, and that neither a forward nor a backward movement needs to take place. In general, however, this facility is more suitable for time-of-day synchronization with lower Time differences.

In the following figures, exemplary embodiments for the time correction device 4 (Fig.l) are shown. The time corrector forms part of the binary

..209826 / 06S6

Coaster 14 (Fig. 2).

According to FIG. 16, the _{clock signal T (line a) located at point P 1} at the output of a reduction stage U, of the binary divider 14, is reduced to half the clock frequency in the next reduction stage U ", after which at the output of this reduction stage U ₂ or at the output of a OR gate 84 at point P _3, the clock grid T, the line c occurs. Via an UNDER gate 83, at whose first input the clock pulses T and at whose second input the selection pulses E shown in line b - the latter at point P ₂ - can be entered, the clock can be advanced by the time T by such an interspersed pulse. The cycle pattern from P- arrives via an AND gate 85 to the stepper stage U ₃ , at the output of which the cycle pattern shown in line e appears. At the point P _{4 of} the second input, the AND gate 85, a suppressor pulse U (line d) can be entered, which can suppress a pulse of the clock grid of line c, after which the clock grid of line c at the output of the reducer U ₃ by the time value T, is reset. The Ε-impulses that can be entered at P ₂ thus cause the clock to be introduced and the U pulses that can be entered at P. cause the clock to be reset.

In Fig. 17 a multi-stage time correction device 4 is shown, which is also switched on in the binary scaler 14. The illustrated time correction device is suitable however only for advancing the clock and corresponds to the Device as shown in Fig. 16, lines a to c.

209826/065 6

.was shown. With each pulse on the input η, the clock is advanced by the amount of one clock period of the output of the binary scaling stage U,. With each pulse on input n _R , the clock is advanced by a time value corresponding to the clock period of the output of U_, etc. A pulse at n_ causes a time advance four times as large as a pulse on input η (because the effect is 2 binary levels of the binary scaler is distant). Furthermore, a pulse at the input η causes a time advance, because before it is 16 times as large as a pulse at the input η, and a pulse at n_ _T a time advance 64 times as large as at

can.

η. So it can be done in a very short time with single pulses Imagine small, medium and large time units by correcting at different levels of the binary scaler he follows. In this way, time corrections can be carried out in a short time, even on a larger scale. The time correction required can also be taken from the time difference memory 62, which contains binary scaler counting stages 88 to 94 and the stored Enter the time difference in the clock and the binary coaster 14

In Fig. 18 a synchronization variant is shown how it for example, advantageous for teletype transmission with relatively small time deviations at the sending and receiving ends can be used. The key pulse program of the key pulse generator 5 is applied to a delay line shift register 95 ("time potentiometer") via line 81, with .Each level corresponds to an information bit and the word length

the length of a telex character. In the distance of the telex characters The shift register contains 95 taps 96, 97, 98, 99 and 100. The process at the receiving side The clock at the receiving end is synchronized first and thus the receiving-side key pulse program (line 81) is synchronized to the start pulses of the received signal will. If there is a small time difference (of the order of 0.1 second) the relative phase position will now be at most one or two full telex characters apart. By searching with a slide switch 101 on the "time potentiometer" 95 can, by sliding it to the left or right, the position where appears on line 102 when received in clear text can be found quickly. This synchronization can be done by a plain text detector can be carried out fully automatically. The plain text detector can, for example, detect abnormally frequent occurrences Letters or characters like "E" or "space" etc. respond and operate the slide switch 101 until plain text appears.

If, as in the methods shown in FIGS. 5, 6 and 9, the synchronization signal is time information - for example Seconds - contains, then the clock on the receiving side can be corrected by arithmetic addition or subtraction Importance can be adjusted in the shortest possible time.

FIG. 19 shows a section from a synchronization device such as that used for multiple networks can. The by means of the time comparator device 61 between the receiving-side date-time memory 1, or that of

209 8 26/0656

.The clock time difference determined by it controlled key pulse generator 5 and the received signal 1481 can be stored in the time difference memory 62 can be stored via the line 131. Via the line 22 the gate 63, and the line 129 can determine the Clock deviation can be corrected by means of the time correction device 4. The stored time difference value can be used on the one hand Clock resetting to the old gear position after the end of the transmission (via line 22, gate 63, line 129) can be used and on the other hand, are additionally stored in further time difference memories 10 6 or 107 or 108. Each of these additional Memory is each assigned to a subscriber station, for Example memory 106 of a station A, memory 107 of a station B and memory 108 of a station C. first with station A, then the determined time difference value is stored in memory 106. When transitioning to traffic this value remains stored with station B, and the time difference value is determined with station B, etc. If the time difference values have been determined for all stations in the network, then With the help of the stored time difference values, all stations can be contacted with practically no re-synchronization are, since each transition to the traffic with a new station via a switch 105, an AND gate 109 and a line 111 the own clock is set to the determined memory value.

In this context it should be mentioned that with the encryption facility Encrypted data blocks can also be transmitted of the type described. Data blocks can e.g. each be 500 bits

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and be transferable, for example, in half a second. Each data block is preceded by a block start character, e.g. 1111 and provided with the block number. This block number is, for example, the number of seconds at the beginning of the Block transfer was just on the clock. Of course, the time must be at least so detailed that everyone new block receives a new time number. With block lengths of 1/2 second, the time resolution would be 1/4 second on the at the lowest point are quite sufficient. In data transmission technology, it is common to briefly block the blocks on the transmission side to be saved in such a way that they can be re-sent upon request. Inquiries are made using a block number, after which the stored block is sent out again, but with a new block number or a new block number time .

In Fig. 20 it is shown how from the secret key memory 3 date-time-dependent different data packets in the Modulo-2 mixer 18 can be entered. The secret key information is stored in 10-stage shift registers 123, 4 shift registers each forming a shift register package in which the 4 horizontally at the same height standing binary numbers together form a binary coded secret key decimal number form. Each shift register packet thus contains 10 secret key decimal numbers. The shift registers. 123 can be pushed "around in a circle" by means of a return. The output of each shift register leads to a stage a shift register in which a shift line 200

20982 & / 0656

, Information can be shifted to the right. The secret key decimal numbers stored in the shift register packets, which were originally entered in a certain initial position, can be shifted around ¹¹ by the date-time numbers "in a circle using the shift line 124. The secret key decimal numbers are retained, but their position in the shift registers corresponds to the assigned time decimal number and is controlled by the date-time divider part 26. The secret key ™ decimal numbers in the shift register packet on the far right ind by 7 steps, those of the second shift register packet by 0 steps, those of the third shift register packet by 5 steps and those of the shift register package on the far left by 2 steps "im. Circle pushed around ", corresponding to the relevant decimal numbers of the date-time indication. At this time, a secret key combination corresponding only to this time is passed to the shift register stages 122 and used for the encryption.

It goes without saying that practically all of the synchronization devices discussed can be used not only to compensate for the time difference on the sending and receiving sides, but also to automatically compensate for the transmission delay times. These transmission times are normally in the order of magnitude of 10 to 100 ms, but can be somewhat longer under certain circumstances. In determining the transmit and receive side time difference, the transmit and receive side ^ Uebertragungslauf is time with included, it is thus automatically taken into account. «.

209826/0656

Claims (1)

Expectations A method for encrypted message transmission, in which the message clear impulses with key impulses on the sending side mixes and from the cipher thus formed on the receiving side by mixing with identical key pulses the message clear pulses recovered, with the key pulse sequences on the sending and receiving sides in a consistent structure Key pulse generators based on identical rules from a secret basic key and a date and time generated term, characterized in that one chooses the rules for the formation of the key pulse sequences so, that the latter depend only for a limited period of time on the state of their terms at the beginning of this period, and that the Current status of the information contained in all memory cells of the key pulse generator at least during the . Message transmission is constantly influenced by the term derived from the date and time. 2. " The method according to claim 1, characterized in that one The date and time and the term derived from them are constantly changing, both on the sending and receiving side as well as during which allows pauses in transmission to run continuously. 209826 / 06S6 3. ■ Method according to Claim 1, characterized in that the clocks used to generate the date-time terms • So accurate on the sending and receiving sides independently of each other considers that their deviations are within two certain limits (plus, minus) and that one is ahead of the Decryption of the time pulses and / or a pulse sequence determined by the clock in the course of time, such as the Key pulse train or parts thereof from the transmitter to the receiver transmits and with these pulse trains the one generated at the receiving end Key pulse train with the incoming, in particular through Correlation synchronized. Method according to Claim 3, characterized in that the clock at the receiving end is synchronized. Method according to Claim 4, characterized in that the time difference determined at the receiving end is stored and After the message has been transmitted or deciphered, the clock at the receiving end returns the stored value to its earlier gear position set back. The method according to claim 3, characterized in that one 20982 67 0656 on the receiving side, the clock difference remains and only the key pulse sequences are synchronized. Method according to one of Claims 3 to 6, characterized in that that the time differences determined in each case are stored separately for different stations on the receiving side and each time a new connection is established with one of these transmitters, the memory value assigned to it for renewed synchronization used. Method according to one of Claims 3 to 7, characterized in that that the time is represented and transmitted in the form of time impulses of different values and these values so that the lower valences are integer multiples of the higher, the period of the highest Significance greater than twice the maximum permissible clock deviation is and preferably corresponds to the lowest value of the period of the cipher that the time pulse trains makes the individual valences distinguishable from each other by a significant characteristic each, and that one for synchronization these time pulse sequences of the transmitter and receiver in the order from the lowest to the highest valence one after the other brings to cover. 209326/0656 I IbU f JZ 9. The method according to claim 8, characterized in that one assigns a significant amplitude value to the time pulses of the individual valencies. 10. Method according to Claim 8, characterized in that one significant value is added to the time pulses of the individual values Time duration (bit length). 11. ' Method according to Claim 8 _f, characterized in that the pulse sequences of the individual values are represented as a significant periodic pulse pattern each. 12th Method according to one of Claims 4 to 8, characterized in that the time is preferably coded in binary ^ Form represents and within a certain period of time which hereinafter referred to as block time, preferably redundantly transmits, and that synchronization with carries out these coded time indications. 13th Method according to Claim 12, characterized in that the periodic block boundaries are used in the transmitted times marked by a significant, preferably binary code word, 209326/0656 14. ■ Method according to claim. 12, characterized in that one for marking the periodic block boundaries in the transmitted times of every nth (n = 1, 2, 3, ..,) coded time specification allows a code word derived from this by always one and the same specific logical arithmetic operation to follow. The method according to claim 14, characterized in that one in the case of redundant transmission of the coded time information of the respective last time information, a code word derived therefrom lets follow. Method according to Claim 14 or 15, characterized in that the code word marking the block boundary is taken from the the preceding code word containing a time information is derived by adding its individual elements in the order inverts and also inverts every element. 17. -f- ■■■ - A method according to claim 3, characterized in that one is the same on the sending and receiving sides, by the transmitter or. Receiver clock generates a time-determined p-digit impulse template, which templates have the property that they correlate with each other in pairs in p-1 positions' all low correlation values and only in a single one 209826/0656 Position a high correlation value indicates that one the temporal length of this impulse template is greater than that Double the maximum permissible clock deviation selects, that the impulse template generated by the transmitter is sent to the receiver transmits and performs the synchronization there by correlation with the self-generated pulse template, 18th The method according to claim 17, characterized in that one A sequence of identical input pulse templates is generated on the sending and receiving sides, and the synchronization with them Carries out impulse template sequences, 19th Method according to claim 3, characterized in that there is an equal number of p-digit on the sending and receiving sides Generated pulse templates, which are generated at the transmitting end Pulse templates are different from one another and each one of them P with one of the pulse templates generated on the receiving side consistently and where the same templates have the property that they only correlate with one another in one single position result in a high correlation value and in every other position a low one, that the one generated on the receiving side Pulse templates transmitted to the receiver in a chronologically determined manner in succession to the receiver, with the total length of this pulse template sequence is chosen to be greater than twice the maximum permissible clock deviation, 2 0 9 8 2 6/0656 S3 .that the receiving side receives the impulse template sequence arriving from the transmitter in parallel with one of the messages generated by the receiver and time-determined by the receiver's clock Impulse templates are correlated, and that one can use the as first occurring high correlation value performs the synchronization. Method according to claim 3, characterized in that on the sending and receiving sides one each is the same by the transmitter and / or the receiver. Receiver clock time-determined sequence of nothing but identical p-digit impulse templates generates which templates have the property that they correlate with each other only in a single position have a high correlation value result and in every other position a low one, that you can send and receive each one of these impulse templates the associated time in coded form follows that the pulse template sequence generated by the transmitter can be used Receiver transmits and there first by correlation with the self-generated pulse template sequence to the two sequences And then the difference in the coded time of two impulse templates that are in congruence determines and the sequence of the receiving-side clock or key pulse sequence by this difference value in the synchronism shifts. 209826/0656 The method according to claim 3, characterized in that one at the receiving end the one arriving from the sender. and through that Clock time-determined pulse sequence in sections with the incoming from the transmitter and through the transmitter Clock time-determined pulse sequence in sections with the one generated on the receiving side and determined by its clock The pulse sequence is correlated in such a way that for this purpose the receiver clock or the one determined by it in the course of time Pulse sequence stops or resets at least by the maximum admissible time advance and from this position starting with an increased running speed, and that one step with each relative shift the two pulse train sections correlated once. The method according to claim 21, characterized in that one carries out the correlation bit by bit in sequence and for this purpose shifts at least one of the two sections around once in a circle, for which one chooses the step frequency so high that during each bit of the pulse train arriving from the transmitter a complete shoving around in a circle can take place. Method according to Claim 1, characterized in that a non-secret uses pseudo-statistical key. 209826/0658 Procedure according to. Claim 1 or 23, characterized in: that additional number information is used to form the key pulse sequence which preferably a participant, Represents network or address information and for the Message transmission duration remains unchanged. Method according to Claim 1 _f 23 or 24, characterized in that parts are selected from the secret basic key as a function of the date and time and / or the number information and these parts are used to form the key sequence. Process according to one of Claims 23 to 25, characterized in that that one is dependent on the non-secret additional key of date and ear time and / or number information Selects parts and selects these parts to form the Sclaliisselimpulsesequence attracts. Method according to one of Claims 23 to 26, characterized in that that the signal representing the date and time of day can be used with the pseudo-statistical key mixes. 2O9826 / O05S -28. Method according to one or more of the preceding claims, characterized in that the cipher and the pulse sequences used for synchronization are transmitted nested from the transmitter to the receiver. 29 Device for performing the method according to claim 1, with a preferably electronic watch and with a key pulse generator - which with one from the secret Basic key and can be fed from the term derived from the date and time of the control pulse sequence, thereby identifying draws in such a way that the key pulse generator is programmable, that every key pulse at the output of the key pulse generator unaffected by that part of the control pulse train is, which in each case by the so-called lead time before relevant key pulse is, and · that the processing time in time intervals depending on the secret key for each fc a certain time span from a larger to a smaller one Value toggles. 30th Device according to claim 29, characterized in that the Clock is switched as a clock for the key pulse generator. 209826/0656 Device according to one of claims 29 or 30., Characterized by at least one correlation circuit, consisting of at least one shift register for one of the two pulse trains to be correlated, this circuit being connected to one input of a sequential correlation stage with an adjustable threshold value is connected, the other input of which is connected to a generator or a second Shift register for the second pulse train is connected. Device according to Claim 31, characterized in that the shift register which can be switched in a circuit has two different ones Has shift clock frequencies, the first of which is on in the open circuit and with the clock frequency corresponds to the pulse sequence to be correlated and the second is switched on when the circuit is closed and is greater than the first clock frequency multiplied by the number of stages of the shift register connected in a circle. 209826/0656 Blank page