CH364528A - Selbsttaktierendes Leseverfahren für in Serie gespeicherte Impulsfolgen - Google Patents

Selbsttaktierendes Leseverfahren für in Serie gespeicherte Impulsfolgen

Info

Publication number
CH364528A
CH364528A CH6342258A CH6342258A CH364528A CH 364528 A CH364528 A CH 364528A CH 6342258 A CH6342258 A CH 6342258A CH 6342258 A CH6342258 A CH 6342258A CH 364528 A CH364528 A CH 364528A
Authority
CH
Switzerland
Prior art keywords
self
series
reading process
pulse trains
clocking
Prior art date
Application number
CH6342258A
Other languages
English (en)
Inventor
Guenter Dipl Ing Giesecke
Original Assignee
Standard Telephon & Radio Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Standard Telephon & Radio Ag filed Critical Standard Telephon & Radio Ag
Publication of CH364528A publication Critical patent/CH364528A/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
CH6342258A 1957-09-13 1958-08-29 Selbsttaktierendes Leseverfahren für in Serie gespeicherte Impulsfolgen CH364528A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DEST12952A DE1051328B (de) 1957-09-13 1957-09-13 Selbsttaktierendes Leseverfahren fuer in Serie gespeicherte Impulsfolgen

Publications (1)

Publication Number Publication Date
CH364528A true CH364528A (de) 1962-09-30

Family

ID=7455885

Family Applications (1)

Application Number Title Priority Date Filing Date
CH6342258A CH364528A (de) 1957-09-13 1958-08-29 Selbsttaktierendes Leseverfahren für in Serie gespeicherte Impulsfolgen

Country Status (7)

Country Link
US (1) US3069627A (de)
BE (1) BE571151A (de)
CH (1) CH364528A (de)
DE (1) DE1051328B (de)
FR (1) FR1212849A (de)
GB (1) GB857955A (de)
NL (1) NL231353A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1227061B (de) * 1963-06-25 1966-10-20 Siemens Ag Verfahren und Vorrichtung zum Abfragen einer auf einem Informationstraeger gespeicherten Zeichenfolge

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL288506A (de) * 1961-01-04
US3193704A (en) * 1962-07-27 1965-07-06 Richard J C Chueh Pulse amplifier

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2145332A (en) * 1936-01-31 1939-01-31 Rca Corp Television system
US2524710A (en) * 1946-08-13 1950-10-03 Rca Corp Pulse generator system
US2779933A (en) * 1950-03-29 1957-01-29 Itt Complex pulse communication system
NL104332C (de) * 1953-04-20
US2851596A (en) * 1954-04-15 1958-09-09 Hewlett Packard Co Electronic counter
US2807003A (en) * 1955-04-14 1957-09-17 Burroughs Corp Timing signal generation
US2875336A (en) * 1955-08-25 1959-02-24 British Tabulating Mach Co Ltd Electronic signal delay circuits
US2847568A (en) * 1955-10-24 1958-08-12 Hoffman Electronics Corp Distance digital display or the like

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1227061B (de) * 1963-06-25 1966-10-20 Siemens Ag Verfahren und Vorrichtung zum Abfragen einer auf einem Informationstraeger gespeicherten Zeichenfolge

Also Published As

Publication number Publication date
GB857955A (en) 1961-01-04
NL231353A (de)
BE571151A (de)
DE1051328B (de) 1959-02-26
FR1212849A (fr) 1960-03-25
US3069627A (en) 1962-12-18

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