CA945675A - Synchronous read clock apparatus - Google Patents

Synchronous read clock apparatus

Info

Publication number
CA945675A
CA945675A CA113,967A CA113967A CA945675A CA 945675 A CA945675 A CA 945675A CA 113967 A CA113967 A CA 113967A CA 945675 A CA945675 A CA 945675A
Authority
CA
Canada
Prior art keywords
read clock
clock apparatus
synchronous read
synchronous
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA113,967A
Other languages
English (en)
Other versions
CA113967S (en
Inventor
Alfred J. Dellicicchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA945675A publication Critical patent/CA945675A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Magnetic Recording (AREA)
CA113,967A 1970-06-19 1971-05-26 Synchronous read clock apparatus Expired CA945675A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4769670A 1970-06-19 1970-06-19

Publications (1)

Publication Number Publication Date
CA945675A true CA945675A (en) 1974-04-16

Family

ID=21950426

Family Applications (1)

Application Number Title Priority Date Filing Date
CA113,967A Expired CA945675A (en) 1970-06-19 1971-05-26 Synchronous read clock apparatus

Country Status (6)

Country Link
US (1) US3624521A (enExample)
JP (1) JPS556244B1 (enExample)
CA (1) CA945675A (enExample)
DE (1) DE2130372C2 (enExample)
FR (1) FR2095373B1 (enExample)
GB (1) GB1346854A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753143A (en) * 1971-08-05 1973-08-14 Honeywell Inf Systems Phase locked oscillator for integer pulse rates
US3749889A (en) * 1971-08-19 1973-07-31 Interface Ind Inc Reader apparatus for reading record materials at speeds which are independent of recording speeds
US3753142A (en) * 1972-06-12 1973-08-14 Logimetrics Inc Signal generators employing digital phase locked loops and compensating circuits
US4059812A (en) * 1976-11-22 1977-11-22 Control Data Corporation Synchronous pulse generator including flywheel tank circuit with phase locked loop
CA1207845A (en) * 1984-07-23 1986-07-15 Leslie M. Koskinen Adaptively tuned clock recovery circuit
IT1185412B (it) * 1985-10-10 1987-11-12 Honeywell Inf Systems Tseparatore digitale di dati
US5192915A (en) * 1991-06-19 1993-03-09 Tektronix, Inc. Edge integrating phase detector

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328719A (en) * 1965-08-24 1967-06-27 Sylvania Electric Prod Phase-lock loop with adaptive bandwidth
US3518554A (en) * 1967-05-22 1970-06-30 Honeywell Inc Detection of double transition recording
US3510786A (en) * 1967-07-17 1970-05-05 Ibm Synchronizing circuit compensating for data bit shift
US3488605A (en) * 1968-05-15 1970-01-06 Slant Fin Corp Oscillator with digital counter frequency control circuits

Also Published As

Publication number Publication date
US3624521A (en) 1971-11-30
FR2095373B1 (enExample) 1973-06-29
FR2095373A1 (enExample) 1972-02-11
DE2130372A1 (de) 1971-12-23
DE2130372C2 (de) 1984-06-07
JPS556244B1 (enExample) 1980-02-14
GB1346854A (en) 1974-02-13

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