CA2978535A1 - Emetteur et procede de permutation de parite associe - Google Patents
Emetteur et procede de permutation de parite associe Download PDFInfo
- Publication number
- CA2978535A1 CA2978535A1 CA2978535A CA2978535A CA2978535A1 CA 2978535 A1 CA2978535 A1 CA 2978535A1 CA 2978535 A CA2978535 A CA 2978535A CA 2978535 A CA2978535 A CA 2978535A CA 2978535 A1 CA2978535 A1 CA 2978535A1
- Authority
- CA
- Canada
- Prior art keywords
- bits
- ldpc
- parity
- group
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
Abstract
La présente invention se rapporte à un émetteur. L'émetteur comprend : un codeur à contrôle de parité de faible densité (LDPC) configuré pour coder des bits d'entrée afin de générer des bits de parité; un permutateur de parité configuré pour entrelacer groupe par groupe une pluralité de groupes de bits comprenant les bits de parité; et un dispositif de poinçonnage configuré pour sélectionner certains des bits de parité dans les groupes de bits entrelacés groupe par groupe et poinçonner les bits de parité sélectionnés, le permutateur de parité entrelaçant groupe par groupe les groupes de bits de telle sorte que certains des groupes de bits, en des emplacements prédéterminés dans les groupes de bits avant l'entrelacement groupe par groupe sont positionnés de manière sérielle après l'entrelacement groupe par groupe et un reste de groupes de bits, avant l'entrelacement groupe par groupe, est positionné sans ordre après l'entrelacement groupe par groupe de sorte que le dispositif de poinçonnage sélectionne des bits de parité compris dans certains des groupes de bits séquentiellement et sélectionne des bits de parité compris dans le reste des groupes de bits sans ordre.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA3209954A CA3209954A1 (fr) | 2015-03-02 | 2016-03-02 | Emetteur et procede de permutation de parite associe |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201562127014P | 2015-03-02 | 2015-03-02 | |
US62/127,014 | 2015-03-02 | ||
KR1020150137188A KR102426780B1 (ko) | 2015-03-02 | 2015-09-27 | 송신 장치 및 그의 패리티 퍼뮤테이션 방법 |
KR10-2015-0137188 | 2015-09-27 | ||
PCT/KR2016/002091 WO2016140513A1 (fr) | 2015-03-02 | 2016-03-02 | Émetteur et procédé de permutation de parité associé |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA3209954A Division CA3209954A1 (fr) | 2015-03-02 | 2016-03-02 | Emetteur et procede de permutation de parite associe |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2978535A1 true CA2978535A1 (fr) | 2016-09-09 |
CA2978535C CA2978535C (fr) | 2023-10-17 |
Family
ID=56950313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA2978535A Active CA2978535C (fr) | 2015-03-02 | 2016-03-02 | Emetteur et procede de permutation de parite associe |
Country Status (4)
Country | Link |
---|---|
KR (1) | KR102426780B1 (fr) |
CN (1) | CN107567692B (fr) |
CA (1) | CA2978535C (fr) |
MX (1) | MX2017011153A (fr) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7706455B2 (en) * | 2005-09-26 | 2010-04-27 | Intel Corporation | Multicarrier transmitter for multiple-input multiple-output communication systems and methods for puncturing bits for pilot tones |
KR101503058B1 (ko) * | 2008-02-26 | 2015-03-18 | 삼성전자주식회사 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서의 채널 부호화/복호화 방법 및 장치 |
CN101807966B (zh) * | 2009-02-13 | 2012-12-12 | 瑞昱半导体股份有限公司 | 奇偶校验码解码器及接收系统 |
PL2387172T3 (pl) * | 2010-05-11 | 2020-01-31 | Electronics And Telecommunications Research Institute | Sposób wysyłania informacji o randze kanału zstępującego przez fizyczny, współdzielony kanał wstępujący |
KR20150005426A (ko) * | 2013-07-05 | 2015-01-14 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
KR20150005853A (ko) * | 2013-07-05 | 2015-01-15 | 삼성전자주식회사 | 송신 장치 및 그의 신호 처리 방법 |
-
2015
- 2015-09-27 KR KR1020150137188A patent/KR102426780B1/ko active IP Right Grant
-
2016
- 2016-03-02 CN CN201680025662.1A patent/CN107567692B/zh active Active
- 2016-03-02 MX MX2017011153A patent/MX2017011153A/es active IP Right Grant
- 2016-03-02 CA CA2978535A patent/CA2978535C/fr active Active
Also Published As
Publication number | Publication date |
---|---|
CA2978535C (fr) | 2023-10-17 |
CN107567692B (zh) | 2020-09-04 |
KR102426780B1 (ko) | 2022-07-29 |
CN107567692A (zh) | 2018-01-09 |
KR20160106476A (ko) | 2016-09-12 |
MX2017011153A (es) | 2017-11-09 |
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Legal Events
Date | Code | Title | Description |
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EEER | Examination request |
Effective date: 20210224 |
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EEER | Examination request |
Effective date: 20210224 |
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EEER | Examination request |
Effective date: 20210224 |
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EEER | Examination request |
Effective date: 20210224 |
|
EEER | Examination request |
Effective date: 20210224 |
|
EEER | Examination request |
Effective date: 20210224 |
|
EEER | Examination request |
Effective date: 20210224 |