CA2826572A1 - System and method for synchronizing processor instruction execution - Google Patents

System and method for synchronizing processor instruction execution Download PDF

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Publication number
CA2826572A1
CA2826572A1 CA2826572A CA2826572A CA2826572A1 CA 2826572 A1 CA2826572 A1 CA 2826572A1 CA 2826572 A CA2826572 A CA 2826572A CA 2826572 A CA2826572 A CA 2826572A CA 2826572 A1 CA2826572 A1 CA 2826572A1
Authority
CA
Canada
Prior art keywords
instructions
processor
total number
time
iterations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA2826572A
Other languages
English (en)
French (fr)
Inventor
William David Ii Smith
Safayet Nizam Ahmed
John Marc Diekeman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CA2826572A1 publication Critical patent/CA2826572A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/182—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits based on mutual exchange of the output between redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/815—Virtual

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
CA2826572A 2012-09-14 2013-09-05 System and method for synchronizing processor instruction execution Abandoned CA2826572A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/620,047 US9342358B2 (en) 2012-09-14 2012-09-14 System and method for synchronizing processor instruction execution
US13/620,047 2012-09-14

Publications (1)

Publication Number Publication Date
CA2826572A1 true CA2826572A1 (en) 2014-03-14

Family

ID=49162034

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2826572A Abandoned CA2826572A1 (en) 2012-09-14 2013-09-05 System and method for synchronizing processor instruction execution

Country Status (6)

Country Link
US (1) US9342358B2 (enExample)
EP (1) EP2709010B1 (enExample)
JP (1) JP6196855B2 (enExample)
CN (1) CN103677756B (enExample)
BR (1) BR102013021930A2 (enExample)
CA (1) CA2826572A1 (enExample)

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US9996431B2 (en) * 2016-03-23 2018-06-12 GM Global Technology Operations LLC Architecture and apparatus for advanced arbitration in embedded controls
FR3052890B1 (fr) 2016-06-21 2018-07-13 Thales Sa Procede de reception garantie de signaux communs dans un systeme avionique comportant une pluralite de calculateurs electroniques
CN106445852B (zh) * 2016-08-12 2019-05-14 中国航空工业集团公司西安飞行自动控制研究所 一种基于自监控架构的任务间通讯装置与方法
US10452446B1 (en) * 2017-06-07 2019-10-22 Rockwell Collins, Inc. High integrity multi-core processing
CN111767078B (zh) * 2019-04-02 2024-08-06 上海寒武纪信息科技有限公司 数据运行方法、装置和相关产品
FR3108993A1 (fr) * 2020-04-07 2021-10-08 Airbus Operations Procédé et système de synchronisation d’unités de calcul d’un aéronef.

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JPH0773059A (ja) 1993-03-02 1995-03-17 Tandem Comput Inc フォールトトレラント型コンピュータシステム
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US5572620A (en) 1993-07-29 1996-11-05 Honeywell Inc. Fault-tolerant voter system for output data from a plurality of non-synchronized redundant processors
JPH07175765A (ja) * 1993-10-25 1995-07-14 Mitsubishi Electric Corp 計算機の障害回復方法
US5557623A (en) 1994-08-12 1996-09-17 Honeywell Inc. Accurate digital fault tolerant clock
US5742753A (en) 1996-06-06 1998-04-21 The Boeing Company Mesh interconnected array in a fault-tolerant computer system
US5896523A (en) 1997-06-04 1999-04-20 Marathon Technologies Corporation Loosely-coupled, synchronized execution
DE69804489T2 (de) 1997-11-14 2002-11-14 Marathon Technologies Corp., Boxboro Verfahren zur erhaltung von synchronisierter ausführung bei fehler-betriebssicheren/ fehlertoleranten rechnersystemen
US6374364B1 (en) 1998-01-20 2002-04-16 Honeywell International, Inc. Fault tolerant computing system using instruction counting
US6247143B1 (en) * 1998-06-30 2001-06-12 Sun Microsystems, Inc. I/O handling for a multiprocessor computer system
US6367031B1 (en) 1998-12-17 2002-04-02 Honeywell International Inc. Critical control adaption of integrated modular architecture
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US6633969B1 (en) * 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
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US6948091B2 (en) 2002-05-02 2005-09-20 Honeywell International Inc. High integrity recovery from multi-bit data failures
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US7558883B1 (en) 2002-06-28 2009-07-07 Microsoft Corporation Fast transaction commit
JP2004046599A (ja) * 2002-07-12 2004-02-12 Nec Corp フォルトトレラントコンピュータ装置、その再同期化方法及び再同期化プログラム
US7620680B1 (en) 2002-08-15 2009-11-17 Microsoft Corporation Fast byzantine paxos
US8005888B2 (en) 2003-12-30 2011-08-23 Microsoft Corporation Conflict fast consensus
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Also Published As

Publication number Publication date
JP2014059870A (ja) 2014-04-03
CN103677756B (zh) 2018-08-10
US9342358B2 (en) 2016-05-17
EP2709010A1 (en) 2014-03-19
CN103677756A (zh) 2014-03-26
US20140082331A1 (en) 2014-03-20
EP2709010B1 (en) 2016-11-09
JP6196855B2 (ja) 2017-09-13
BR102013021930A2 (pt) 2015-01-27

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Legal Events

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EEER Examination request

Effective date: 20180703

FZDE Discontinued

Effective date: 20220406

FZDE Discontinued

Effective date: 20220406