CA2711027C - Low power fir filter in multi-mac architecture - Google Patents

Low power fir filter in multi-mac architecture Download PDF

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Publication number
CA2711027C
CA2711027C CA2711027A CA2711027A CA2711027C CA 2711027 C CA2711027 C CA 2711027C CA 2711027 A CA2711027 A CA 2711027A CA 2711027 A CA2711027 A CA 2711027A CA 2711027 C CA2711027 C CA 2711027C
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Canada
Prior art keywords
multiply
accumulator
adder
accumulators
output
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CA2711027A
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English (en)
French (fr)
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CA2711027A1 (en
Inventor
Jeffrey Allan Jacob
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Ceva DSP Ltd
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Ceva DSP Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CA2711027A 2009-07-30 2010-07-29 Low power fir filter in multi-mac architecture Active CA2711027C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/512,032 2009-07-30
US12/512,032 US8706791B2 (en) 2009-07-30 2009-07-30 Low power fir filter in multi-MAC architecture

Publications (2)

Publication Number Publication Date
CA2711027A1 CA2711027A1 (en) 2011-01-30
CA2711027C true CA2711027C (en) 2016-05-10

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Family Applications (1)

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CA2711027A Active CA2711027C (en) 2009-07-30 2010-07-29 Low power fir filter in multi-mac architecture

Country Status (4)

Country Link
US (1) US8706791B2 (enExample)
EP (1) EP2280341B1 (enExample)
JP (1) JP5544240B2 (enExample)
CA (1) CA2711027C (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112602054B (zh) 2018-08-31 2024-06-25 弗莱克斯-罗技克斯技术公司 乘法器累加器电路、用于乘法累加的逻辑瓦片架构和包括逻辑瓦片阵列的ic
JP7165018B2 (ja) * 2018-10-03 2022-11-02 キヤノン株式会社 情報処理装置、情報処理方法
US11194585B2 (en) 2019-03-25 2021-12-07 Flex Logix Technologies, Inc. Multiplier-accumulator circuitry having processing pipelines and methods of operating same
US11314504B2 (en) 2019-04-09 2022-04-26 Flex Logix Technologies, Inc. Multiplier-accumulator processing pipelines and processing component, and methods of operating same
US11288076B2 (en) 2019-09-13 2022-03-29 Flex Logix Technologies, Inc. IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
US11455368B2 (en) 2019-10-02 2022-09-27 Flex Logix Technologies, Inc. MAC processing pipeline having conversion circuitry, and methods of operating same
US12015428B2 (en) 2019-11-05 2024-06-18 Flex Logix Technologies, Inc. MAC processing pipeline using filter weights having enhanced dynamic range, and methods of operating same
US11693625B2 (en) 2019-12-04 2023-07-04 Flex Logix Technologies, Inc. Logarithmic addition-accumulator circuitry, processing pipeline including same, and methods of operation
US11960856B1 (en) 2020-01-15 2024-04-16 Flex Logix Technologies, Inc. Multiplier-accumulator processing pipeline using filter weights having gaussian floating point data format
US11442881B2 (en) 2020-04-18 2022-09-13 Flex Logix Technologies, Inc. MAC processing pipelines, circuitry to control and configure same, and methods of operating same
US12282748B1 (en) 2020-05-26 2025-04-22 Analog Devices, Inc. Coarse floating point accumulator circuit, and MAC processing pipelines including same
WO2022020164A1 (en) 2020-07-22 2022-01-27 Flex Logix Technologies, Inc. Mac processing pipelines having programmable granularity, and methods of operating same
WO2022039914A1 (en) 2020-08-20 2022-02-24 Flex Logix Technologies, Inc. Configurable mac pipelines for finite-impulse-response filtering, and methods of operating same
US12455723B2 (en) 2021-02-02 2025-10-28 Analog Devices, Inc. MAC processing pipeline having activation circuitry, and methods of operating same
US12461713B2 (en) 2021-03-03 2025-11-04 Analog Devices, Inc. MAC processing pipelines, circuitry to configure same, and methods of operating same
US12430100B2 (en) * 2021-06-01 2025-09-30 Ceremorphic, Inc. Analog multiplier accumulator with unit element gain balancing
CN120045162B (zh) * 2025-04-25 2025-09-16 北京凯芯微科技有限公司 一种抗混叠降采样电路、电路模组、芯片和信号处理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3693367B2 (ja) * 1994-07-28 2005-09-07 富士通株式会社 積和演算器
US5931892A (en) * 1996-12-20 1999-08-03 Compaq Computer Corporation Enhanced adaptive filtering technique
US5862063A (en) * 1996-12-20 1999-01-19 Compaq Computer Corporation Enhanced wavetable processing technique on a vector processor having operand routing and slot selectable operations
JPH1196136A (ja) 1997-09-24 1999-04-09 Fujitsu Ltd 積和演算モジュール
JP2002073586A (ja) 2000-08-28 2002-03-12 Matsushita Electric Ind Co Ltd 演算処理装置
US6978287B1 (en) * 2001-04-04 2005-12-20 Altera Corporation DSP processor architecture with write datapath word conditioning and analysis
US7570704B2 (en) * 2005-11-30 2009-08-04 Intel Corporation Transmitter architecture for high-speed communications

Also Published As

Publication number Publication date
US8706791B2 (en) 2014-04-22
EP2280341B1 (en) 2013-06-05
JP2011034566A (ja) 2011-02-17
US20110029589A1 (en) 2011-02-03
EP2280341A1 (en) 2011-02-02
CA2711027A1 (en) 2011-01-30
JP5544240B2 (ja) 2014-07-09

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