CA2594947A1

CA2594947A1 - Iii/v semiconductor

Info

Publication number: CA2594947A1
Application number: CA002594947A
Authority: CA
Inventors: Bernardette Kunert; Joerg Koch; Stefan Reinhard; Kerstin Volz; Wolfgang Stolz
Original assignee: Individual
Current assignee: Philipps Universitaet Marburg
Priority date: 2005-01-26
Filing date: 2006-01-26
Publication date: 2006-08-03
Anticipated expiration: 2026-01-26
Also published as: EP1842268B1; JP2019075540A; JP6748156B2; WO2006079333A2; JP2015167249A; KR20070092752A; JP2016213488A; KR101320836B1; WO2006079333A3; JP5369325B2; JP2013102209A; CA2594947C; EP1842268A2; JP2008529260A

Abstract

The invention relates to a monolithic integrated semiconductor structure comprising a carrier layer based on doped Si or doped GaP and a III/V
semiconductor arranged on said carrier layer, with the composition Gaxlny-NaAsbPcSbd, where x = 70 - 100 mol, y = 0 - 30 mol %, a = 0.5 - 15 mol %, b =
67.5 99.5 mol %, c = 0 32.0 mol %, and d = 0 - 15 mol %. According to the invention, x and y always add up to 100 mol %, and a, b, c and d always add up to 100 mol %. The ratio of the sums of x and y to a, b, c and d is essentially equal to 1:1. The invention also relates to a method for the production of said semiconductor structure, and to the use thereof for producing light-emitting diodes and laser diodes, or modulator and detector structures that are monolithically integrated into integrated circuits based on Si or GaP
technology.

Description

III/V semiconductor.

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Field of the invention.

The invention relates to a new III/V semicon-ductor, a semiconductor layer consisting of such a semiconductor, a monolithically integrated semiconductor structure comprising~ such a semi-conductor layer, the uses of such a semiconduc-tor or of such a semiconductor layer, and a method for the production of such a semiconduc-tor layer.

Background of the invention and prior art.

In the field of computer technology, there is a continuously growing demand for higher proc-es-sing and signal conduction capacities in con-junction with a high reliability and flexibil-ity. In the past, the chip technology has made a rapid progress with regard to integration den-sity and working speeds or cycle frequencies.
With this trend further advancing, problems are coming up for the connection of fast chips.

Critical aspects in conjunction with high-speed connections are reliability, cost, on-chip driver size and performance, crosstalk, signal distortions and lack of flexibility in the chip design. Connections between chips by using opto-electronic components and optical waveguides are a solution for many connection problems. Optical connections have an extremely high bandwidth and are comparatively insensitive against crosstalk and other interferences. By using these proper-ties of optical connections, it may become pos-sible to connect high-speed chips with each other by optical channels and to achieve a con-siderable improvement with regard to connection density, current consumption, interferences and crosstalk.

Usually high-integrated circuits are based on the Si technology. Silicium is however an indi-rect semiconductor, and the production of effi-cient optoelectronic components using the Si technology is consequently hardly possible. Ef-ficient optoelectronic components can however be produced by using the technology of the III/V
semiconductors, for instance the GaAs technol-ogy, since these semiconductors are often direct semiconductors consequently emitting and absorb-ing light with a high efficiency.

For producing integrated circuits, commonly the epitaxial process is employed. If now con-tacts between layers on the basis of the Si technology and layers on the basis of the tech-nology of the III/V semiconductor are to be made, it is problematic that the lattice con-stants of the respective materials are different (this also applies to GaP substrates instead of Si substrates). This has as a consequence that during the epitaxial growth of III/V semiconduc-tors on Si (or GaP) substrates, dislocations are created. Such dislocations however disturb the function of the complete semiconductor structure to a substantial degree, the more since the functional layer thicknesses are today in the order of atomic dimensions. In the case of high layer thicknesses, the difference of the lattice constants even leads to bends of the substrate.
The reason for this is basically that with high deposition temperatures an epitaxial growth of III/V semiconductors takes place ~on Si or GaP
semiconductors, however the generation of dislo-cations begins already at less high deposition temperatures. If then the semiconductor struc-ture cools down to ambient temperature, the dif-ferences of the lattice constants caused by the different thermal expansion coefficients will lead to the above stresses and dislocations.

For eliminating the above problems, various approaches exist. In the document EP 0380815 B1 there is described that GaAs layers can be de-posited on a Si substrate and form defined mi-crocracks at predetermined positions, thus dis-locations of the Si substrate being avoided, at least however reduced. This technology is how-ever not suitable for high-integrated circuits because of the lacking controllability of micro-cracks in atomic scales.

The document EP 0297483 describes a hybrid integrated semiconductor structure, wherein on a Si substrate an integrated circuit on the basis of the Si technology is applied. Further, an op-tically active element in GaAs technology is provided on the Si substrate. An electrical con-nection between the integrated circuit and the optically active element is however not estab-lished by a direct contact or by the Si substrate, but rather by an electrical wire con-nection. This technology, too, is not suitable for applications in high-integrated circuits.

From the document DE 10355357 it is known, for layer structures with optically active ele-ments on the basis of III/V semiconductors, to compensate dislocations caused by lattice con-stants for instance by adaptation layers sub-jected to tensile stress. By the insofar known measures, a modeling of electronic properties is also possible, and thus emission wavelengths not accessible up to now become accessible.
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From the document US 2004/0135136 Al, a mul-titude of different III/V semiconductors are known in the art, and they are always layers, which are not suitable for application on a Si substrate. Corresponding considerations apply to the documents EP 1257026 A2, US 6,233,264 B1, US
2004/0084667 A2, Merz et al., IEE Proc.-Opto-electron. 151(5):346-351 (2004), US 6,072,196, EP 1553670 A2, US 5,825,796, Ishizuka et al., Journal of Crystal Growth 272:760-764 (2004) and US 2004/0161009 Al.

In the document EP 0896406 A2 there are de-scribed layers of optically active III/V semi-conductors on GaP or Si substrates (and others), and these layers contain exclusively In as the III component. In fact, such layers are only suitable for InP substrates and form undesirably many dislocations and faults on Si or GaP sub-strates. The document US 5,937,274 describes in a very general manner different layers on dif-ferent substrates.
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As a result, there continues being a need in particular for the field of high-integ,rated cir-cuits to connect subassemblies or layer se-quences on the basis of the Si technology and on the basis of the III/V semiconductor monolithi-cally with each other.

Technical object of the inve-ntion.

It is a technical object of the invention to propose means for providing optically active elements on the basis of the III/V semiconduc-tors on substrates of the Si technology or GaP
technology, wherein the conduction of electrical signals of the Si based or GaP-based subassem-blies to and from the optically active elements is integrally formed, i.e. by contact of layers, and that practically free from dislocations forming nonradiative recombination centers in the III/V semiconductor or at the border face thereof to the layer underneath. It is further a technical object of the invention to propose stable luminescence and laser components on Si substrates or GaP substrates, which are directly contacted, i.e. by layer contact. It is another technical obj.ect of the invention to provide a monolithically integrated semiconductor struc-ture, which emits directly, i.e. without wire-bound connection lines, data currents from a Si-technology based processor circuitry as an opti-cal signal. Further, it is an object of the in-vention to propose a monolithically integrated semiconductor structure, by means of which emit-ted optical signals can also be modulated and/or detected.

Basics of the invention and embodiments.

For achieving this technical object, the in-vention teaches monolithically integrated semi-conductor structures according to claim 1 with Si or GaP substrates and a III/V semiconductor having the composition GaXlnyNaAsbPCSbd, wherein x = 70 - 100 mole-%, y = 0 - 30 mole-%, a 0.5 - 15 mole-%, b = 67.5 - 99.5 mole-%, c 0-32.0 mole-% and d = 0 15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand and of a to d on the other hand is substantially 1:1. Preferably, y = 1- 30 mole-%, and c = 1 - 32.0 mole-%, and such a semiconductor per se.

In the case of a P-free system, In and/or Sb should be comprised, since these elements mini-mize, like P, the local distortion fields caused by the N-incorporation.

III/V semiconductors having the following compositions are particularly preferred:

a) x = 70 - 100 mole-%, y = 0 - 30 mole-%, a 0.5 - 10 mole-%, b = 70 - 98.5 mole-%, c 1-29.5 mole-%, or b)x = 85 - 99 mole-%, y 1 - 15 mole-%, a 0.5 - 10 mole-%, b = 70 - 98.5 mole-%, c = 1 29.5 mole-%, or c) x= 85 - 99 mole-%, y = 1-- 15 mole-%, a 0.5 - 10 mole-%, b 70 - 98.5 mole-%, c= 0 - 32 mole-% and d = 1 10 mole-%.

In particular, x=>70 - 100 mole-%, a = >1.3 or >1.7 mole-% (optionally in connection with y > 0 or 1 mole-%) , c = 0 - 32 mole-% and/or b 60 - 99.5 mole-%. Preferred is also c = or be-tween 4 - 8 mole-%. Preferred is also a = 4 or 5.5 - 11 mole-%.

The semiconductor class according to the in-vention of the mixed crystal system GaInNAsPSb is characterized, on the one hand, by that be-cause of the composition, presumably of the ad-dition of nitrogen and/phosphorus, layer se-quences adapted to the lattice or compressively stressed can be produced on GaP and/or Si sub-strates, without causing dislocations. On the other hand, beginning from a nitrogen concentra-tion of > 0.5 mole-% in conjunction with the phosphorus content, an interaction of the elec-tronic levels caused by the incorporation of ni-trogen with the conduction band states of the nitrogen-free mixed crystal system at the r point will occur, which will lead to an effec-tive red shift of the fundamental energy gap at the r point and thus strengthen the character as a direct semiconductor of the GaInNAsPSb mate-rial system. For instance, for a = 1 - 10 mole-%, b = 60 - 95 mole-% and c 2 - 15 mole-%, preferably a = 3 - 5 mole-%, b 85 - 95 mole-%
and c-- 4 - 8 mole-%, there will result a funda-mental energy gap of distinctly less than 1.8 eV, even down to 1.4 eV and smaller. This makes clear the drastic influence of the energy gap by the composition of this semiconductor system ac-cording to the invention.

In detail, the invention relates to a mono-lithically integrated semiconductor structure . -;~;..
comprising the following layer structure:

A) a carrier layer on the basis of doped or undoped Si or GaP, B) as an option, a first current-conducting layer composed of doped Si, doped GaP or doped (AlGa)P, C) as an option, a first adaptation layer, and D) an optically active element comprising a semiconductor layer according to the invention.
To the layer D), the below layers may follow:
E) optionally a second adaptation layer and F) a second current-conducting layer composed of doped Si or doped GaP or doped (AlGa) P. In case of the (AlGa) P, the share of Al may be 20 - 100 mole-%, and the total of the shares of Al and Ga is always 100 mole-o. The layer B) may be p or n-doped. In case that the layer F) is present, the layer F) may be p-doped, if layer B) is n-doped, and vice versa.

Normally, the optical element will have a layer structure (D1-D2-D3)n, wherein the layer D2 is a quantum well layer, of a semiconductor according to the invention, wherein the layers Dl and D3 are barrier layers, and wherein n = 1 - 15. By such an optically active element, lumi-nescence diodes as well a's laser diodes can be built up. Following one of the terminal layers Dl or D3, a barrier layer D4 may be provided. It may be recommended that the barrier layers are semiconductors having the composition Gap_ InqNrPsAst, wherein p = 85 - 100 mole-%, q= 0 -15 mole-%, r 0 - 15 mole-%, s= 60 - 100 mole-% and t = 0 40 mole-%, wherein the total of p and q is always 100 mole-%, wherein the total of r, s and t is always 100 mole-%, and wherein the ratio of the totals of p and q on the one hand and of r to t on the other hand is substantially 1:1, and wherein the barrier layer has a layer thickness of preferably 5 - 50 nm. Preferred ranges are: p 90 - 100 mole-%, q = 0 - 10 mole-%, r 0 10 mole-%, s = 70 - 100 mole-%
and t = 0 30 mole-%. For the layer thickness, a range of 2 - 20 nm is preferred. An adaptation layer may be a semiconductor having the composi-tion GapInqNzPSAst, wherein p = 90 - 100 mole-%, q = 0 - 10 mole-%, r 0 - 10 mole-%, s = 70 -100 mole-% and t = 0 30 mole-%, wherein the total of p and q is always 100 mole-%, wherein the total of r, s and t is always 100 mole-%, and wherein the ratio of the totals of p and q on the one hand and of r to t on the other hand is substantially 1:1, and wherein the adaptation layer has a layer thickness of preferably 50 -500 nm.

In the monolithically integrated semiconduc-tor structure according to the invention, a cur-rent-conducting layer and/or barrier layer dis-posed between the carrier layer and the opti-cally active element may be at the same time an adaptation layer.

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Underneath and/or above the optically active element, at least one optical waveguide layer may be provided, which is optically coupled to the optically active element. In this way, data currents can be guided as optical signals from the emitting optically active element to an op-tical receiver at a different place on the car-rier. It is understood that other elements may additionally or alternatively be used for con-ducting optical signals, such as fibers or the like.

A luminescence diode or also a vertically emitting laser diode may be produced by that be-tween the layers A) and D) and/or outside the layer F) , there is provided at least one peri-odic reflection structure.

Preferably, the optically active element has a fundamental emission wavelength in the range of 700 - 1,100 nm.

The invention further relates to the use of a semiconductor according to the invention or a semiconductor layer according to the invention for the production of a luminescence diode (LED), a VCSEL (vertical cavity surface emitting laser) laser diode or a VECSEL (vertical exter-nal cavity surface emitting laser) laser diode and a modulator or a detector structure.

Finally, the invention relates to a method for the production of a semiconductor layer ac-cording to the invention comprising the follow-ing steps: a substrate on the basis of doped or undoped Si or GaP is brought into a MOVPE
(metal-organic vapor phase epitaxy) apparatus, optionally a surface of the substrate is pro-vided in at least one epitaxial coating step first with respectively at least one adaptation layer, one barrier layer, one current-conducting layer, one waveguide layer and/or one reflection structure, a carrier gas is loaded with educts in defined concentrations, the loaded carrier gas is conducted over the surface of the sub-strate heated to a temperature in the range of 300 C to 700 C or on the surface of the upper-most layer on the substrate for a defined dura-tion of exposure, and the total concentration of the educts and the duration of exposure are ad-justed to each other such that the semiconductor layer is epitaxially formed with a given layer thickness on the surface of the substrate or on the surface of the uppermost layer on the sub-strate.

Preferably, the following educts are used for the MOVPE technology: CI-C5 trialkylgallium, in particular triethylgallium (Ga(C2H5)3) and/or trimethylgallium (Ga(CH3)3), as a Ga educt, C1-C5 trialkylindium, in particular trimethylindium (In (CH3) 3) , as an In educt, arnmonia (NH3), mono(C1-C8)alkylhydrazine, in particular terti-arybutylhydrazine (t-(C4H9)-NH-NH2), and/or 1,1-di(C1-C5)alkylhydrazine, in particular 1,1-di-methylhydrazine ((CH3)2-N-NH2), as an N educt, 20 arsine (AsH3) and/or C1-C5 alkylarsine, in par-ticular tertiarybutylarsine (t-(C9H9)-AsH2), as an As educt, phosphine (PH3) and/or Cl-C5 alkyl-phosphine, in particular tertiarybutylphosphine (t-(C4H9)-PH2), as a P educt, and C1-C5 trialkyl-antimony, in particular trimethylantimony ((CH3)3Sb) and/or triethylantimony ((C2H5)3Sb), as an Sb educt, wherein the C3-C5 alkyl groups may be linear or branched.

Preferably, the educts are employed in the following molar ratios: As educt/group III
educts 5 - 300, P educt/group-III educts 0 -500, N educt/As educt 0.1 - 10, optionally Sb educt/As educt 0 - 1, wherein the surface tem-perature of the substrate is adjusted to the range from 500 C to 630 C, wherein the total pressure of carrier gas and educts is adjusted to the range from 10 to 1,000 hPa or to 200 hPa, wherein the ratio of the total of the partial pressure of all educts to the partial pressure of the carrier gas is between 0.005 and 0.1, and wherein the deposition rate is 0.1 to 10 pm/h.
In particular the following ratios may be em-ployed: As educt/group III educts 10 - 100, for instance 10 - 30, P educt/group III educts 1 -100, for instance 1 10, N educt/As educt 1 -10, for instance 3 S. The surface temperature may preferably be in the range from 500 C to 650 C, in particular 550 C to 600 C. The total pressure of carrier gas and educts may be in the range from 20 to 100 hPa. The ratio of the par-tial pressure of all educts to the partial pres-sure of the carrier gas may be in the range from 0.01 to 0.05. The deposition rate may be between 0.1 and 5 pm/h, in particular 0.5 and 3 pm/h.

In principle, the precise concentrations of the educts depend on the thermal decomposition properties of the respective educts in the MOVPE
process. The growth speed of the layer is deter-mined by the concentrations of the group III
educts. On the basis of various decomposition properties of the Ga and if applicable In educts, known to the man skilled in the art, de-pending on the selected deposition temperature (surface temperature of the substrate), suitable educt concentrations are adjusted, which will lead to the desired group III concentrations of the respective elements in the semiconductor layer according to the invention. Because of the known temperature-dependent incongruent vapori-zation of the group V educts or species of the growth surface of the III/V semiconductors, the respective group V educt concentrations in the MOVPE deposition should carefully be adjusted to the desired concentrations in the semiconductor layer according to the invention as a function of the selected deposition temperature in the excess. This is easily achievable for the man skilled in the art. For higher deposition tem-peratures or educts that cannot easily be decom-posed, if applicable, higher V/III ratios, but also higher N/As ratios than melationed above have to be selected. For lower deposition tem-peratures, correspondingly the reversed behavior applies.

Alternatively to MOVPE, of course other epi-taxial methods can also be employed, such as MBE
(molecular beam epitaxy), also under inclusion of gas sources in particular for the group V
components (gas source MBE, GS-MBE), CBE (chemi-cal beam epitaxy) or also MOMBE (metal-organic molecular beam epitaxy). These methods can be carried out by means of the usual and per se known epitaxy apparatuses, and the respectively suitable and per se known educts and sources have to be employed. The respective conditions can easily be adjusted by the man skilled in the art.

A method for the production of a semiconduc-tor structure according to the invention is de-scribed in the claims 22 to 33.

Definitions.

A direct semiconductor is a semiconductor, where in the band structure the valence band maximum and the conduction band minimum are lo-cated opposite to each other at the same crystal pulse vector. In contrast thereto, for an indi-rect semiconductor, the valence band maximum and the conduction band minimum are not located op-posite to each other at the same "crystal pulse vector, but are located at different crystal pulse vectors.

A monolithic semiconductor structure is a structure, wherein an electric contact of dif-ferent functional semiconductor sections occurs by (preferably epitaxial) layers immediately connected with each other. In contrast thereto, in a hybrid semiconductor structure, an electri-cal contact of different functional semiconduc-tor sections is achieved by auxiliary connec-tions, such as for instance wire connections.

In an n-doped semiconductor, the electrical conduction is achieved by electrons because of donor atoms having extra valence electrons. For the n-doping of silicon, there can for instance be used nitrogen, phosphorus, arsenic and anti-. ' . ~

mony. For the n-doping of GaP or (AlGa) P semi-conductors, for instance silicon and tellurium can be used. In a p-doped semiconductor, the electrical conduction occurs by holes because of the incorporation of acceptor atoms. Acceptors for silicon are boron, aluminum, gallium and in-dium. For GaP or (AIGa)P can be used for in-stance magnesium, zinc or carbon as acceptors.

A semiconductor is typically undoped, if the concentration of donor or.acceptor atoms is be-low 105 cm-3. Doped semiconductors usually have concentrations above 1015 cm 3.

A current-conducting layer consists of a semiconductor doped to such an extent that a conductivity being sufficient for providing a defined electrical power is given.

III/V semiconductors according to the inven-tion are typically compressively stressed. For the purpose of the lattice adaptation and model-ing of the band structure, barrier layers are provided, which may be tensile-stressed.
Thereby, a compensation of the stress of the III/V semiconductor is achieved.

An optically active element according to the invention transforms energy into light radiation and emits the latter, modulates the light radia-tion and/or absorbs light radiation and trans-forms it into an electrical signal. For laser diodes, the number of layer periods n is typi-cally 1- 5. For luminescence diodes, n may how-r = , i ever be up to 15. For modulators or detector structures, n may be substantially higher and have values of up to 50 and more.

An adaptation layer serves for the compensa-tion of stresses of a semiconductor layer or a semiconductor structure according to the inven-tion on the basis of III/V semiconductors on Si or GaP substrates. Adaptation layers do not con-tribute to light emission.

A quantum well layer is also called a quantum film. By the two-side contact with a barrier layer, the movements of the charge carriers are confined, and the charge carriers are in the case of epitaxial layers in a one-dimensional inclusion (movements mainly' in two spatial di-mensions). Optically active elements having the layer structure according to the invention are also called multiple quantum well (MQW) struc-tures. By epitaxial stresses between the quantum well layers and the barrier layers, the elec-tronic properties with regard to the fundamental band gap can be influenced.

Optical waveguide layers are widely known from prior art. As an example only, reference is made to the document "Semiconductor Optoelec-tronics: Physics and Technology", J. Singh, McGraw-Hill Inc., New York (1995).

Periodic reflection structures are dielectric and/or epitaxial (A/4) multi-layer mirrors. They are so-called distributed Bragg reflectors (DBR), reflecting the light emitted by the opti-cally active element and representing thus the high-reflective end mirror in the laser resona-tor. With regard thereto, reference is made to the document "Vertical-cavity Surface-emitting Lasers: Design, Fabrication, Characterization and Application", Eds.: C. Wilmsen et al., Cam-bridge University Press, Cambridge (1999). Such periodic reflection structures may also be p or n-doped for the purpose of current conduction.
Then these periodic reflection structures accept at the same time the function of a current-con-ducting layer.

III/V semiconductors according to the inven-tion are typically metastable at 'room tempera-ture or at operating temperature. This means that because of the thermodynamics of the situa-tion at the respective temperature, there should not exist a stable, homogeneous phase, but that a decay into at least two different phases should occur. This decay is however kinetically =:h.. inhibited. For overcoming the kinetic inhibi-tion, a high temperature would be required to act, and for this reason such metastable phases can only be epitaxially deposited at compara-tively low substrate temperatures, typically be-low 700 C. After the deposition at reduced tem-peratures, an annealing step of the semiconduc-tor layer according to the invention may be em-ployed in the temperature range of typically 700 C to 850 C for the reduction of nonradiative recombination centers. There can be performed equilibrium annealing steps, for instance imme-diately in a MOVPE reactor, as well as non-equi-librium methods, such as rapid thermal annealing (RTA). The respective annealing temperatures are to be selected such that no decay into different phases is observed.

The carrier layer used according to the in-vention is typically a GaP or Si single crystal.
It is understood that the surface of such a sin-gle crystal may be purified in a conventional 1o manner and prepared for the epitaxial deposi-tion. In this context, reference is made to the document A. Ishizaka et al., Electrochem. Soc.
33:666 (1986).

The term "substantially 1:1" comprises the 1S range of 0.8:1.2 - 1.2:0.8, in particular 0.9:1.1 - 1.1:0.9, preferably 0.95:1.05 -1.05:0.95, and of course also exactly 1:1.

Embodiments of the invention.
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20 Example 1: Production of a semiconductor layer according to the invention.

After the usual pretreatment, a Si wafer (manufacturer: Wacker, Virginia Semiconductor) is placed in a MOVPE apparatus (type AIX200-GFR, 25 manufacturer Aixtron). First, epitaxial layers are deposited in a conventional way on the Si wafer, as described in more detail in the fol-lowing Examples. On the thus obtained surface, then a layer of the III/V semiconductor accord-ing to the invention'is deposited. For this pur-pose, an inert gas flow (H2) is loaded with the various educts. The following educts are used:
trimethylgallium or triethylgallium, trialkylin-dium (as far as applicable), 1,1-dimethylhydra-zine, tertiarybutylarsine, tertiarybutylphos-phine and trimethylantimony (as far as applica-ble). All these educts are for instance avail-able from Akzo Nobel HPMO.

For the production of a semiconductor layer according to the invention having an exemplary composition Ga(N0.037AS0.883P0.08), the following conditions were selected with a total reactor pressure of 50 hPa: partial pressures TEGa (tri-ethylgallium) 0.007 hPa, TBAs (tertiarybutylar-sine) 0.142 hPa, TBP (tertiarybutylphosphine) 0.035 hPa and UDMHy (dimethylhydrazine) 0.85 hPa. Therefrom result the following ratios: ra-tio As/Ga 20, ratio P/Ga 5 and ratio N/As 6.

.,.,.;f The loaded H2 carrier gas having a total pressure of 50 hPa is then conducted for 22 s over the surface of the coated substrate heated to 575 C. A layer according to the invention having a thickness of 7.0 nm is obtained. After expiration of the exposure period for the semi-conductor layer according to the invention, the MOVPE system is adjusted to the deposition con-ditions of the respective barrier or adaptation layer.

-, , Example 2: Production of an optically active element.

In the MOVPE apparatus of Example 1, first the layers described in the following examples are epitaxially grown on a Si wafer in a conven-tional manner. Thereafter, alternatingly a bar-rier layer and a quantum well layer each are de-posited, and the deposition of a barrier layer repre.sents the completion. This periodic layer structure comprises in total 5 quantum well lay-ers. As the quantum well layer, a layer accord-ing to Example 1 is used. All quantum well lay-ers have the same composition. As the barrier layer, GaP is used. All barrier layers have the same composition. The quantum well layers have thicknesses between 2 and 20 nm each. The bar-rier layers have thicknesses between 5 and 500 nm.

Example 3: Monolithic integrated semiconductor structure according to the inven-tion.

A monolithic integrated semiconductor struc-ture according to the invention is shown in Fig.
1. For the production, the layers B1) to F2) are subsequently epitaxially grown on a Si wafer A.
The layer B1) is p-doped GaP. Zinc or magnesium is used as doping element. The doping concentra-tion is typically 1=1018 cm-3. The layer thick-ness of the layer Bl) is 5 300 nm. The layer B1) is a contact layer, which is also current conducting. Thereafter, the layer B2) is pro-duced, which is formed of p-doped (AlGa) P. Dop-ing is made with zinc or magnesium in a doping concentration of typically 1=1018 cm 3. The alu-minum concentration is more than 15 mole-%, re-ferred to the total amount of group III ele-ments. A typical value is in the range of 15 -45 mole-%. Alternatively, p-doped (AlGa)(NP) can also be used, and with regard to doping and alu-minum content the above applies. The share of nitrogen referred to the total amount of group V
elements, is 0 - 4 mole-%. The layer thickness is between 500 and 1, 500 nm. The layer B2) is a waveguide layer, which acts at the same time as a current-conducting layer. The layer C) dis-posed thereupon is composed of undoped GaP. The layer thickness is 50 - 100 nm. It is a separate confinement heterostructure similar to a barrier layer. Further, the layer C) acts as an adapta-tion layer. For better vis'ibility, the optically active element D) disposed thereupon is shown as a single layer. In fact, the layer D) is a layer structure according to Example 2. The layer E) corresponds to the layer C). Alternatively, both layers can also be adapted as Ga(NP), (GaIn)(NP) or (GaIn)(NaSP) layers. The nitrogen share re-ferred to the group V elements may be 0 - 10 mole-%. In the case of the latter layer, the share of In referred to the total amount of group III elements may be 0 - 15 mole-%. The layer Fl) corresponds to the layer B2), and the layer F2) corresponds to the layer Bl), with the difference that the layers Fl) and F2) are n-doped. As the doping element, tellurium with a doping concentration of typically 2= 1018 cm-3 is employed. The layer thicknesses of the layers E), Fl) and F2) correspond to the layer thick-nesses of the layers C), B2) and B1) (in a re-flection-symmetric order with regard to the op-tically active element).

For improving the degree of output coupling, for luminescence diodes as optically active ele-ments, in addition (AlGa)/P/(AlGa)/P periodic reflection structures (DBR structures) having different aluminum contents can be incorporated in the current-conducting layer located under the optically active element. The aluminum share of successive layers is different, and is, re-ferred to the total amount- of group III ele-ments, 0 - 60 mole-% or 40 - 100 mole-%, resp.
Alternatively, (A1Ga)(NP) individual layers may also be used for the compensation of stress of these DBR structures, and the Al contents are to be selected as above, and the N contents from 0 - 4 mole-%, referred to the total amount of group V elements.

For surface emitting laser diodes (VCSEL) as optically active elements, the optically active element is enclosed from below as well as from above by a reflection structure of the above type. For current supply, either- these two DBR
mirror structures may be n-doped or p-doped, or additionally so-called intra cavity current con-tacts are introduced in the overall structure, said contacts permitting to produce the two DBR
mirrors in an undoped condition.

Example 4: Fundamental energy gap of a semicon-ductor according to the invention.

A semiconductor layer produced according to Example 1 with 4 mole-% nitrogen, 90 mole-% ar-senic and 6 mole-% phosphorus, referred to the total amount of group V elements, was investi-gated by means of the photoluminescence excita-tion spectroscopy. The result is shown in Fig.
2. The fundamental energy gap is approx. 1.4 eV.
This value is clearly lower than, the value of 1.8 eV modeled without the nitrogen interaction and shows the drastic influence of the energy gap by the incorporation of nitrogen in coordi-nation with the further shares of other compo-nents in the semiconductor system according to the invention.
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vu Example 5: Dislocation-free structure of opti-cally active elements according to the invention.

An optically active element produced accord-ing to Example 2 was investigated by means of the high-resolution x-ray diffraction (HR-XRD) and of the transmission electron microscopy (TEM).

r ~

Fig. 3 shows an experimental HR-XRD profile (Fig. 3 top) in comparison with a theoretical profile according to the dynamic x-ray diffrac-tion theory (Fig. 3 bottom). The observed sharp-ness of the individual diffraction reflexes and the nearly perfect match of the experimental and theoretical diffraction profiles confirm the outstanding structural layer quality over a large area without generation of dislocations.

Fig. 4 shows a TEM dark field image. There can be seen pentanary layers according to the invention as dark layers. The lighter layers are Ga(NP) barrier layers. All three layers are clearly resolved, and there cannot be seen any large-area defects in the crystalline structure.
In the high-resolution TEM- image of Fig. 5, there are nearly atomically abrupt border faces at the transition of the (dark) pentanary layer according to the invention to the barrier layer, said border faces being free from dislocations and the like.

Example 6: Semiconductors with a particularly low fundamental energy gap.

Different semiconductor layers produced anal-ogously to Example, said layers however contain-ing nitrogen in the range of 5.5 to 11 mole-%
(as always, referred to the total amount of group V elements), show in the investigation by means of photoluminescence spectroscopy at 20 C

w - 26 -a fundamental, direct energy gap of less than 1.2 eV, even less than 1.1 eV, which is below the energy gap of silicon (1.124 eV) . Semicon-ductor layers having an energy gap below that of silicon in particular for the production of lu-minescence and laser diodes, which are inte-grated with Si/Si02-based waveguide structures.
In particular for these emission energies, there will namely be no absorption and thus attenua-tion of the light signal in the waveguide struc-ture.

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Claims

1. A monolithic integrated semiconductor structure comprising the following layer struc-ture:
A) a carrier layer on the basis of doped or undoped Si or GaP, B) as an option, a first current-conducting layer composed of doped Si, doped GaP or doped (AlGa)P, C) as an option, a first adaptation layer, and D) an optically active element comprising a semiconductor layer formed from a III/V semicon-ductor having the composition Ga x In y N a As b P c Sb d, wherein x = 70 - 100 mole-%, y = 0 - 30 mole-%, a = 0.5 - 15 mole-%, b = 67.5 - 99.5 mole-%, c =
0 - 39.5 mole-% and d = 0 - 15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ratio of the totals of x and y on the one hand and of a to d on the other hand is substantially 1:1.

2. A semiconductor structure according to claim 1, comprising the below layer structure following to the layer D):
E)optionally a second adaptation layer, and F) a second current-conducting layer composed of doped Si, doped GaP or doped (AlGa)P.

3. A semiconductor structure according to claim 1 or 2, wherein the layer B) is p-doped or n-doped.

4. A semiconductor structure according to one of claims 1 to 3, wherein y = 1 to 30 mole-%.

5. A semiconductor structure according to one of claims 1 to 4, wherein c = 1 to 32.0 mole-%.

6. A semiconductor structure according to one of claims 1 to 5, wherein the semiconductor is a direct semiconductor.

7. A semiconductor structure according to one of claims 2 to 6, wherein the layer F) is p-doped, if the layer B) is n-doped, and wherein the layer F) is n-doped, if the layer B) is p-doped.

8. A semiconductor structure according to one of claims 1 to 7, wherein the optically ac-tive element has a layer structure (D1-D2-D3)n, wherein the layer D2 is a quantum well layer of the said semiconductor, wherein the layers D1 and D3 are barrier layers, and wherein n = 1-50, in particular 1 - 15.

9. A semiconductor structure according to claim 8, wherein following one of the terminal layers D1 or D3, a barrier layer D4 is provided.

10. A semiconductor structure according to claim 8 or 9, wherein the barrier layers are semiconductors having the composition Ga p In q N r-P s As t, wherein p = 85 - 100 mole-%, q = 0 - 15 mole-%, r = 0 - 15 mole-%, s = 60 - 100 mole-%
and t = 0 - 40 mole-%, wherein the total of p and q is always 100 mole-%, wherein the total of r, s and t is always 100 mole-%, wherein the ra-tio of the totals of p and q on the one hand and of r to t on the other hand is substantially 1:1, and wherein the barrier layer has a layer thickness of preferably 5 - 50 nm

11. A semiconductor structure according to one of claims 1 to 10, wherein the first and/or the second adaptation layers are semiconductors having the composition Ga p In q N r P s As t, wherein p = 90 - 100 mole-%, q= 0 - 10 mole-%, r = 0 - 10 mole-%, s = 70 - 100 mole-% and t = 0 - 30 mole-%, wherein the total of p and q is always 100 mole-%, wherein the total of r, s and t is al-ways 100 mole-%, and wherein the ratio of the totals of p and q on the one hand and of r to t on the other hand is substantially 1:1, and wherein the adaptation layer has a layer thick-ness of preferably 50 - 500 nm.

12. A semiconductor structure according to one of claims 1 to 11, wherein a current-con-ducting layer and/or barrier layer disposed be-tween the carrier layer and the optically active element is at the same time an adaptation layer.

13. A semiconductor structure according to one of claims 1 to 12, wherein underneath and/or above the optically active element, at least one optical waveguide layer is provided, which is optically coupled to the optically active ele-ment.

14. A semiconductor structure according to one of claims 1 to 13, wherein between the lay-ers A) and D) and/or outside the layer F), there is provided at least one periodic reflection structure.

15. A semiconductor structure according to one of claims 1 to 14, wherein the optically ac-tive element has a fundamental emission wave-length in the range of 700 - 1,100 nm.

16. A method for the production of a mono-lithic integrated semiconductor structure ac-cording to one of claims 8 to 15, wherein on a carrier layer A on the basis of doped or undoped Si or GaP, optionally a first current-conducting layer B
consisting of doped Si, doped GaP or doped (AlGa)P is epitaxially grown, optionally a first adaptation layer C is epi-taxially grown, and a multi-layer structure D, which forms an op-tically active element including a semiconductor layer comprising a semiconductor according to one of claims 1 to 6, is epitaxially grown.

17. A method according to claim 16, wherein on the optically active element optionally a second adaptation layer E is epitaxially grown, and on the optically active element or the sec-ond adaptation layer a second current-conducting layer F consisting of doped-Si or doped GaP or doped (AlGa)P is epitaxially grown.

18. A method according to claim 16 or 17, wherein the layer B is p-doped or n-doped.

19. A method according to claim 18, wherein the layer F) is p-doped, if the layer B) is n-doped, and wherein the layer F) is n-doped, if the layer B) is p-doped.

20. A method according to one of claims 16 to 19, wherein the optical element is formed by epitaxial growth of layers D1, D2 and D3, wherein the order of the epitaxial steps is per-formed such that the layer structure is (D1-D2-D3)n, wherein the layer D2 is a quantum well layer of a semiconductor according to one of claims 1 to 4, wherein the layers D1 and D3 are barrier layer.s, and wherein n = 1 - 50, in par-ticular 1 - 15.

21. A method according to claim 20, wherein following one of the terminal layers D1 or D3, a barrier layer D4 is epitaxially grown.

22. A method according to claim 20 or 21, wherein the barrier layers are semiconductors having the composition Ga p In q N r P s As t, wherein p = 85 - 100 mole-%, q = 0 - 15 mole-%, r = 0 - 15 mole-%, s = 60 - 100 mole-% and t = 0 - 40 mole-%, wherein the total of p and q is always 100 mole-%, wherein the total of r, s and t is al-ways 100 mole-%, wherein the ratio of the totals of p and q on the one hand and of r to t on the other hand is substantially 1:1, and wherein the barrier layer has a layer thickness of prefera-bly 5 - 50 nm.

23. A method according to one of claims 16 to 22, wherein the first and/or second adaptation layers are semiconductors having the composition Ga p In q N r P s As t, wherein p = 90 - 100 mole-%, q =
0 - 10 mole-%, r = 0 - 10 mole-%, s = 70 - 100 mole-% and t = 0 30 mole-%, wherein the total of p and q is always 100 mole-%, wherein the to-tal of r, s and t is always 100 mole-%, wherein the ratio of the totals of p and q on the one hand and of r to t on the other hand is substan-tially 1:1, and wherein the adaptation layer has a layer thickness of preferably 50 - 500 nm.

24. A method according to one of claims 16 to 23, wherein a current-conducting layer and/or barrier layer disposed between the carrier layer and the optically active element is at the same time an adaptation layer.

25. A method according to one of claims 16 to 24, wherein underneath and/or above the opti-cally active element, at least one optical waveguide layer is provided, which is optically coupled to the optically active element.

26. A method according to one of claims 16 to 25, wherein between the layers A) and D) and/or outside the layer F), there is provided at least one periodic reflection structure.

27. A method according to one of claims 16 to 26, wherein the optically active element has a fundamental emission wavelength in the range of 700 - 1,100 nm.

28. A III/V semiconductor having the composi-tion Ga x In y N a As b P c Sb d, wherein x = 70 - 100 mole-%, y = 0 - 30 mole-%, a = 0.5 - 15 mole-%, b =
67.5 - 99.5 mole-%, c = 0 39.5 mole-% and d =
0 - 15 mole-%, wherein the total of x and y is always 100 mole-%, wherein the total of a, b, c and d is always 100 mole-%, and wherein the ra-tio of the totals of x and y on the one hand and of a to d on the other hand is substantially 1:1.

29. A III/V semiconductor according to claim 28, wherein y = 1 to 30 mole-%.

30. A III/V semiconductor according to claim 28 or 29, wherein c = 1 - 32.0 mole-%.

31. A III/V semiconductor according to one of claims 28 to 30, wherein the semiconductor is a direct semiconductor.

32. A semiconductor layer comprising a semi-conductor according to one of claims 28 to 31, wherein the layer thickness of the semiconductor layer is in the range from 1 - 50 nm, preferably 2 - 20 nm.

33. The use of a semiconductor according to one of claims 28 to 31 or of a semiconductor layer according to claim 32 for the production of a luminescence diode, a VCSEL laser diode, a VECSEL laser diode, a modulator structure or a detector structure.

34. A method for the production of a semicon-ductor layer according to claim 33 comprising the following steps:
a substrate on the basis of doped or undoped Si or GaP is brought into a MOVPE apparatus, optionally a surface of the substrate is pro-vided in at least one epitaxial coating step first with respectively at least one adaptation layer, one barrier layer, one current-conducting layer, one waveguide layer and/or one reflection structure, an inert carrier gas is loaded with educts in defined concentrations, the loaded carrier gas is conducted over the surface of the substrate heated to a temperature in the range of 300°C to 700°C or on the surface of the uppermost layer on the substrate for a defined duration of exposure, and the total con-centration of the educts and the duration of ex-posure are adjusted to each other such that the semiconductor layer is epitaxially formed with a given layer thickness on the surface of the sub-strate or on the surface of the uppermost layer on the substrate.

35. A method according to claim 34, wherein the following educts are used:

C1-C5 trialkylgallium, in particular tri-ethylgallium (Ga(C2H5)3) and/or trimethylgallium (Ga(CH3)3), as a Ga educt, optionally C1-C5 trialkylindium, in particular trimethylindium (In(CH3)3), as an In educt, ammonia (NH3), mono(C1-C8)alkylhydrazine, in particular tertiarybutylhydrazine (t-(C4H9)-NH-NH2), and/or 1,1-di(C1-C5)alkylhydrazine, in particular 1,1-dimethylhydrazine ((CH3)2-N-NH2), as an N educt, arsine (AsH3) and/or C1-C5 alkylarsine, in particular tertiarybutylarsine (t-(C4H9)-AsH2), as an As educt, phosphine (PH3) and/or C1-C5 alkylphosphine, in particular tertiarybutylphosphine (t-(C4H9)-PH2), as a P educt, and optionally C1-C5 trialkylantimony, in par-ticular trimethylantimony (Sb(C2H5)3) and/or tri-ethylantimony (Sb(CH3)3), as an Sb educt, wherein the C3-C5 alkyl groups may be linear or branched.

36. A method according to claim 35, wherein the educts are employed in the following molar ra-tios:
As educt/group III educts 5 - 300, P educt/group-III educts 0 - 500, N educt/As educt 0.1 - 10, optionally Sb educt/As educt 0 - 1, wherein the surface temperature of the sub-strate is adjusted to the range from 500°C to 630°C, wherein the total pressure of carrier gas and educts is adjusted to the range from 10 to 200 hPa, wherein the ratio of the total of the partial pressures of the educts to the partial pressure of the carrier gas is between 0.005 and 0.1, and wherein the deposition rate is 0.1 to µm/h.

37. A semiconductor layer obtainable with a method according to one of claims 34 to 36.

38. An integrated monolithic semiconductor structure obtainable with a method according to one of claims 16 to 26.