CA2448978A1 - Cell-based switch fabric architecture - Google Patents
Cell-based switch fabric architecture Download PDFInfo
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- CA2448978A1 CA2448978A1 CA002448978A CA2448978A CA2448978A1 CA 2448978 A1 CA2448978 A1 CA 2448978A1 CA 002448978 A CA002448978 A CA 002448978A CA 2448978 A CA2448978 A CA 2448978A CA 2448978 A1 CA2448978 A1 CA 2448978A1
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- switch fabric
- data packet
- cell
- data
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/15—Interconnection of switching modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3036—Shared queuing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/45—Arrangements for providing or supporting expansion
Abstract
A switch fabric implemented on a chip includes an array of cells and an I/O
interface in communication with the cells for permitting exchange of data packet between the cells and components external thereto. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the packet and forward it to at least one cell of the array selected on a basis of the determined destination. Each cell further includes plural receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets thereto. In this way, the transmitter in a given cell functionally extends into those cells where dedicated receivers are located, reducing transmitter memory requirements and allowing the switch fabric to be implemented on a single chip.
interface in communication with the cells for permitting exchange of data packet between the cells and components external thereto. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the packet and forward it to at least one cell of the array selected on a basis of the determined destination. Each cell further includes plural receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets thereto. In this way, the transmitter in a given cell functionally extends into those cells where dedicated receivers are located, reducing transmitter memory requirements and allowing the switch fabric to be implemented on a single chip.
Claims (192)
1) A switch fabric implemented on a chip, comprising:
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell including:
I) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
II) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver; ~
III) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell including:
I) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
II) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver; ~
III) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
2) A switch fabric as defined in claim 1, wherein said array of cells includes a plurality of data channels, each data channel being associated with a given cell, the data channel associated with said given cell connecting the transmitter of said given cell to receivers in cells other than said given cell and associated with said given cell.
3) A switch fabric as defined in claim 2, wherein the data channel associated with said given cell connects the transmitter of said given cell to a receiver in every cell of said array and associated with said given cell.
4) A switch fabric as defined in claim 3, wherein the plurality of data channels are independent from one another, wherein transmission of a data packet over one data channel is made independently of a transmission of a data packet over another data channel.
5) A switch fabric as defined in claim 4, wherein each data channel performs a parallel data transfer.
6) A switch fabric as defined in claim 2, wherein said array of cells forms a matrix.
7) A switch fabric as defined in claim 6, wherein said matrix is bi-dimensional.
8) A switch fabric as defined in claim 7, wherein said matrix is three-dimensional.
9) A switch fabric as defined in claim 2, wherein said array of cells forms a toroidal mesh arrangement.
10)A switch fabric as defined in claim 2, wherein the transmitter of said given cell includes a memory for storing data packets received from said I/O interface.
11)A switch fabric as defined in claim 10, wherein said memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array to which the transmitter of said given cell is capable of forwarding a data packet via the data channel associated with said given cell.
12)A switch fabric as defined in claim 11, wherein the transmitter of said given cell includes a control entity that processes a data packet forwarded from said I/O
interface to determine a cell of said array to which the packet is destined and identify on a basis of the determined cell a segment of said memory into which the packet is to be loaded.
interface to determine a cell of said array to which the packet is destined and identify on a basis of the determined cell a segment of said memory into which the packet is to be loaded.
13)A switch fabric as defined in claim 12, wherein said control entity includes a plurality of queue controllers associated with respective segments of said memory.
14)A switch fabric as defined in claim 13, wherein said memory implements a plurality of registers, each register being associated with a queue controller and being suitable for holding data representative of a degree of occupancy of a segment of said memory associated with the queue controller.
15)A switch fabric as defined in claim 14, wherein a data packet received by said transmitter from said I/O interface is characterized by a priority level selected from a group of priority levels, each segment of said memory being partitioned into slots, each slot being capable of storing at least one data packet, each slot being associated with a given priority level of said group of priority levels.
16)A switch fabric as defined in claim 15, wherein the registers of said memory associated with each queue controller store data indicative of a degree of occupancy of the slots of said segment associated with the queue controller, for each priority level of the group of priority levels.
17)A switch fabric as defined in claim 12, wherein the transmitter of said given cell communicates with each receiver associated with said given cell to assess a degree of occupancy of each receiver associated with said given cell.
18)A switch fabric as defined in claim 17, wherein the transmitter of said given cell communicates with each receiver associated with said given cell to assess the degree of occupancy of each receiver associated with said given cell over a back channel.
19)A switch fabric as defined in claim 18, including a plurality of back channels, there being a dedicated back channel between the transmitter of said given cell and each receiver associated with said given cell.
20)A switch fabric as defined in claim 19, wherein each back channel transfers data serially.
21)A switch fabric as defined in claim 18, wherein said memory includes an area for storing data indicative of the degree of occupancy of each receiver associated with said given cell.
22)A switch fabric as defined in claim 21, wherein said control entity is operative to process the data indicative of the degree of occupancy of each receiver associated with said given cell to determine which data packet stored in said memory is suitable for transmission to a receiver.
23)A switch fabric as defined in claim 22, wherein said control entity determines that a data packet is suitable for transmission to a certain receiver when the data indicative of the degree of occupancy of the certain receiver indicates that the receiver is capable of accepting the data packet.
24)A switch fabric as defined in claim 23, wherein when said control entity determines that a data packet is suitable for transmission, said control entity generates a control signal to request transmission of the data packet.
25)A switch fabric as defined in claim 24, wherein when said control entity determines that a plurality of data packets are suitable for transmission, said control entity generates a plurality of control signals to request transmission of the data packets, each control signal being associated with a data packet.
26)A switch fabric as defined in claim 25, wherein said control entity includes an arbiter for processing said control signals to select a data packet to transmit among the plurality of data packets suitable for transmission.
27)A switch fabric as defined in claim 26, wherein a data packet is characterized by a priority level, wherein each control signal conveys the priority level of the data packet associated with the control signal.
28)A switch fabric as defined in claim 27, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission on a basis of the priority levels of the plurality of data packets suitable for transmission.
29)A switch fabric as defined in claim 28 wherein said arbiter processes control signals to request transmission of data packets in a round robin manner.
30)A switch fabric as defined in claim 29, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission on a basis of the priority levels of the plurality of data packets suitable for transmission and on the basis of whether or not a data packet was previously submitted for transmission.
31)A switch fabric as defined in claim 10, wherein said memory is a first memory, said cell comprising a second memory including a plurality of sectors associated with respective receivers of said plurality of receivers, said sectors being capable of storing data packets forwarded to said receivers by cells of said array.
32)A switch fabric as defined in claim 31, wherein each receiver of said plurality of receivers communicates with said I/O interface.
33)A switch fabric as defined in claim 31, wherein said plurality of receivers includes a control entity to regulate a release of data packets from said sectors to said I/O interface.
34)A switch fabric as defined in claim 33, wherein said control entity includes a plurality of queue controllers associated with respective sectors of said memory.
35)A switch fabric as defined in claim 34, wherein a data packet received by a receiver of said plurality of receivers is characterized by a priority level selected from a group of priority levels, each sector of said second memory being divided into subdivisions, each subdivision being capable of storing at least one data packet, each subdivision being associated with a given priority level of said group of priority levels.
36)A switch fabric as defined in claim 35, wherein said control entity includes an arbiter in communication with said queue controllers, each queue controller being operative to transmit a control signal to said arbiter for each data packet held in the sector associated with the queue controller to request release of the data packet to said I/O interface.
37)A switch fabric as defined in claim 36, wherein each control signal conveys,the priority level of the data packet associated with the control signal.
38)A switch fabric as defined in claim 37, wherein said arbiter selects a data packet for release to said I/O interface among the data packets corresponding to the control signals transmitted to said arbiter on the basis of the levels of priority of the data packets corresponding to the control signals transmitted to said arbiter.
39)A switch fabric as defined in claim 1, wherein each data packet comprises a plurality of words including a first word of said data packet and a last word of said data packet, wherein each word comprises a field indicative of whether said word is a pre-determined number of words away from said last word of said data packet.
40)A switch fabric as defined in claim 39, wherein the transmitter is operative to monitor said field in each word of each data packet forwarded to at least one cell of said array, the transmitter further being operative to begin forwarding a next data packet upon detecting that said field of a word in a packet currently being forwarded is indicative of said word being a pre-determined number of words away from the last word of said data packet currently being forwarded.
41)A switch fabric as defined in claim 1, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination.
42)A switch fabric as defined in claim 2, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination, wherein data packets received by the transmitter in a given cell from the I/O
interface and from the CPU in said given cell share the data channel associated with said given cell.
interface and from the CPU in said given cell share the data channel associated with said given cell.
43)A switch fabric as defined in claim 1, each cell further including a central processing unit (CPU) connected to the plurality of receivers, said receivers being further operative to determine whether data packets are to be released to the I/O interface or to the CPU and release said data packets accordingly.
44)A switch fabric as claimed in claim 43, wherein each data packet comprises a field indicative of whether the data packet is destined for a CPU and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
45)A switch fabric as defined in claim 25, each cell further including a central processing unit (CPU) connected to the plurality of receivers, wherein said control entity includes a first arbiter for processing said control signals to select a data packet to transmit to the I/O interface among the plurality of data packets suitable for transmission to the I/O interface, wherein said control entity includes a second arbiter for processing said control signals to select a data packet to transmit to the CPU among the plurality of data packets suitable for transmission to the CPU.
46)A switch fabric as defined in claim 1, wherein the transmitter of said given cell includes a memory for storing data packets received from said I/O interface.
47)A switch fabric as defined in claim 46, wherein said memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array in which the transmitter of said given cell is capable of forwarding a data packet via the data channel associated with said given cell.
48)A switch fabric implemented on a chip, comprising:
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for receiving a data packet from another cell of said array;
II) a control entity to control release of a data packet toward a selected destination cell of said array at least in part on a basis of a degree of occupancy of the memory in said destination cell.
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for receiving a data packet from another cell of said array;
II) a control entity to control release of a data packet toward a selected destination cell of said array at least in part on a basis of a degree of occupancy of the memory in said destination cell.
49)A switch fabric as defined in claim 48, wherein each cell of said array includes:
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
50)A switch fabric as defined in claim 49, wherein said array of cells includes a plurality of data channels, each data channel being associated with a given cell, the data channel associated with said given cell connecting the transmitter of said given cell to receivers in cells other than said given cell and associated with said given cell.
51)A switch fabric as defined in claim 49, wherein said array of cells includes a plurality of data channels, each data channel being associated with a given cell, the data channel associated with said given cell connecting the transmitter of said given cell to a receiver in every cell of said array of cells and associated with said given cell.
52)A switch fabric as defined in claim 51, wherein the plurality of data channels are independent from one another, wherein transmission of a data packet over one data channel is made independently of a transmission of a data packet over another data channel.
53)A switch fabric as defined in claim 52, wherein each data channel performs a parallel data transfer.
54)A switch fabric as defined in claim 48, wherein said array of cells forms a matrix.
55)A switch fabric as defined in claim 54, wherein said matrix is bi-dimensional.
56)A switch fabric as defined in claim 54, wherein said matrix is three-dimensional.
57)A switch fabric as defined in claim 48, wherein said array of cells forms a toroidal mesh arrangement.
58)A switch fabric as defined in claim 49, wherein said memory is a first memory and wherein the transmitter of said given cell includes a second memory for storing data packets received from said I/O interface.
59)A switch fabric as defined in claim 58, wherein said second memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array to which the transmitter of said given cell is capable of forwarding a data packet via the data channel.
60)A switch fabric as defined in claim 59, wherein the transmitter of said given cell includes said control entity, said control entity being operative to process a data packet forwarded from said I/O interface to determine a cell of said array to which the data packet is destined and identify on a basis of the determined cell a segment of said second memory into which the packet is to be loaded.
61)A switch fabric as defined in claim 60, wherein said control entity includes a plurality of queue controllers associated with respective segments of said second memory.
62)A switch fabric as defined in claim 61, wherein said second memory implements a plurality of registers, each register being associated with a queue controller and being suitable for holding data representative of a degree of occupancy of a segment of said second memory associated with the queue controller.
63)A switch fabric as defined in claim 62, wherein a data packet received by said transmitter from said I/O interface is characterized by a priority level selected in a group of priority levels, each segment of said second memory being partitioned into slots, each slot capable of storing at least one data packet, each slot being associated with a given priority level of said group of priority levels.
64)A switch fabric as defined in claim 63, wherein the registers of said second memory associated with each queue controller store data indicative of a degree of occupancy of the slots of said segment associated with the queue controller, for each priority level of the group of priority levels.
65)A switch fabric as defined in claim 60, wherein said first memory is divided into a plurality of sectors associated with respective ones of said receivers, said sectors capable of storing data packets forwarded to said receivers by cells of said array, said control entity being operative to communicate with each receiver associated with said given cell to assess a degree of occupancy of the sector of each receiver associated with said given cell.
66)A switch fabric as defined in claim 65, wherein said control entity communicates with each receiver associated with said given cell to assess the degree of occupancy of the sector of each receiver associated with said given cell, over a back channel.
67)A switch fabric as defined in claim 66, including a plurality of back channels, there being a dedicated back channel between said control entity and each receiver associated with said given cell.
68)A switch fabric as defined in claim 67, wherein each back channel transfers data serially.
69)A switch fabric as defined in claim 66, wherein said second memory includes an area for storing data indicative of the degree of occupancy of the sector of each receiver associated with said given cell.
70)A switch fabric as defined in claim 69, wherein said control entity is operative to process the data indicative of the degree of occupancy of the sector of each receiver associated with said given cell to determine which data packet stored in said second memory is suitable for transmission to a receiver.
71)A switch fabric as defined in claim 70, wherein when said control entity determines that a data packet is suitable for transmission, said control entity generates a control signal to request transmission of the data packet.
72)A switch fabric as defined in claim 71, wherein when said control entity determines that a plurality of data packets are suitable for transmission, said control entity generates a plurality of control signals to request transmission of the data packets, each control signal being associated with a data packet.
73)A switch fabric as defined in claim 72, wherein said control entity includes an arbiter for processing said control signals to select a data packet to transmit among the plurality of data packets suitable for transmission.
74)A switch fabric as defined in claim 73, wherein a data packet is characterized by a priority level, wherein each control signal conveys the priority level of the data packet associated with the control signal.
75)A switch fabric as defined in claim 74, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission on a basis of the priority levels of the plurality of data packets suitable for transmission.
76)A switch fabric as defined in claim 75, wherein said arbiter processes control signals to request transmission of data packets in a round robin manner.
77)A switch fabric as defined in claim 76, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission on a basis of the priority levels of the plurality of data packets suitable for transmission and on the basis of whether or not a data packet was previously submitted for transmission.
78)A switch fabric as defined in claim 65, wherein each receiver of said plurality of receivers communicates with said I/O interface.
79)A switch fabric as defined in claim 78, wherein said control entity is a first control entity and wherein said plurality of receivers include a second control entity to regulate a release of data packets from said sectors to said I/O
interface.
interface.
80)A switch fabric as defined in claim 79, wherein said second control entity includes a plurality of queue controllers associated with respective sectors of said first memory.
81)A switch fabric as defined in claim 80, wherein a data packet received by a receiver of said plurality of receivers is characterized by a priority level selected in a group of priority levels, each sector of said second memory being divided into subdivisions, each subdivision capable of storing at least one data packet, each subdivision being associated with a given priority level of said group of priority levels.
82)A switch fabric as defined in claim 81, wherein said second control entity includes an arbiter in communication with said queue controllers, each queue controller operative to transmit a control signal to said arbiter for each data packet held in the sector associated with the queue control to request release of the data packet to said I/O interface.
83)A switch fabric as defined in claim 82, wherein each control signal conveys the priority level of the data packet associated with the control signal.
84)A switch fabric as defined in claim 83, wherein said arbiter selects a data packet for release to said I/O interface among the data packets corresponding to the control signals transmitted to said arbiter on the basis of the levels of priority of the data packets corresponding to the control signals transmitted to said arbiter.
85)A switch fabric as defined in claim 49, wherein each data packet comprises a plurality of words including a first word of said data packet and a last word of said data packet, wherein each word comprises a field indicative of whether said word is a pre-determined number of words away from said last word of said data packet.
86)A switch fabric as defined in claim 85, wherein the transmitter is operative to monitor said field in each word of each data packet forwarded to at least one cell of said array, the transmitter further being operative to begin forwarding a next data packet upon detecting that said field of a word in a packet currently being forwarded is indicative of said word being a pre-determined number of words away from the last word of said data packet currently being forwarded.
87)A switch fabric as defined in claim 49, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination.
88)A switch fabric as defined in claim 50, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination, wherein data packets received by the transmitter in a given cell from the I/O
interface and from the CPU in said given cell share the data channel associated with said given cell.
interface and from the CPU in said given cell share the data channel associated with said given cell.
89)A switch fabric as defined in claim 49, each cell further including a central processing unit (CPU) connected to the plurality of receivers, said receivers being further operative to determine whether data packets are to be released to the I/O interface or to the CPU and release said data packets accordingly.
90)A switch fabric as claimed in claim 89, wherein each data packet comprises a field indicative of whether the data packet is destined for a CPU, and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
91)A switch fabric as defined in claim 72, each cell further including a central processing unit (CPU) connected to the plurality of receivers, wherein said control entity includes a first arbiter for processing said control signals to select a data packet to transmit to the I/O interface among the plurality of data packets suitable for transmission to the I/O interface, wherein said control entity includes a second arbiter for processing said control signals to select a data packet to transmit to the CPU among the plurality of data packets suitable for transmission to the CPU.
92)A switch fabric implemented on a chip comprising:
a) an array of cells; and b) an I/O interface in communication with said array of cells permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for holding a plurality of data packets for transmission to other cells of said array, each data packet of the plurality of data packets having a characteristic element represented by a parameter, the parameter allowing to distinguish one data packet from another data packet in the plurality of data packets; and II) a control entity operative to:
(i) select at least one data packet from the plurality of data packets at least in part on a basis of the parameter; and (ii) transmit the selected data packet to another cell of said array of cells.
a) an array of cells; and b) an I/O interface in communication with said array of cells permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for holding a plurality of data packets for transmission to other cells of said array, each data packet of the plurality of data packets having a characteristic element represented by a parameter, the parameter allowing to distinguish one data packet from another data packet in the plurality of data packets; and II) a control entity operative to:
(i) select at least one data packet from the plurality of data packets at least in part on a basis of the parameter; and (ii) transmit the selected data packet to another cell of said array of cells.
93)A switch fabric as defined in claim 92, wherein the parameter is priority, the characteristic element being a priority level.
94)A switch fabric as defined in claim 93, wherein each cell of said array includes:
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells from said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
95)A switch fabric as defined in claim 94, wherein said array of cells includes a plurality of data channels, each data channel being associated with a given cell, the data channel associated with said given cell connecting the transmitter of said given cell to receivers in cells other than said given cell and associated with said given cell.
96)A switch fabric as defined in claim 94, wherein the data channel associated with said given cell connects the transmitter of said given cell to a receiver in every cell of said array of cells and associated with said given cell.
97)A switch fabric as defined in claim 96, wherein the plurality of data channels are independent from one another, wherein transmission of a data packet over one data channel is made independently of a transmission of a data packet over another data channel.
98)A switch fabric as defined in claim 97, wherein each data channel performs a parallel data transfer.
99)A switch fabric as defined in claim 98, wherein said memory and said control entity form part of said transmitter.
100) A switch fabric as defined in claim 99, wherein said memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array to which the transmitter of said given cell is capable of forwarding a data packet via the data channel.
101) A switch fabric as defined in claim 100, wherein said control entity is operative to process a data packet forwarded from said I/O interface to determine a cell of said array to which the data packet is destined and identify on a basis of the determined cell a segment of said memory into which the packet is to be loaded.
102) A switch fabric as defined in claim 101, wherein said control entity includes a plurality of queue controllers associated with respective segments of said memory.
103) A switch fabric as defined in claim 102, wherein said memory implements a plurality of registers, each register being associated with a queue controller and being suitable for holding data representative of a degree of occupancy of a segment of said memory associated with the queue controller.
104) A switch fabric as defined in claim 103, wherein each segment of said memory is partitioned in slots, each slot capable of storing at least one data packet, each slot being associated with a given priority level of said group of priority levels.
105) A switch fabric as defined in claim 104, wherein the registers of said memory associated with each queue controller store data indicative of a degree of occupancy of the slots of said segment associated with the queue controller, for each priority level of the group of priority levels.
106) A switch fabric as defined in claim 105, wherein the transmitter of said given cell communicates with each receiver associated with said given cell to assess a degree of occupancy of each receiver associated with said given cell.
107) A switch fabric as defined in claim 106, wherein the transmitter of said given cell communicates with each receiver associated with said given cell to assess the degree of occupancy of each receiver associated with said given cell over a back channel.
108) A switch fabric as defined in claim 107, including a plurality of back channels, there being a dedicated back channel between the transmitter of said given cell and each receiver associated with said given cell.
109) A switch fabric as defined in claim 108, wherein each back channel transfers data serially.
110) A switch fabric as defined in claim 109, wherein said memory .includes an area for storing data indicative of the degree of occupancy of each receiver associated with said given cell.
111) A switch fabric as defined in claim 110, wherein said control entity is operative to process the data indicative of the degree of occupancy of each receiver associated with said given cell to determine which data packet stored in said memory is suitable for transmission to a receiver.
112) A switch fabric as defined in claim 111, wherein said control entity determines that a data packet is suitable for transmission to a certain receiver when the data indicative of the degree of occupancy of the certain receiver indicates that the receiver is capable of accepting the data packet.
113) A switch fabric as defined in claim 112, wherein when said control entity determines that a group of data packets are suitable for transmission, said control entity generates a plurality of control signals to request transmission of the data packets, each control signal being associated with a data packet.
114) A switch fabric as defined in claim 113, wherein said control entity includes an arbiter for processing said control signals to select a data packet to transmit among the group of data packets suitable for transmission.
115) A switch fabric as defined in claim 114, wherein each control signal conveys the priority level of the data packet associated with the control signal.
116) A switch fabric as defined in claim 115, wherein said arbiter selects a data packet to transmit among the group of data packets suitable for transmission on a basis of the priority levels of the group of data packets suitable for transmission.
117) A switch fabric as defined in claim 116, wherein said arbiter processes control signals to request transmission of data packets in a round robin manner.
118) A switch fabric as defined in claim 117, wherein said arbiter selects a data packet to transmit among the group of data packets suitable for transmission on a basis of the priority levels of the packets in the group of data packets suitable for transmission and on the basis of whether or not a data packet was previously submitted for transmission.
119) A switch fabric as defined in claim 97, wherein said memory is a first memory, said switch fabric including a second memory wherein said second memory includes a plurality of sectors associated with respective receivers of said plurality of receivers, said sectors capable of storing data packets forwarded to said receivers by cells of said array.
120) A switch fabric as defined in claim 119, wherein each receiver of said plurality of receivers communicates with said I/O interface.
121) A switch fabric as defined in claim 120, wherein said control entity is a first control entity, said switch fabric including a second control entity to regulate a release of data packets from said sectors to said I/O interface.
122) A switch fabric as defined in claim 121, wherein said second control entity includes a plurality of queue controllers associated with respective sectors of said second memory.
123) A switch fabric as defined in claim 122, wherein a data packet received by a receiver of said plurality of receivers is characterized .by a priority level selected in a group of priority levels, each sector of said second memory being divided in subdivisions each subdivision capable of storing at least one data packet, each subdivision being associated with a given priority level of said group of priority levels.
124) A switch fabric as defined in claim 123, wherein said second control entity includes an arbiter in communication with said queue controllers, each queue controller operative to transmit a control signal to the arbiter of said second control entity for each data packet held in the sector associated with the queue controller to request release of the data packet to said I/O interface.
125) A switch fabric as defined in claim 124, wherein each control signal conveys the priority level of the data packet associated with the control signal.
126) A switch fabric as defined in claim 125, wherein said arbiter selects a data packet for release to said I/O interface among the data packets corresponding to the control signals transmitted to the arbiter of said second control entity on the basis of the levels of priority of the data packets corresponding to the control signals.
127) A switch fabric as defined in claim 92, wherein said control entity is operative to alter the parameters associated with respective data packets of the plurality of data packets.
128) A switch fabric as defined in claim 93, wherein said control entity is operative to alter the priority levels associated with respective data packets of said plurality of data packets.
129) A switch fabric as defined in claim 128, wherein said control entity is operative to alter the priority level associated with a given data packet of said plurality of data packets at least in part on a basis of a time of residence of the given data packet in said memory.
130) A switch fabric as defined in claim 129, wherein said control entity is operative to alter the priority level associated with the given data packet according to a function that relates the priority level of the given data packet to the time of residence of the data packet, the function selected in the group consisting of linear function, exponential function and logarithmic function.
131) A switch fabric as defined in claim 94, wherein each data packet comprises a plurality of words including a first word of said data packet and a last word of said data packet, wherein each word comprises a field indicative of whether said word is a pre-determined number of words away from said last word of said data packet.
132) A switch fabric as defined in claim 131, wherein the transmitter is operative to monitor said field in each word of each data packet forwarded to at least one cell of said array, the transmitter further being operative to begin forwarding a next data packet upon detecting that said field of a word in a packet currently being forwarded is indicative of said word being a pre-determined number of words away from the last word of said data packet currently being forwarded.
133) A switch fabric as defined in claim 94, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination.
134) A switch fabric as defined in claim 95, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination, wherein data packets received by the transmitter in a given cell from the I/O
interface and from the CPU in said given cell share the data channel associated with said given cell.
interface and from the CPU in said given cell share the data channel associated with said given cell.
135) A switch fabric as defined in claim 94, each cell further including a central processing unit (CPU) connected to the plurality of receivers, said receivers being further operative to determine whether data packets are to be released to the I/O interface or to the CPU and release said data packets accordingly.
136) A switch fabric as claimed in claim 135, wherein each data packet comprises a field indicative of whether the data packet is destined for a CPU
and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
137) A switch fabric as defined in claim 113, each cell further including a central processing unit (CPU) connected to the plurality of receivers, wherein said control entity includes a first arbiter for processing said control signals to select a data packet to transmit to the I/O interface among the plurality of data packets suitable for transmission to the I/O interface, wherein said control entity includes a second arbiter for processing said control signals to select a data packet to transmit to the CPU among the plurality of data packets suitable for transmission to the CPU.
138) A switch fabric implemented on a chip, comprising:
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array, permitting:
I) exchange of data packets between the cells of said array;
II) exchange of control information between the cells of said array;
d) each cell operative to control transmission of data packets to other cells of said array at least in part on a basis of the control information.
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array, permitting:
I) exchange of data packets between the cells of said array;
II) exchange of control information between the cells of said array;
d) each cell operative to control transmission of data packets to other cells of said array at least in part on a basis of the control information.
139) A switch fabric as defined in claim 138, wherein said array of cells includes:
a) a plurality of data channels for transporting data packets between the cells of said array; and b) a plurality of channels distinct from said data channels for conveying the control information to the cells of said array.
a) a plurality of data channels for transporting data packets between the cells of said array; and b) a plurality of channels distinct from said data channels for conveying the control information to the cells of said array.
140) A switch fabric as defined in claim 139, wherein each of the channels of the plurality of channels distinct from said data channels interconnects two cells of said array.
141 ) A switch fabric as defined in claim 140, wherein each cell of said array includes:
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells of said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
a) a transmitter in communication with said I/O interface and in communication with every other cell of said array, said transmitter operative to process a data packet received from said I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on a basis of the determined destination;
b) a plurality of receivers associated with respective cells of said array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver;
c) said receivers in communication with said I/O interface for releasing data packets to said I/O interface.
142) A switch fabric as defined in claim 141, wherein each data channel of said plurality of data channels is associated with a given cell of said array, the data channel associated with said given cell connecting the transmitter of said given cell to receivers in cells other than said given cell and associated with said given cell.
143) A switch fabric as defined in claim 141, wherein each data channel of said plurality of data channels is associated with a given cell of said array, the data channel associated with said given cell connecting the transmitter of said given cell to a receiver in every cell of said array of cells and associated with said given cell.
144) A switch fabric as defined in claim 143, wherein the plurality of data channels are independent from one another, wherein transmission of a data packet over one data channel is made independently of transmission of a data packet over another data channel.
145) A switch fabric as defined in claim 144, wherein each data channel performs a parallel data transfer.
146) A switch fabric as defined in claim 145, wherein the transmitter of said given cell includes a memory for storing data packets received from said I/O
interface.
interface.
147) A switch fabric as defined in claim 144, wherein said memory includes a plurality of segments, each segment being associated with a receiver in a cell of said array to which the transmitter of said given cell is capable of forwarding a data packet via a data channel from said plurality of data channels.
148) A switch fabric as defined in claim 147, wherein the transmitter of said given cell includes a control entity, said control entity being operative to process a data packet forwarded from said I/O interface to determine a cell of said array to which the data packet is destined and identify on a basis of the determined cell a segment of said memory in which the packet is to be loaded.
149) A switch fabric as defined in claim 148, wherein said control entity includes a plurality of queue controllers associated with respective segments of said memory.
150) A switch fabric as defined in claim 149, wherein said memory implements a plurality of registers, each register being associated with a queue controller and being suitable for holding data representative of a degree of occupancy of a segment of said memory associated with the queue controller.
151) A switch fabric as defined in claim 150, wherein a data packet received by said transmitter from said I/O interface is characterized by a priority level selected in a group of priority levels, each segment of said memory being partitioned into slots, each slot capable of storing at least one data packet, each slot being associated with a given priority level of said group of priority levels.
152) A switch fabric as defined in claim 151, wherein the registers of said memory associated with each queue controller store data indicative of a degree of occupancy of the slots of said segment associated with the queue controller, for each priority level of the group of priority levels.
153) A switch fabric as defined in claim 152, wherein said memory is a first memory; wherein each cell includes a second memory, said second memory being divided into a plurality of sectors corresponding to respective ones of the receivers associated with the cell, said sectors capable of storing data packets forwarded to the receivers; and wherein the control information is passed between said control entity and each receiver associated with said given cell and is indicative of a degree of occupancy of the sector corresponding to each receiver associated with said given cell.
154) A switch fabric as defined in claim 153, wherein said control entity communicates with each receiver associated with said given cell via a channel from said plurality of channels distinct from said data channels to receive the control information.
155) A switch fabric as defined in claim 154, wherein said plurality of channels distinct from said data channels are back channels, there being a dedicated back channel between said control entity and respective receivers associated with said given cell.
156) A switch fabric as defined in claim 155, wherein each back channel transfers data serially.
157) A switch fabric as defined in claim 156, wherein said first memory includes an area for storing data derived from the control information, indicative of the degree of occupancy of the sectors of receivers associated with said given cell.
158) A switch fabric as defined in claim 157, wherein said control entity is operative to process the data derived from the control information to determine which data packet stored in said first memory is suitable for transmission to a receiver.
159) A switch fabric as defined in claim 158, wherein when said control entity determines that a data packet is suitable for transmission, said control entity generates a control signal to request transmission of the data packet.
160) A switch fabric as defined in claim 159, wherein when said control entity determines that a plurality of data packets are suitable for transmission, said control entity generates a plurality of control signals to request transmission of the data packets, each control signal being associated with a data packet.
161) A switch fabric as defined in claim 160, wherein said control entity includes an arbiter for processing said control signals to select a data packet to transmit among the plurality of data packets suitable for transmission.
162) A switch fabric as defined in claim 161, wherein a data packet is characterized by a priority level, wherein each control signal conveys the priority level of the data packet associated with the control signal.
163) A switch fabric as defined in claim 162, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission at least in part on a basis of the priority levels of the plurality of data packets suitable for transmission.
164) A switch fabric as defined in claim 163, wherein said arbiter processes control signals to request transmission of data packets in a round robin manner.
165) A switch fabric as defined in claim 164, wherein said arbiter selects a data packet to transmit among the plurality of data packets suitable for transmission on a basis of the priority levels of the plurality of data packets suitable for transmission and on the basis of whether or not a data packet was previously submitted for transmission.
166) A switch fabric as defined in claim 165, wherein each receiver of said plurality of receivers communicates with said I/O interface.
167) A switch fabric as defined in claim 166, wherein said control entity is a first control entity, the plurality of receivers of each cell include a second control entity to regulate a release of data packets from the sectors of the receivers to said I/O interface.
168) A switch fabric as defined in claim 141, wherein each data packet comprises a plurality of words including a first word of said data packet and a last word of said data packet, wherein each word comprises a field indicative of whether said word is a pre-determined number of words away from said last word of said data packet.
169) A switch fabric as defined in claim 168, wherein the transmitter is operative to monitor said field in each word of each data packet forwarded to at least one cell of said array, the transmitter further being operative to begin forwarding a next data packet upon detecting that said field of a word in a packet currently being forwarded is indicative of said word being a pre-determined number of words away from the last word of said data packet currently being forwarded.
170) A switch fabric as defined in claim 141, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination.
171) A switch fabric as defined in claim 142, each cell further including a central processing unit (CPU) connected to the transmitter, said transmitter being further operative to process a data packet received from said CPU to determine a destination of the data packet and forward the data packet to at least one cell of said array selected on the basis of the determined destination, wherein data packets received by the transmitter in a given cell from the I/O
interface and from the CPU in said given cell share the data channel associated with said given cell.
interface and from the CPU in said given cell share the data channel associated with said given cell.
172) A switch fabric as defined in claim 141, each cell further including a central processing unit (CPU) connected to the plurality of receivers, said receivers being further operative to determine whether data packets are to be released to the I/O interface or to the CPU and release said data packets accordingly.
173) A switch fabric as claimed in claim 172, wherein each data packet comprises a field indicative of whether the data packet is destined for a CPU
and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
and wherein said receivers are operative to determine whether data packets are to be released to the I/O interface or to the CPU on the basis of said field.
174) A switch fabric as defined in claim 160, each cell further including a central processing unit (CPU) connected to the plurality of receivers, wherein said control entity includes a first arbiter for processing said control signals to select a data packet to transmit to the I/O interface among the plurality of data packets suitable for transmission to the I/O interface, wherein said control entity includes a second arbiter for processing said control signals to select a data packet to transmit to the CPU among the plurality of data packets suitable for transmission to the CPU.
175) A router, comprising:
a) a routing layer, said routing layer including a plurality of I/O ports for exchanging data with components external to said router;
b) a switching layer to switch data packets between I/O ports of said routing layer, said switching layer including an array of cells in communication with said routing layer for permitting exchange of data packets between said array of cells and said routing layer;
c) each cell including a memory for receiving a data packet from said routing layer;
d) said routing layer including a controller to control release of a data packet toward a cell of said array at feast in part on a basis of a degree of occupancy of the memory in said cell.
a) a routing layer, said routing layer including a plurality of I/O ports for exchanging data with components external to said router;
b) a switching layer to switch data packets between I/O ports of said routing layer, said switching layer including an array of cells in communication with said routing layer for permitting exchange of data packets between said array of cells and said routing layer;
c) each cell including a memory for receiving a data packet from said routing layer;
d) said routing layer including a controller to control release of a data packet toward a cell of said array at feast in part on a basis of a degree of occupancy of the memory in said cell.
176) A router as defined in claim 175, wherein said routing layer comprising a memory for storing data packets for release to said switching layer, said controller controlling release of data packets from the memory of said routing layer.
177) A router as defined in claim 176, wherein the memory of said routing layer includes an area for storing data indicative of a degree of occupancy of the memory of said cell.
178) A router as defined in claim 177, wherein said controller is in communication with said memory to obtain access to the data indicative of a degree of occupancy of the memory of said cell, said controller controlling release of data packets from the memory of said routing layer at least in part on a basis of the data indicative of a degree of occupancy of the memory of said cell.
179) A router as defined in claim 178, wherein the memory of said routing layer includes a plurality of areas associated with respective cells of said array, each area operative to store data indicative of a degree of occupancy of the memory of a corresponding cell.
180) A router as defined in claim 179, wherein said controller is responsive to a control signal issued by said switching layer to alter the data indicative of a degree of occupancy of the memory of a given cell in the area associated with the given cell.
181) A router as defined in claim 180, wherein each cell of said switching layer is operative to issue a control signal to said controller to convey to said controller data indicative of the degree of occupancy of the memory of the cell.
182) A router as defined in claim 181, wherein the memory of each cell is partitioned into slots, each slot capable of storing a data packet.
183) A router as defined in claim 182, wherein each area associated with a given cell of said array is partitioned into zones, each zone being associated with a slot of the memory of the given cell, each zone containing data indicating if the associated slot of the memory of the given cell is available for reception of a data packet.
184) A router as defined in claim 183, wherein each cell of said array, in response to release of a data packet from a certain slot of the memory of the cell, issues the control signal to convey to said controller data indicative of the degree of occupancy of the memory of the cell.
185) A router as defined in claim 184, wherein the control signal contains information identifying the certain slot of the memory of the cell.
186) A router as defined in claim 185, wherein said controller is responsive to the control signal containing information identifying the certain slot of the memory of the cell to alter the data in the zone of the memory of the routing layer associated with the certain slot.
187) A switch fabric implemented on a chip, comprising:
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for receiving a data packet from said I/O interface; and II) a control signal path for transporting a control signal to a component external to said array of cells, the control signal being indicative of a degree of occupancy of said memory.
a) an array of cells;
b) an I/O interface in communication with said array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells;
c) each cell communicating with at least one other cell of said array permitting exchange of data packets between the cells of said array;
d) each cell including:
I) a memory for receiving a data packet from said I/O interface; and II) a control signal path for transporting a control signal to a component external to said array of cells, the control signal being indicative of a degree of occupancy of said memory.
188) A switch fabric as defined in claim 187, wherein said memory is partitioned into slots, each slot capable of storing a data packet.
189) A switch fabric as defined in claim 188, wherein the control signal indicative of a degree of occupancy of said memory contains information indicating whether a slot of said memory is free to accept a data packet.
190) A switch fabric as defined in claim 189, wherein in response to release of a data packet from a certain cell of said memory, said cell generating the control signal, the control signal including information identifying the certain cell.
191) A router, comprising:
a) a routing layer, said routing layer including a plurality of I/O ports for exchanging data with components external to said router; and b) a switching layer in communication with said routing layer to switch data packets between I/O ports of said routing layer;
c) said routing layer including a controller, said controller responsive to reception of a control signal containing information indicating that said switching layer is capable of accepting a data packet, to release a data packet to said switching layer.
a) a routing layer, said routing layer including a plurality of I/O ports for exchanging data with components external to said router; and b) a switching layer in communication with said routing layer to switch data packets between I/O ports of said routing layer;
c) said routing layer including a controller, said controller responsive to reception of a control signal containing information indicating that said switching layer is capable of accepting a data packet, to release a data packet to said switching layer.
192) A router as defined in claim 191, wherein said switching layer includes a memory, the control signal containing information indicating the degree of occupancy of said memory.
Applications Claiming Priority (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/870,766 | 2001-06-01 | ||
| US09/870,800 | 2001-06-01 | ||
| US09/870,766 US6990096B2 (en) | 2001-06-01 | 2001-06-01 | Cell-based switch fabric architecture implemented on a single chip |
| US09/870,767 US6990097B2 (en) | 2001-06-01 | 2001-06-01 | Cell-based switch fabric with inter-cell control for regulating packet flow |
| US09/870,841 | 2001-06-01 | ||
| US09/870,800 US7277429B2 (en) | 2001-06-01 | 2001-06-01 | Cell-based switch fabric with distributed scheduling |
| US09/870,767 | 2001-06-01 | ||
| US09/870,841 US7197042B2 (en) | 2001-06-01 | 2001-06-01 | Cell-based switch fabric with cell-to-line-card control for regulating injection of packets |
| US09/870,703 | 2001-06-01 | ||
| US09/870,703 US20020181453A1 (en) | 2001-06-01 | 2001-06-01 | Cell-based switch fabric with distributed arbitration |
| PCT/CA2002/000810 WO2002098066A2 (en) | 2001-06-01 | 2002-05-31 | Cell-based switch fabric architecture on a single chip |
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| CA2448978A1 true CA2448978A1 (en) | 2002-12-05 |
| CA2448978C CA2448978C (en) | 2011-08-09 |
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| US9755907B2 (en) | 2011-09-28 | 2017-09-05 | Hewlett Packard Enterprise Development Lp | Managing a switch fabric |
| WO2014037916A2 (en) * | 2012-09-10 | 2014-03-13 | Marvell World Trade Ltd. | Method and apparatus for transferring packets between interface control modules of line cards |
| KR101519743B1 (en) * | 2013-11-29 | 2015-05-12 | 엘에스산전 주식회사 | Bi-directional Packet Transfer Fail-over Switch for Serial Communication |
| US10841246B2 (en) | 2017-08-30 | 2020-11-17 | Arista Networks, Inc. | Distributed core switching with orthogonal fabric card and line cards |
| US10986423B2 (en) | 2019-04-11 | 2021-04-20 | Arista Networks, Inc. | Network device with compact chassis |
| US11266007B2 (en) | 2019-09-18 | 2022-03-01 | Arista Networks, Inc. | Linecard system using riser printed circuit boards (PCBS) |
| CN112044081B (en) * | 2020-08-26 | 2023-11-10 | 杭州电魂网络科技股份有限公司 | Method and system for updating and inquiring player list |
| CN113868172A (en) * | 2021-09-28 | 2021-12-31 | 上海兆芯集成电路有限公司 | Interconnection interface |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2189112B (en) * | 1986-04-10 | 1990-03-14 | Stc Plc | Automatic telecommunications switching system |
| MX9308193A (en) * | 1993-01-29 | 1995-01-31 | Ericsson Telefon Ab L M | CONTROLLED ACCESS ATM SWITCH. |
| US5790539A (en) * | 1995-01-26 | 1998-08-04 | Chao; Hung-Hsiang Jonathan | ASIC chip for implementing a scaleable multicast ATM switch |
| US5831980A (en) * | 1996-09-13 | 1998-11-03 | Lsi Logic Corporation | Shared memory fabric architecture for very high speed ATM switches |
| US6188690B1 (en) * | 1996-12-12 | 2001-02-13 | Pmc-Sierra, Inc. | Method and apparatus for high speed, scalable communication system |
| US6069895A (en) * | 1997-08-29 | 2000-05-30 | Nortel Networks Corporation | Distributed route server |
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- 2002-05-31 AU AU2002302279A patent/AU2002302279A1/en not_active Abandoned
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| WO2002098066A2 (en) | 2002-12-05 |
| CN1533655A (en) | 2004-09-29 |
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