CN113868172A - Interconnection interface - Google Patents

Interconnection interface Download PDF

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Publication number
CN113868172A
CN113868172A CN202111142604.6A CN202111142604A CN113868172A CN 113868172 A CN113868172 A CN 113868172A CN 202111142604 A CN202111142604 A CN 202111142604A CN 113868172 A CN113868172 A CN 113868172A
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CN
China
Prior art keywords
receiver
transmitter
data
interconnect interface
packet
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Pending
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CN202111142604.6A
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Chinese (zh)
Inventor
王惟林
杨帆
张帅
郑春晖
沈鹏
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Shanghai Zhaoxin Semiconductor Co Ltd
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VIA Alliance Semiconductor Co Ltd
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Publication date
Application filed by VIA Alliance Semiconductor Co Ltd filed Critical VIA Alliance Semiconductor Co Ltd
Priority to CN202111142604.6A priority Critical patent/CN113868172A/en
Priority to US17/506,124 priority patent/US11853250B2/en
Priority to US17/506,144 priority patent/US11675729B2/en
Priority to US17/511,800 priority patent/US11526460B1/en
Priority to US17/523,049 priority patent/US20230101918A1/en
Publication of CN113868172A publication Critical patent/CN113868172A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4013—Coupling between buses with data restructuring with data re-ordering, e.g. Endian conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4031—Coupling between buses using bus bridges with arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling

Abstract

An interconnection interface for use between packages, or between chips. An interconnect interface includes a first transmitter, a first receiver, and an electrical physical layer coupled between the first transmitter and the first receiver. Data provided by a first device is sent from the first transmitter to the electro-physical layer for transmission to the first receiver for retrieval from the first receiver by a second device. The first transmitter includes an arbiter that arbitrates a plurality of channels of the first device to obtain data from the first device. The first transmitter includes a packet generator that packetizes data received from the first device for transmission by the electrophysical layer. The first transmitter further includes a first buffer for buffering data retrieved from the first device for retransmission.

Description

Interconnection interface
Technical Field
The present invention relates to an interconnection interface, and more particularly, to a socket-to-socket interconnection interface between packages and a die-to-die interconnection interface between chips in each package.
Background
Traditional point-to-point transmission is implemented with a high speed serial bus (PCIE).
However, high-speed serial bus (PCIE) complicates the pipeline design, even causes transmission delay to be lengthened, and has the problems of hardware consumption, limited effective bandwidth …, and the like.
There is a need in the art for an interconnect interface that has low latency, high reliability, and high bandwidth utilization.
Disclosure of Invention
The invention discloses a high-performance interconnection interface, which comprises a socket-to-socket interconnection interface between packages and a die-to-die interconnection interface between chips in each package.
An interconnect interface (ZPI/ZDI) implemented according to an embodiment of the invention includes a first transmitter (TX0), a first receiver (RX0), and an electrical physical layer (EPHY) coupled between the first transmitter and the first receiver. Data provided by a first device (socket0/Die0) is sent from the first transmitter to the electrophysical layer for transmission to the first receiver. The first transmitter includes an arbiter (TXARB) that arbitrates among a plurality of channels (CH 1-CHN) of the first device to obtain data from the first device. The first transmitter includes a packet generator (PacketGen) that creates packets (flits) from data received from the first device for transmission by the electrophysical layer. The first transmitter further includes a first buffer (RetryBuf) that buffers data retrieved from the first device for retransmission.
In one embodiment, the first transmitter further comprises a dummy packet generator (FlitGen) for generating dummy packets to be filled into the electro-physical layer transmission when no packet is generated by the packet generator. The first transmitter further includes a parallel-to-serial converter (PtoS) that performs parallel-to-serial conversion on the packet for transmission by the electrical physical layer. The first receiver includes a serial-to-parallel converter (StoP) that performs serial-to-parallel conversion on packets transmitted from the electrical physical layer. The first receiver also includes a decoder (FlitDec) to decode the data from the received packet. The first receiver further includes a check logic module for discarding the received data and enabling the second device to request retransmission from the first device when the check fails. The first receiver further includes an analysis module (RXanls) for analyzing the verified data to allocate a plurality of channels (CH 1-CHN) to the second device.
In one embodiment, the interconnect interface further includes a second transmitter (TX1) and a second receiver (RX1) coupled across the electrical physical layer. The second transmitter is coupled to the second device, and the second receiver is coupled to the first device, so that the interconnection interface is in a full-duplex structure.
In one embodiment, the first transmitter further comprises a retransmission controller (RetryCon). When the checking logic module of the first receiver fails to check data, the second device transmits the retransmission request to the first device through the second transmitter, the electrical physical layer and the second receiver, and the first device drives the retransmission controller to take out the content of the first buffer for retransmission.
In one embodiment, the first transmitter further comprises a state machine (LTSSM) that stops the operation of the arbiter and reduces the transmission rate of the electrophysical layer when switching to a reduced speed state. The first transmitter further includes a second buffer for buffering packets not transmitted by the electrophysical layer when the state machine is in the reduced speed state. In one embodiment, the first receiver further comprises a third buffer for buffering data received from the electrophysical layer for verification and analysis. When the third buffer is full, the second device transmits a speed reduction request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device enables the state machine to be switched to the speed reduction state. In one embodiment, the state machine is switched to the reduced speed state by the first device in response to a low power setting.
In one embodiment, a packet previously transmitted by the first device and the second device through the interconnection interface includes a unit code (FlitCode), a packet information, a Cyclic Redundancy Check (CRC), and a channel code (FEC). Data from the first device or the second device is carried as the packet information. The unit code indicates an attribute of the packet information. The cyclic redundancy check code and the channel code are used for a receiver to check the packet information.
In one embodiment, the first transmitter and the first receiver are pipeline hardware.
In one embodiment, the first device and the second device linked by the interconnection interface are a first package (socket0) and a second package (socket1), respectively. The packets transmitted by the first and second encapsulations through the interconnect interface are of varying lengths and have a size of 2NBit, N is a variable. The first transmitter further includes a data compressor (DataComp) coupled between the arbiter and the packet generator, responsive to a request for an inter-package interconnect variable length packet transmission. The first receiver further includes a data reordering module (DataRea) for reordering the verified data for re-supply to the analyzer in response to a request for an inter-package interconnect variable length packet transmission.
In one embodiment, the first device and the second device linked by the interconnection interface are a first chip (Die0) and a second chip (Die1), respectively. The packets transmitted by the first chip and the second chip through the interconnect interface are of fixed length.
In one embodiment, the first device and the first transmitter are in handshake communication, such that the first transmitter obtains data from the first device and sends the data to the electrophysical layer for transmission to the first receiver. The first receiver communicates with the second device as a handshake, passing data received from the electrophysical layer to the first receiver.
The following description specifically illustrates embodiments of the present invention, with reference to the accompanying drawings.
Drawings
FIG. 1 is an embodiment of an ZPI interconnect interface, where two encapsulating sockets 0 and socket1 are linked by a ZPI interconnect interface (labeled ZPI in the figure);
FIGS. 2A-2C illustrate other planar interconnect embodiments implemented with interconnect interface ZPI between packages;
FIGS. 3A, 3B illustrate a three-dimensional (3D) interconnect embodiment implemented with an interconnect interface ZPI between packages;
FIG. 4 is one embodiment of a ZDI interconnect interface;
FIGS. 5A-5C illustrate a planar interconnect embodiment in which the packages are linked by interconnect interface ZPI and the chips within the packages are linked by interconnect interface ZDI;
FIGS. 6A and 6B illustrate a three-dimensional interconnect embodiment in which the packages are linked by interconnect interface ZPI and the chips inside the packages are linked by interconnect interface ZDI;
FIG. 7 illustrates a package 700 including a chipset 702 and other chips (e.g., compute nodes, co-processors, and accelerators);
FIG. 8 illustrates the communication architecture of interconnect interface ZPI/ZDI of the present invention;
FIGS. 9A, 9B illustrate in waveform diagrams the input/output protocol (I/O protocol) between a device and the interconnect interface ZPI/ZDI;
fig. 10 illustrates a packet format 1000 transmitted by the interconnect interface ZPI/ZDI, according to one embodiment of the invention;
11A, 11B illustrate the information path and hardware structure of interconnect interface ZPI between package socket0 and package socket1, in accordance with one embodiment of the present invention; and
fig. 12A and 12B illustrate the information paths and hardware structures of the interconnection interface ZDI between the chip Die0 and the chip Die1 according to an embodiment of the present invention.
Detailed Description
The following description sets forth various embodiments of the invention. The following description is made for the purpose of illustrating the general principles of the invention and is not meant to limit the invention. The actual invention scope should be determined from the following claims.
The invention discloses a high-performance interconnection interface, which comprises a socket-to-socket interconnection interface between packages and a die-to-die interconnection interface between chips in each package.
First, a socket-to-socket interconnect interface between packages will be described, which will be named ZPI interconnect interface or ZPI hereinafter.
Fig. 1 is an embodiment of an ZPI interconnect interface, in which two package sockets 0 and socket1 are connected with ZPI interconnect interface (labeled ZPI in the figure). Two clusters (clusters) are shown included in each package, labeled cluster0 and cluster 1: other embodiments may have other numbers of clusters. Each cluster includes a number of Central Processing Unit (CPU) cores. Within each package may be a Last Level Cache (LLC), an interconnect bus 102, and various components such as an input/output controller 104, a clock module 106, a power consumption module 108 …, and the like. Each package may also link a two-wire memory module (labeled DIMM).
Through the interconnect interface ZPI, the package socket0 and the socket1 constitute a system in which the cpu cores and i/o resources of all clusters can be uniformly scheduled, and the memories owned by the package socket0 and the socket1 can be uniformly used.
For example, through interconnect interface ZPI, packets (flits) of different encapsulated caches have a consistent format. Thus, any CPU core, or I/O device, of the system formed by the packages may access any memory resource within the system.
Fig. 2A-2C illustrate other interconnect embodiments implemented with interconnect interface ZPI between packages. Fig. 2A, 2B have the packages form a ring link with an interconnect interface ZPI. Fig. 2A is a three-pack ring link. Fig. 2B is a four package ring link. The four packages of fig. 2C have more interconnect interfaces ZPI ensuring the shortest communication path between the packages compared to fig. 2B. The number of packages can be extended to larger values.
Fig. 3A, 3B illustrate a three-dimensional (3D) interconnect embodiment implemented with an interconnect interface ZPI between packages. FIG. 3A implements a three-level interconnect; the packaging sockets 0-3 are a plane (belong to the same layer), and the front layer and the rear layer are respectively packaging sockets 4 and 5. In addition to the front level package socket4 having an interconnect interface ZPI linked to the middle level package socket 3526, an interconnect interface ZPI is linked to the back level package socket5 to form a ring link. Fig. 3B implements a two-layer interconnect. The first-layer planar package sockets 0-3 are linked with the second-layer planar package sockets 4-7 in a one-to-one manner by an interconnection interface ZPI. There may be more layers of the stereoscopic interconnect. The number of planar packages can be extended to larger values.
In addition, the interconnection interface (die-to-die interconnection interface) between the chips is described as follows; this will be designated as ZDI interconnect interface or interconnect interface ZDI in the following.
FIG. 4 is one embodiment of a ZDI interconnect interface. Two chips Die0 and Die1 in a package 400 are shown connected by a ZDI interconnect interface (labeled ZDI in the figure). Other embodiments may have a greater number of chips packaged together. Each chip may include multiple clusters (clusters). Each chip may have, without limitation, a last level cache LLC, an interconnect bus 402, and various components (e.g., input/output controller 404, clock module 406, power consumption module 408 …, etc.).
The above interconnection interfaces ZPI, ZDI can be used jointly so that chips in different packages can communicate with each other.
Fig. 5A-5C illustrate a planar interconnect embodiment in which the packages are linked by interconnect interface ZPI and the chips inside the packages are linked by interconnect interface ZDI. Fig. 5A illustrates three packages annularly linked by interconnect interface ZPI, each die linked by an interconnect interface ZDI; therefore, the six chips form a system, and resources can be shared. Fig. 5B illustrates four packages with interconnect interfaces ZPI ring-linked, with die-in-package chips linked with interconnect interfaces ZDI; therefore, the eight chips form a system, and resources can be shared. In comparison to fig. 5B, fig. 5C has more interconnect interfaces ZPI to minimize the communication path for different packaged chips. The number of chips per package may vary.
Fig. 6A, 6B illustrate a three-dimensional interconnect embodiment in which the packages are linked by interconnect interface ZPI and the chips inside the packages are linked by interconnect interface ZDI. FIG. 6A illustrates a three-level interconnect, each level may be a single package or a multi-package plane, and each package may include multiple chips (e.g., D0, D1); the three-layer plane realizes ring-shaped link with the interconnection interface ZPI, and is matched with the interconnection interface ZDI. Each chip is a node of the system and can control the resources of other nodes. FIG. 6B illustrates a dual-level interconnect, each package including multiple chips on a dual-level plane; the chips on the double-layer structure are each a node of the system and can control the resources of other nodes. The above three-dimensional interconnections may be extended to more layers and any number of chips may be within each package. On chipset (chipset) applications, the interconnect interface ZPI, as well as the ZDI of the present invention, may be used as follows.
Fig. 7 illustrates a package 700 that includes a chipset 702 (a chip) as well as other chips (e.g., compute nodes, co-processors, and accelerators). The chipset 702 is linked to other chips such as compute nodes, co-processors, accelerators, etc. via an interconnect interface ZDI. To form a larger system, multiple chipset packages may be linked by an interconnect interface ZPI to form the planar interconnect architecture of fig. 2A-2C, or the volumetric interconnect architecture of fig. 3A, 3B. In one embodiment, multiple chipsets may be included within a single package; to form a larger system, such multiple packages may be linked by interconnect interface ZPI to form the planar interconnect architecture of fig. 5A-5C, or the volumetric interconnect architecture of fig. 6A, 6B.
Fig. 8 illustrates the communication architecture of the interconnect interface ZPI/ZDI of the present invention. The interconnect interface 800 provides a bi-directional transmission channel between the devices Device0 and Device1, and is a full duplex design that allows simultaneous bi-directional transmission. In one embodiment, the devices Device0 and Device are two packages and the interconnect interface 800 is a ZPI interconnect interface. In another embodiment, the devices 0 and Device are two chips and the interconnect interface 800 is a ZDI interconnect interface.
The Device0 sends out the packet signal 802 and the clock signal 804 via the transmitter TX0 of the interconnect interface 800 to be received by the receiver RX0 of the Device1 coupled to the interconnect interface 800. Conversely, the Device1 may send out the packet signal 806 and the clock signal 808 via the transmitter TX1 of the interconnect interface 800 to be received by the receiver RX1 of the interconnect interface 800 at the Device 0.
Fig. 9A, 9B illustrate in waveform diagrams the input/output protocol (I/O protocol) between a device and the interconnect interface ZPI/ZDI.
The data signal TX _ ENTRY of the source device is transmitted by the transmitter TX of the interconnection interface, transmitted to the receiver RX at the other end of the transmission line through the transmission line (EPHY) of the interconnection interface, received as the data signal RX _ ENTRY and then delivered to the target device.
Fig. 9A shows handshake communication between the source device and the transmitter TX of the interconnect interface ZPI/ZDI, causing the transmitter TX to fetch transmission content (TX transmission sequence) from the source device.
The signal READY/ACTIVE pulls up, indicating that the interconnect interface ZPI/ZDI is indeed established. Clock (CLK) T0, source device pull signal TX _ REQ and transmitter TX pull signal TX _ ACK responds, handshaking informs the transfer of data signal TX _ ENTRY from the source device to the transmitter TX. Clock T1, signals TX _ REQ and TX _ ACK are dropped, temporarily not fetching data from the source device. Clocks T2-T3, the source device pulls up the signal TX _ REQ, but the transmitter TX has not pulled up the signal TX _ ACK; indicating that the source device is ready for data signals but that the transmitter TX has not yet fetched data from the source device. Clock T4, signals TX _ REQ and TX _ ACK are pulled up and the data signal TX _ ENTRY from the source device is handed over to transmitter TX. The transmitter TX succeeds in taking the data signal from the source device. Clock T5, signals TX _ REQ and TX _ ACK conditions handshake with clock T1 informs the source device of the end of data transfer to interconnect interface ZPI/ZDI. From clocks T6 to T7, the transmitter TX is ready to fetch data from the source device (pull signal TX _ ACK), but the source device does not have data (drop signal TX _ REQ).
Fig. 9B shows handshake communication between the receiver RX of the interconnection interface ZPI/ZDI and the target device, so that the transmission content (RX transmission sequence) received by the receiver RX can be handed over to the target device.
The signal READY/ACTIVE pulls up, indicating that the interconnect interface ZPI/ZDI is indeed established. Clock T0, receiver RX pull signal RX _ REQ of interconnect interface ZPI/ZDI, and target device pull signal RX _ ACK respond, handshaking informs the passage of data signal RX _ ENTRY from receiver RX to target device. Clock T1, signals RX _ REQ and RX _ ACK are dropped, at which time no data has yet been taken from receiver RX. Clock T2, receiver RX pulls up signal RX _ REQ, but the target device has not pulled up signal RX _ ACK; the representative receiver RX is ready for data signals, but the target device has not yet received data from the receiver RX. Clock T3, signals RX _ REQ and RX _ ACK are pulled up, and data signal RX _ ENTRY taken by receiver RX from interconnect interface ZPI/ZDI transmission line is delivered to the target device; the target device successfully acquires the data signal from the receiver RX. The clock T4, the RX _ REQ and RX _ ACK signals, along with the clock T1, handshake signals the interconnect interface ZPI/ZDI that the data transfer to the target device is complete. Clocks T5-T6 indicate that the target device is ready to fetch data from receiver RX (pull signal RX _ ACK), but receiver RX does not have data (drop signal RX _ REQ). Clock T7, signals RX _ REQ, and RX _ ACK pull up to again handshake notification of the transfer of data signal RX _ ENTRY from receiver RX to the target device. However, the target device may have a mechanism to reject the received data (e.g., the target device may consider its buffer status, or otherwise reject the data from the interconnect interface ZPI/ZDI). Clocks T8, T9, the target device pull signal RX _ BNT requests blocking of the incoming data, and the receiver RX responds to the pull signal RX _ ACK, indicating acknowledgement of the blocking request.
Fig. 10 illustrates a format 1000 of packets transmitted by the interconnect interface ZPI/ZDI according to an embodiment of the present invention, including a unit code FlitCode, packet information, a cyclic redundancy check code CRC, and a channel coding (or forward error correction code) FEC. Interconnection interface ZPI uses a format 1000 of length 2NBits, of indefinite length. In interconnect interface ZDI applications, the length of format 1000 is a fixed length.
The unit code FlitCode may comprise 5 bits, meaning as follows:
1: (tlpenable) representing packet information taken from the information signal TX _ Entry;
0: (tlpdisable) indicating that the packet information is not taken from the information signal TX _ Entry but is dummy content generated by the interconnect interface ZPI/ZDI;
000 _: (ACK/NAK DLLP) to put forward retransmission (retry) requirements;
01 _: (FCI/FCU DLLP) for feeding back buffer status of the receiver RX;
1000 _: (PM related DLLP) for power management;
1100 _; (DLLP disable) indicating that the packet information has no valid content;
1111 _: (Reserved for PHY) for padding with start, end, or idle flags for transmissions.
11A, 11B illustrate the information path and hardware structure of the interconnect interface ZPI between package socket0 and package socket1, in accordance with one embodiment of the present invention. As shown, package socket0 links transmitter TX of interconnect interface ZPI, so that data signals of package socket0 are transmitted via transmitter TX to phy of interconnect interface ZPI for transmission and received by receiver RX of interconnect interface ZPI, and passed to package socket1 linked to the other end of interconnect interface ZPI. The full duplex reverse path (package socket 1-socket 0) is also so designed. The clock of the interconnect interface ZPI is generated by a phase locked loop PLL and a clock generator CLKgen.
Fig. 11A illustrates the transmitter TX in particular in detail. The package socket0 delivers multiple types of data to the arbiter TXARB in the transmitter TX via different channels CH1 CHN for arbitration. The data winning arbitration is compressed by the data compressor DataComp and sent to the packet generator PacketGen to generate packets (flits, e.g., format 1000). The data transmitted through the channels CH1 to CHN may include a plurality of packets for each cycle when generating the packets, and the plurality of packets may have the same format and different contents, or may be one packet for each cycle, depending on the amount of data and the data format. When the package socket0 has no data transmission requirement, the interconnect interface ZPI may generate a null packet by itself using the dummy packet generator FlitGen, in which dummy content is filled. Then, through the parallel-to-serial converter PtoS, the packets are transmitted to the receiver RX on the other side of the interconnect interface ZPI through the phy, and then delivered to one of the corresponding channels CH 1-CHN in the package socket1 according to the data type.
The hardware of interconnect interface ZPI may be in a pipelined (pipelined) design. For transmitter TX, when packet generator PacketGen wraps the first data packet, data compressor DataComp is compressing the second data, and arbiter TXARB is arbitrating the third data. The interconnect interface ZPI operates efficiently.
The transmitter TX may buffer the transmission data with a buffer RetryBuf. If the receiver RX finds that there is a data error from the phy, the retransmission mechanism is activated. The retransmission controller RetryCon takes out the data that failed in transmission from the buffer RetryBuf, and the packet generator PacketGen repackages the data into a packet for retransmission. One implementation is to send a retry request from the RX side of package socket1 to the retry of the TX side of package socket1 (the TX side of socket1 is not shown in fig. 11A), driving the retry controller RetryCon of package socket 1. Referring to fig. 8, in fig. 8, TX0 and RX1 belong to socket1, and TX1 and RX0 belong to socket 0. After RX1 fails to verify the data, the package socket1 may issue a retransmission request, which is transmitted from the sender TX0 of socket1, through the phy and the receiver RX0 of socket0 to the package socket0, and the package socket0 drives the retransmission controller RetryCon to extract the contents of the buffer RetryBuf for retransmission.
The illustration also contemplates a state machine LTSSM for interconnect interface ZPI for controlling the transfer rate of interconnect interface ZPI. In one embodiment, the state machine LTSSM may switch to a reduced speed state, pausing the arbiter TXARB and the data compressor DataComp so that no more data is provided to the packet generator PacketGen wrapper. In addition, the state machine LTSSM may also control the transmission rate of the electrophysical layer EPHY to achieve the speed reduction of the interconnect interface ZPI. The state machine LTSSM can be switched to the reduced speed state by the package socket0 in response to a low power consumption requirement, reducing the transmission rate of the interconnect interface ZPI. In another embodiment, the receiver RX may be jammed (e.g., a buffer in the receiver RX is full), and the package socket1 may send a speed-down request to the package socket0 (not shown to the transmission hardware in the other direction in the figure via the interconnect interface ZPI), so that the package socket0 requests the state machine LTSSM to switch the transmission rate of the interconnect interface ZPI. Referring to FIG. 8, when the buffer in the receiver RX is full, the packet socket1 issues a speed reduction request from the transmitter TX1, the EPHY layer, and the receiver RX1 to the packet socket0, and the state machine LTSSM is switched to the speed reduction state by the packet socket 0. In one embodiment, the PtoS converter includes a buffer to handle speed reduction. For example, if the LTSSM reduces the EPHY rate, the buffer is used to buffer data that cannot be transferred to the other side.
Fig. 11B illustrates the details of the receiver RX in particular. The packet received from the EPHY of the electric physical layer is converted by a serial-to-parallel converter StoP, unpacked by a decoder FlitDec and checked by a check logic. The check logic may be based on a cyclic redundancy check, CRC, code and a channel coding, FEC. If the check fails, the receiver RX skips the received data and triggers the retransmission mechanism. If the verification is passed, the received data is rearranged by a data rearrangement module datarear (data rearrangement), and then distributed to a corresponding channel CH1 … CHN in the package socket1 by an analysis module RXanls, so that transmission from the package socket0 to the interconnection interface ZPI of the package socket1 is completed. The hardware of the receiver RX may also be designed in a pipeline (pipelined) manner. When the analysis module RXanls analyzes the first data, the data rearrangement module datarean rearranges the second data to be checked, and the decoder FlitDec unpacks the third data. The interconnect interface ZPI operates efficiently.
Fig. 12A, 12B illustrate the information paths and hardware structures of the interconnection interface ZDI between chip Die0 and chip Die1, according to one embodiment of the present invention. In particular, the indeterminate format 1000 length (2) differs from the interconnection interface ZPINBits), the format 1000 length of the interconnect interface ZDI is a fixed length. In contrast to the transmitter TX details of interconnect interface ZPI of fig. 11A, interconnect interface ZDI transmitter TX of fig. 12A does not have data compressor DataComp. In contrast to the receiver RX details of interconnect interface ZPI of fig. 11B, interconnect interface ZDI receiver RX of fig. 12B does not have data reordering module datareal. The check retransmission and state machine speed reduction mechanism can be designed as shown in FIGS. 11A and 11B.
In summary, an interconnect interface (ZPI/ZDI) implemented according to an embodiment of the invention includes a first transmitter (TX0), a first receiver (RX0), and an electrical physical layer (EPHY) coupled between the first transmitter and the first receiver. Data provided by a first device (socket0/Die0) is sent by the first transmitter to the electrophysical layer for transmission to the first receiver for retrieval from the first receiver by a second device (socket1/Die 1). The first transmitter includes an arbiter (TXARB) that arbitrates among a plurality of channels (CH 1-CHN) of the first device to obtain data from the first device. The first transmitter includes a packet generator (PacketGen) that creates packets (flits) from data received from the first device for transmission by the electrophysical layer. The first transmitter further includes a first buffer (RetryBuf) that buffers data retrieved from the first device for retransmission.
In one embodiment, the first transmitter further comprises a dummy packet generator (FlitGen) for generating dummy packets to be filled into the electro-physical layer transmission when no packet is generated by the packet generator. The first transmitter further includes a parallel-to-serial converter (PtoS) that performs parallel-to-serial conversion on the packet for transmission by the electrical physical layer. The first receiver includes a serial-to-parallel converter (StoP) that performs serial-to-parallel conversion on packets transmitted from the electrical physical layer. The first receiver also includes a decoder (FlitDec) to decode the data from the received packet. The first receiver further includes a check logic module for discarding the received data and enabling the second device to request retransmission from the first device when the check fails. The first receiver further includes an analysis module (RXanls) for analyzing the verified data to allocate a plurality of channels (CH 1-CHN) to the second device.
In one embodiment, the interconnect interface further includes a second transmitter (TX1) and a second receiver (RX1) coupled across the electrical physical layer. The second transmitter is coupled to the second device, and the second receiver is coupled to the first device, so that the interconnection interface is in a full-duplex structure.
The interconnection interface of the invention also has the design of retransmission, speed reduction, etc., and has exclusive transmission grouping, and the hardware is a pipeline architecture. The communication between the interconnection interface and the device is handshake communication.
Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (20)

1. An interconnect interface, comprising:
a first transmitter, and a first receiver; and
an electro-physical layer coupled between the first transmitter and the first receiver,
wherein:
the first transmitter is further coupled to a first device, and the first receiver is further coupled to a second device;
the data provided by the first device is sent to the electric physical layer by the first transmitter and transmitted to the first receiver;
the first transmitter comprises an arbiter for arbitrating a plurality of channels of the first device to obtain data from the first device;
the first transmitter includes a packet generator for generating packets from the data received from the first device for transmission by the electrophysical layer; and
the first transmitter further includes a first buffer for buffering data retrieved from the first device for retransmission.
2. The interconnect interface of claim 1, wherein:
the first transmitter further includes a dummy packet generator that generates dummy packets and fills the dummy packets to the EPL transmission when the packet generator does not generate the packets.
3. The interconnect interface of claim 2, wherein:
the first transmitter also comprises a parallel-to-serial converter which performs parallel-to-serial conversion on the packet and transmits the packet to the electrical physical layer for transmission; and
the first receiver includes a serial-to-parallel converter that serial-to-parallel converts packets transmitted from the electrical physical layer.
4. The interconnect interface of claim 3, wherein:
the first receiver also includes a decoder that decodes the data from the received packet, the data including data provided by the first device.
5. The interconnect interface of claim 4, wherein:
the first receiver further includes a check logic module for discarding the received data and enabling the second device to request retransmission from the first device when the check fails.
6. The interconnect interface of claim 5, wherein:
the first receiver further includes an analysis module for analyzing the verified data to allocate a plurality of channels to the second device.
7. The interconnect interface of claim 6, further comprising:
a second transmitter and a second receiver coupled to both ends of the EPL,
the second transmitter is coupled to the second device, and the second receiver is coupled to the first device, so that the interconnection interface is in a full-duplex structure.
8. The interconnect interface of claim 7, wherein:
the first transmitter further comprises a retransmission controller;
when the checking logic module of the first receiver fails to check data, the second device transmits the retransmission request to the first device through the second transmitter, the electrical physical layer and the second receiver, and the first device drives the retransmission controller to take out the content of the first buffer for retransmission.
9. The interconnect interface of claim 7, wherein:
the first transmitter further includes a state machine that, when switched to a reduced speed state, disables the arbiter and reduces the transmission rate of the E-PHY.
10. The interconnect interface of claim 9, wherein:
the first transmitter further includes a second buffer for buffering the packet that has not been transmitted by the electrophysical layer when the state machine is in the reduced speed state.
11. The interconnect interface of claim 10, wherein:
the first receiver also comprises a third buffer for buffering the data received from the electric physical layer for verification and analysis;
when the third buffer is full, the second device transmits a speed reduction request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device enables the state machine to be switched to the speed reduction state.
12. The interconnect interface of claim 10, wherein:
the state machine is switched to the reduced speed state by the first device in response to a low power setting.
13. The interconnect interface of claim 10, wherein:
the packet previously transmitted by the first device and the second device through the interconnect interface includes a unit code, a packet information, a cyclic redundancy check code, and a channel code;
data taken from the first device or the second device is loaded as the grouping information;
the unit code indicates the attribute of the packet information; and
the cyclic redundancy check code and the channel code are used for a receiver to check the packet information.
14. The interconnect interface of claim 13, wherein:
the unit code includes data indicating the packet information as dummy content or data taken from the device;
the unit code includes a flag indicating whether the packet information is a retransmission request; and
the unit code includes a flag indicating whether the packet information is fed back to the buffer status of the receiver to switch the interconnect interface to a reduced speed state.
15. The interconnect interface of claim 14, wherein:
the unit code includes a flag indicating whether the packet information is a power management request;
the unit code includes a content indicating whether the packet information is valid; and
the unit code includes a flag indicating whether the packet is a start, end, or idle transmission.
16. The interconnect interface of claim 6, wherein:
the first transmitter and the first receiver are pipeline hardware.
17. The interconnect interface of claim 6, wherein:
the first device and the second device are linked to form a first package and a second package respectively; and
the packets transmitted by the first and second encapsulations through the interconnect interface are of varying lengths and have a size of 2NBit, N is a natural number.
18. The interconnect interface of claim 17, wherein:
the first transmitter further includes a data compressor, coupled between the arbiter and the packet generator, responsive to a request for an inter-package interconnect variable length packet transmission; and
the first receiver further comprises a data reordering module for reordering the checked data for re-supply to the analyzer in response to a need for an inter-package interconnect variable length packet transmission.
19. The interconnect interface of claim 6, wherein:
the first device and the second device which are linked are respectively a first chip and a second chip; and
the packets transmitted by the first chip and the second chip through the interconnect interface are of fixed length.
20. The interconnect interface of claim 1, wherein:
the first device and the first transmitter are in handshake communication, so that the first transmitter acquires data from the first device and sends the data to the electrical physical layer for transmission to the first receiver; and
the first receiver communicates with the second device as a handshake, passing data received from the electrophysical layer to the first receiver.
CN202111142604.6A 2021-09-28 2021-09-28 Interconnection interface Pending CN113868172A (en)

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US17/506,124 US11853250B2 (en) 2021-09-28 2021-10-20 Interconnect interface
US17/506,144 US11675729B2 (en) 2021-09-28 2021-10-20 Electronic device and operation method of sleep mode thereof
US17/511,800 US11526460B1 (en) 2021-09-28 2021-10-27 Multi-chip processing system and method for adding routing path information into headers of packets
US17/523,049 US20230101918A1 (en) 2021-09-28 2021-11-10 Interconnect system

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