CA2426422C - Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele - Google Patents

Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele Download PDF

Info

Publication number
CA2426422C
CA2426422C CA2426422A CA2426422A CA2426422C CA 2426422 C CA2426422 C CA 2426422C CA 2426422 A CA2426422 A CA 2426422A CA 2426422 A CA2426422 A CA 2426422A CA 2426422 C CA2426422 C CA 2426422C
Authority
CA
Canada
Prior art keywords
node
data
logic
storage
rings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA2426422A
Other languages
English (en)
Other versions
CA2426422A1 (fr
Inventor
John Hess
Coke S. Reed
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interactic Holdings LLC
Original Assignee
Interactic Holdings LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interactic Holdings LLC filed Critical Interactic Holdings LLC
Publication of CA2426422A1 publication Critical patent/CA2426422A1/fr
Application granted granted Critical
Publication of CA2426422C publication Critical patent/CA2426422C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

Selon la présente invention, de multiples processeurs peuvent accéder aux mêmes données en parallèle en mettant en oeuvre diverses techniques innovatrices. Tout d'abord, plusieurs processeurs à distance peuvent effectuer une requête de lecture depuis un même emplacement de données et les requêtes peuvent être satisfaites dans des périodes de temps se chevauchant. Ensuite, plusieurs processeurs peuvent accéder à un élément de données qui est situé au même emplacement et peut lire, écrire ou réaliser plusieurs opérations aux mêmes moments se chevauchant d'élément de données, puis un paquet de données peut être diffusé sélectivement vers plusieurs emplacements et plusieurs paquets peuvent être diffusés sélectivement vers plusieurs ensembles d'emplacements cibles.
CA2426422A 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele Expired - Fee Related CA2426422C (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US69360300A 2000-10-19 2000-10-19
US09/693,603 2000-10-19
PCT/US2001/050543 WO2002033565A2 (fr) 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele

Publications (2)

Publication Number Publication Date
CA2426422A1 CA2426422A1 (fr) 2002-04-25
CA2426422C true CA2426422C (fr) 2012-04-10

Family

ID=24785344

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2426422A Expired - Fee Related CA2426422C (fr) 2000-10-19 2001-10-19 Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele

Country Status (7)

Country Link
EP (1) EP1360595A2 (fr)
JP (1) JP4128447B2 (fr)
CN (1) CN100341014C (fr)
AU (1) AU2002229127A1 (fr)
CA (1) CA2426422C (fr)
MX (1) MXPA03003528A (fr)
WO (1) WO2002033565A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8605099B2 (en) 2008-03-31 2013-12-10 Intel Corporation Partition-free multi-socket memory system architecture
CN101833439B (zh) * 2010-04-20 2013-04-10 清华大学 基于分合思想的并行计算硬件结构
CN102542525B (zh) * 2010-12-13 2014-02-12 联想(北京)有限公司 一种信息处理设备以及信息处理方法
US10168923B2 (en) 2016-04-26 2019-01-01 International Business Machines Corporation Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module
US10236043B2 (en) * 2016-06-06 2019-03-19 Altera Corporation Emulated multiport memory element circuitry with exclusive-OR based control circuitry
FR3083350B1 (fr) * 2018-06-29 2021-01-01 Vsora Acces memoire de processeurs
US10872038B1 (en) * 2019-09-30 2020-12-22 Facebook, Inc. Memory organization for matrix processing
CN117294412B (zh) * 2023-11-24 2024-02-13 合肥六角形半导体有限公司 基于单比特位移的多通道串转并自动对齐电路及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4977582A (en) * 1988-03-31 1990-12-11 At&T Bell Laboratories Synchronization of non-continuous digital bit streams
US5043981A (en) * 1990-05-29 1991-08-27 Advanced Micro Devices, Inc. Method of and system for transferring multiple priority queues into multiple logical FIFOs using a single physical FIFO
US5923654A (en) * 1996-04-25 1999-07-13 Compaq Computer Corp. Network switch that includes a plurality of shared packet buffers
US6289021B1 (en) * 1997-01-24 2001-09-11 Interactic Holdings, Llc Scaleable low-latency switch for usage in an interconnect structure

Also Published As

Publication number Publication date
MXPA03003528A (es) 2005-01-25
AU2002229127A1 (en) 2002-04-29
WO2002033565A3 (fr) 2003-08-21
WO2002033565A2 (fr) 2002-04-25
CN100341014C (zh) 2007-10-03
CN1489732A (zh) 2004-04-14
JP4128447B2 (ja) 2008-07-30
EP1360595A2 (fr) 2003-11-12
JP2004531783A (ja) 2004-10-14
CA2426422A1 (fr) 2002-04-25

Similar Documents

Publication Publication Date Title
US5797035A (en) Networked multiprocessor system with global distributed memory and block transfer engine
EP0696367B1 (fr) Reseau d'interconnexion processeur-memoire a temps de latence variable
KR900006791B1 (ko) 패킷 스위치식 다중포트 메모리 n×m 스위치 노드 및 처리 방법
Tamir et al. Dynamically-allocated multi-queue buffers for VLSI communication switches
US4621359A (en) Load balancing for packet switching nodes
US5630162A (en) Array processor dotted communication network based on H-DOTs
US4837676A (en) MIMD instruction flow computer architecture
Felperin et al. Routing techniques for massively parallel communication
US5594918A (en) Parallel computer system providing multi-ported intelligent memory
CA2426422C (fr) Structure d'interconnexion adaptable autorisant un traitement parallele et l'acces a une memoire parallele
US5765015A (en) Slide network for an array processor
WO2006069355A2 (fr) Procede et appareil permettant une communication efficace entre des elements de traitement d'une unite processeur
US20050036445A1 (en) Processing data packets
WO1986003038A1 (fr) Ordinateur a flux d'instructions
Liu Architecture and performance of processor-memory interconnection networks for MIMD shared memory parallel processing systems
EP0570952A2 (fr) Réseau transparent pour un processeur à architecture parallèle
Sakai et al. Design and implementation of a circular omega network in the EM-4
Sharif et al. Design and simulations of a serial-link interconnection network for a massively parallel computer system
Dickey et al. Hardware combining and scalability
Khan et al. A transputer routing algorithm for non‐linear or dynamic finite elementanalysis
Coll et al. A strategy for efficient and scalable collective communication in the Quadrics network
US20050038902A1 (en) Storing data packets
Lay High-performance communication in parallel computers
Ashraf Routing in multicomputer networks: A classification and comparison
Yoo et al. Multistage ring network: a new multiple ring network for large scale multiprocessors

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20131021