CA2398441A1 - Procede et appareil d'operations electroniques equilibrees - Google Patents

Procede et appareil d'operations electroniques equilibrees Download PDF

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Publication number
CA2398441A1
CA2398441A1 CA002398441A CA2398441A CA2398441A1 CA 2398441 A1 CA2398441 A1 CA 2398441A1 CA 002398441 A CA002398441 A CA 002398441A CA 2398441 A CA2398441 A CA 2398441A CA 2398441 A1 CA2398441 A1 CA 2398441A1
Authority
CA
Canada
Prior art keywords
bit
hamming
neutral
bits
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002398441A
Other languages
English (en)
Inventor
James Zhengchu Xiao
Harold J. Johnson
Stanley T. Chow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cloakware Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA002298990A external-priority patent/CA2298990A1/fr
Application filed by Individual filed Critical Individual
Priority to CA002398441A priority Critical patent/CA2398441A1/fr
Publication of CA2398441A1 publication Critical patent/CA2398441A1/fr
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q20/00—Payment architectures, schemes or protocols
    • G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
    • G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
    • G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/0806—Details of the card
    • G07F7/0813—Specific details related to card security
    • G07F7/082—Features insuring the integrity of the data on or in the card
    • G—PHYSICS
    • G07—CHECKING-DEVICES
    • G07F—COIN-FREED OR LIKE APPARATUS
    • G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
    • G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
    • G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
    • G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/04—Masking or blinding
    • H04L2209/046—Masking or blinding of operations, operands or results of the operations

Abstract

Etant donné que les microprocesseurs et d'autres dispositifs électroniques deviennent plus rapides et utilisent des densités de composants supérieures, le bruit généré par les transitions entre les états de données ont une plus grande influence sur les performances et la sécurité de ces dispositifs. Des calculs et des processus réalisés au moyen du procédé de l'invention vont avoir un nombre constant de transitions de bits, minimisant ainsi le rebondissement sur la terre et les effets similaires. Dans un mode de réalisation préféré, ceci est réalisé en remplaçant des processus logiciels à fuites avec des tables de recherche remplies de données de sortie correspondant aux sorties du processus logiciel indexé à l'aide de valeurs d'opérandes correspondantes. L'invention se révèle particulièrement utile dans l'implémentation de carte à puce à protection DES (standard de chiffrement des données), ladite protection pouvant être déverrouillée si la signature électrique est contrôlée au moment où les données sont traitées.
CA002398441A 2000-02-18 2001-02-19 Procede et appareil d'operations electroniques equilibrees Abandoned CA2398441A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002398441A CA2398441A1 (fr) 2000-02-18 2001-02-19 Procede et appareil d'operations electroniques equilibrees

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CA002298990A CA2298990A1 (fr) 2000-02-18 2000-02-18 Methode et systeme de resistance a l'analyse de puissance
CA2,298,990 2000-02-18
PCT/CA2001/000199 WO2001061914A2 (fr) 2000-02-18 2001-02-19 Procede et appareil d'operations electroniques equilibrees
CA002398441A CA2398441A1 (fr) 2000-02-18 2001-02-19 Procede et appareil d'operations electroniques equilibrees

Publications (1)

Publication Number Publication Date
CA2398441A1 true CA2398441A1 (fr) 2001-08-23

Family

ID=25681549

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002398441A Abandoned CA2398441A1 (fr) 2000-02-18 2001-02-19 Procede et appareil d'operations electroniques equilibrees

Country Status (1)

Country Link
CA (1) CA2398441A1 (fr)

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Legal Events

Date Code Title Description
FZDE Discontinued