CA2350466A1 - Improved result handling in a multiprocessing system - Google Patents

Improved result handling in a multiprocessing system Download PDF

Info

Publication number
CA2350466A1
CA2350466A1 CA002350466A CA2350466A CA2350466A1 CA 2350466 A1 CA2350466 A1 CA 2350466A1 CA 002350466 A CA002350466 A CA 002350466A CA 2350466 A CA2350466 A CA 2350466A CA 2350466 A1 CA2350466 A1 CA 2350466A1
Authority
CA
Canada
Prior art keywords
job
memory
pointer
speculatively
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002350466A
Other languages
English (en)
French (fr)
Inventor
Per Anders Holmberg
Lars-Orjan Kling
Sten Edward Johnson
Terje Egeland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9803901A external-priority patent/SE9803901D0/xx
Application filed by Individual filed Critical Individual
Publication of CA2350466A1 publication Critical patent/CA2350466A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Advance Control (AREA)
  • Information Transfer Systems (AREA)
CA002350466A 1998-11-16 1999-11-12 Improved result handling in a multiprocessing system Abandoned CA2350466A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
SE9803901-9 1998-11-16
SE9803901A SE9803901D0 (sv) 1998-11-16 1998-11-16 a device for a service network
SE9902373-1 1999-06-22
SE9902373A SE9902373D0 (sv) 1998-11-16 1999-06-22 A processing system and method
PCT/SE1999/002063 WO2000029941A1 (en) 1998-11-16 1999-11-12 Improved result handling in a multiprocessing system

Publications (1)

Publication Number Publication Date
CA2350466A1 true CA2350466A1 (en) 2000-05-25

Family

ID=26663436

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002350466A Abandoned CA2350466A1 (en) 1998-11-16 1999-11-12 Improved result handling in a multiprocessing system

Country Status (9)

Country Link
EP (1) EP1131702B1 (https=)
JP (1) JP4608100B2 (https=)
KR (1) KR100437227B1 (https=)
AU (1) AU1437200A (https=)
BR (1) BR9915369A (https=)
CA (1) CA2350466A1 (https=)
DE (1) DE69940784D1 (https=)
SE (1) SE9902373D0 (https=)
WO (1) WO2000029941A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263331A (ja) * 2002-03-07 2003-09-19 Toshiba Corp マルチプロセッサシステム
WO2004042574A2 (en) * 2002-10-31 2004-05-21 Lockheed Martin Corporation Computing machine having improved computing architecture and related system and method
GB2401748B (en) * 2003-05-14 2005-04-13 Motorola Inc Apparatus and method of memory allocation therefor
KR100957060B1 (ko) * 2007-12-12 2010-05-13 엠텍비젼 주식회사 명령어 병렬 스케줄러, 방법 및 그 기록매체
US8572359B2 (en) 2009-12-30 2013-10-29 International Business Machines Corporation Runtime extraction of data parallelism
US9696995B2 (en) 2009-12-30 2017-07-04 International Business Machines Corporation Parallel execution unit that extracts data parallelism at runtime
US8683185B2 (en) 2010-07-26 2014-03-25 International Business Machines Corporation Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
US9086909B2 (en) * 2011-05-17 2015-07-21 Oracle International Corporation System and method for supporting work sharing muxing in a cluster
CN104025045B (zh) * 2011-11-04 2017-07-04 学校法人早稻田大学 处理器系统及加速器
KR101603429B1 (ko) * 2014-09-03 2016-03-14 (주)솔투로 빅데이터의 멀티프로세스 분배를 통한 멀티 출력 장치 및 그 방법
US10042773B2 (en) * 2015-07-28 2018-08-07 Futurewei Technologies, Inc. Advance cache allocator

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
ES2138051T3 (es) * 1994-01-03 2000-01-01 Intel Corp Metodo y aparato para la realizacion de un sistema de resolucion de bifurcaciones en cuatro etapas en un procesador informatico.
US5875326A (en) * 1997-04-25 1999-02-23 International Business Machines Corporation Data processing system and method for completing out-of-order instructions
US5870597A (en) * 1997-06-25 1999-02-09 Sun Microsystems, Inc. Method for speculative calculation of physical register addresses in an out of order processor
US6240509B1 (en) * 1997-12-16 2001-05-29 Intel Corporation Out-of-pipeline trace buffer for holding instructions that may be re-executed following misspeculation

Also Published As

Publication number Publication date
DE69940784D1 (de) 2009-06-10
EP1131702A1 (en) 2001-09-12
JP4608100B2 (ja) 2011-01-05
AU1437200A (en) 2000-06-05
SE9902373D0 (sv) 1999-06-22
KR20010080468A (ko) 2001-08-22
EP1131702B1 (en) 2009-04-22
KR100437227B1 (ko) 2004-06-23
BR9915369A (pt) 2001-08-14
JP2002530736A (ja) 2002-09-17
WO2000029941A1 (en) 2000-05-25

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Legal Events

Date Code Title Description
FZDE Discontinued