CA2330169A1 - Multiplicateur de mots longue distance utilisant le codage booth - Google Patents

Multiplicateur de mots longue distance utilisant le codage booth Download PDF

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Publication number
CA2330169A1
CA2330169A1 CA 2330169 CA2330169A CA2330169A1 CA 2330169 A1 CA2330169 A1 CA 2330169A1 CA 2330169 CA2330169 CA 2330169 CA 2330169 A CA2330169 A CA 2330169A CA 2330169 A1 CA2330169 A1 CA 2330169A1
Authority
CA
Canada
Prior art keywords
carry
bit
adder
sum
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2330169
Other languages
English (en)
Inventor
Maher Amer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chartoleaux KG LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CA002294554A external-priority patent/CA2294554A1/fr
Application filed by Individual filed Critical Individual
Priority to CA 2330169 priority Critical patent/CA2330169A1/fr
Publication of CA2330169A1 publication Critical patent/CA2330169A1/fr
Abandoned legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
CA 2330169 1999-12-30 2001-01-02 Multiplicateur de mots longue distance utilisant le codage booth Abandoned CA2330169A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA 2330169 CA2330169A1 (fr) 1999-12-30 2001-01-02 Multiplicateur de mots longue distance utilisant le codage booth

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002294554A CA2294554A1 (fr) 1999-12-30 1999-12-30 Methode et circuit de multiplication utilisant le code de booth et l'addition iterative
CA2,294,554 1999-12-30
CA 2330169 CA2330169A1 (fr) 1999-12-30 2001-01-02 Multiplicateur de mots longue distance utilisant le codage booth

Publications (1)

Publication Number Publication Date
CA2330169A1 true CA2330169A1 (fr) 2001-06-30

Family

ID=25681457

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2330169 Abandoned CA2330169A1 (fr) 1999-12-30 2001-01-02 Multiplicateur de mots longue distance utilisant le codage booth

Country Status (1)

Country Link
CA (1) CA2330169A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit
US7330869B2 (en) 2002-12-05 2008-02-12 Micron Technology, Inc. Hybrid arithmetic logic unit
US7827226B2 (en) 2002-12-05 2010-11-02 Micron Technology, Inc. Hybrid arithmetic logic unit

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Legal Events

Date Code Title Description
EEER Examination request
FZDE Dead

Effective date: 20130102