CA2320612A1 - Compact chip labelling using stepper technology - Google Patents
Compact chip labelling using stepper technology Download PDFInfo
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- CA2320612A1 CA2320612A1 CA002320612A CA2320612A CA2320612A1 CA 2320612 A1 CA2320612 A1 CA 2320612A1 CA 002320612 A CA002320612 A CA 002320612A CA 2320612 A CA2320612 A CA 2320612A CA 2320612 A1 CA2320612 A1 CA 2320612A1
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- reticle
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
A method is provided for printing identification patterns on photoresist-coated wafers comprising integrated electronic circuits or other devices. The photoresist is subjected to at least 2 partial exposures of electromagnetic radiation via a first and a second reticle. The first reticle comprises an area transparent to electromagnetic radiation having a surface equal to or greater than the surface of the identification pattern to be printed on the photoresist. The second reticle comprises a plurality of identification patterns. The photoresist is exposes sequentially to the projection of each reticle such that the desired identification pattern and the area of the first reticle are projected on the same area of the photoresist with the proviso that the sum of the partial doses is equal to or greater than the dose required for full sensitization. This method allows the printing of small identification characters on wafers using the stepper technology.
Description
COMPACT CHIP LABELLING USING STEPPER TECHNOLOGY
Field of Invention This invention relates generally to the manufacture of integrated circuits.
More specifically, this invention relates to a method of labelling each die on a wafer during the manufacture of integrated circuits with identification information that can identify and distinguish the position of each die on the wafer. Even more specifically this invention relates to a method of labelling each die on a wafer during the manufacture of integrated circuits where an identification label occupies a minimal space on the die.
Background of the Invention Modern electronic systems, such as network optoelectronic systems typically, contain several integrated circuit devices, each of which has a specific function or functions to perform. Each of these functions must be performed correctly or the electronic system will not function properly. When one of the modern electronic systems fails, it is necessary for the manufacturer of the electronic system to determine which integrated circuit device caused the failure.
In addition, when the specific semiconductor device that caused the failure is identified, it is desirable for the manufacturer of the specific integrated circuits device to be able to identify during testing procedures (such as by customer return failure analysis) in which manufacturing lot the integrated circuit device was manufactured.
Field of Invention This invention relates generally to the manufacture of integrated circuits.
More specifically, this invention relates to a method of labelling each die on a wafer during the manufacture of integrated circuits with identification information that can identify and distinguish the position of each die on the wafer. Even more specifically this invention relates to a method of labelling each die on a wafer during the manufacture of integrated circuits where an identification label occupies a minimal space on the die.
Background of the Invention Modern electronic systems, such as network optoelectronic systems typically, contain several integrated circuit devices, each of which has a specific function or functions to perform. Each of these functions must be performed correctly or the electronic system will not function properly. When one of the modern electronic systems fails, it is necessary for the manufacturer of the electronic system to determine which integrated circuit device caused the failure.
In addition, when the specific semiconductor device that caused the failure is identified, it is desirable for the manufacturer of the specific integrated circuits device to be able to identify during testing procedures (such as by customer return failure analysis) in which manufacturing lot the integrated circuit device was manufactured.
These testing procedures assist the manufacturer of the integrated circuit device to determine the manufacturing dependent anomalies associated with a location of that individual die on the wafer.
One difficulty with retaining labelling of each die during each stage of the manufacturing integrated circuits is that there is a limited space on each die surface for labelling purposes.
Many prior art methods use a die labeling method during the process of semiconductor manufacturing.
For example, in United States Patent 6,063,685 for "Device Level Identification Methodology", Steffan discloses the method of individual labeling of dies by laser. The laser draws the identification label on each die during the final lithographic stage of the process.
United States Patent 5,733,711 for "Process for Forming Both Fixed and Variable Creation Patterns on a Single Photoresist Resin Mask", Juengling provides an opportunity to form an unique pattern onto a wafer. This method needs additional embedded equipment such as a computer controlled laser. Additional equipment will complicate the lithographic process and will make the labeling process of each die longer.
Other methods are used in a lithographic process of semiconductors for manufacturing the multiplicity of masks.
For example, in United States Patent 5,036,209 for "Fabrication Method for Semiconductors Devices and Transparent Mask for Charged Particle Beam", Kataoka discloses an apparatus wherein a combination of masks is allowed to reduce the charged beam pattern through the masks and the same is projected onto a semiconductor device substrate to be exposed. This apparatus gives an opportunity project individually selected small areas of the mask with a pattern having a plurality of images to be formed onto a semiconductor device substrate.
One difficulty with retaining labelling of each die during each stage of the manufacturing integrated circuits is that there is a limited space on each die surface for labelling purposes.
Many prior art methods use a die labeling method during the process of semiconductor manufacturing.
For example, in United States Patent 6,063,685 for "Device Level Identification Methodology", Steffan discloses the method of individual labeling of dies by laser. The laser draws the identification label on each die during the final lithographic stage of the process.
United States Patent 5,733,711 for "Process for Forming Both Fixed and Variable Creation Patterns on a Single Photoresist Resin Mask", Juengling provides an opportunity to form an unique pattern onto a wafer. This method needs additional embedded equipment such as a computer controlled laser. Additional equipment will complicate the lithographic process and will make the labeling process of each die longer.
Other methods are used in a lithographic process of semiconductors for manufacturing the multiplicity of masks.
For example, in United States Patent 5,036,209 for "Fabrication Method for Semiconductors Devices and Transparent Mask for Charged Particle Beam", Kataoka discloses an apparatus wherein a combination of masks is allowed to reduce the charged beam pattern through the masks and the same is projected onto a semiconductor device substrate to be exposed. This apparatus gives an opportunity project individually selected small areas of the mask with a pattern having a plurality of images to be formed onto a semiconductor device substrate.
This method cannot solve the problem of forming small identification symbols on a wafer surface.
In United States Patent 6,040,892 for "Multi Image Reticle for Forming Layers", Pierrat, discloses a method for forming a layer of the wafer using a combination of reticles. The first reticle consists of a two dimensional array of patterns and the second reticle has an aperture which allows for the transfer of a selected image from the array of the first reticle. This method cannot solve the problem of forming a small unique label onto a die.
Therefore, there is a need for a die labeling method that can provide a distinct label for each die or particular group of dies during the step-and-repeat process for the production of semiconductor devices. Labels must be associated with a die location on the wafer during a step-and-repeat process of manufacturing semiconductor devices. An important requirement is that the label must consume as little space on a die as possible. Another very important requirement is that the labeling method must use existing step-and-repeat technology without the need for additional equipment implementation into the step-and-repeat apparatus.
Summary of the Invention According to the present invention, the foregoing and other objects and advantages are attained by a method of identifying individual semiconductor devices during the manufacturing process of the semiconductor devices. Each individual semiconductor device is marked during a lithographic stepping exposure with a projection of three masks in the step-and-repeat lithographic system.
Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of one embodiment of the invention in conjunction with the accompanying drawings.
Brief Description of the Drawings The invention will be described with reference to the accompanying drawings, wherein:
FIG. 1 is a schematic plan view of a wafer coated by photoresist and the arrangement of particular dies, labels, and projected stepper field onto a wafer surface;
FIG.2 is an schematic fragmentary isometric view of masks and final pattern on a wafer;
FIG.3 is an enlarged schematic fragmentary isometric view of masks with labels pattern and final labels pattern on a wafer;
FIG. 4 is a graph of a functional dependence resist thickness from exposure dose for positive lithographic process. The graph shows a preferred exposure dose range;
FIG. 5 illustrates various enlarged fragmentary schematic plan views of the second mask with identification symbols and the wafer surface;
FIG. 6 is a cross section schematic view of two separate mask projection into a same photoresist on a wafer surface and the wafer after developing;
Detailed Description of the Invention In order to understand the method of forming the photoresist pattern herein, in this description all drawings are shown with the scale of masks pattern and pattern to be forming $ onto the wafer being equal. In an actual embodiment, as is well known, the scale of the image on the reticle is many times larger than the image being formed onto the wafer. A
positive lithographic process is described hereafter.
Referring first to FIG. 1, there is schematically shown the final pattern to be formed on the wafer photoresist coating 100. In the integrated circuit technology the pattern of integrated circuits becomes very complicated. As a result of that complexity, the pattern scale of the reticle is much larger than the pattern to be formed onto the wafer. The step-and-repeat technology provides an opportunity of forming the pattern by projection of the same reticle or by projecting the same set of reticles. Each individual area 102, 104, 106, 108 is divided 1$ into discrete areas - die 110. The die is that part of the wafer which at the end of the manufacturing process will be an integrated circuits device. Each die 110 comprises the identical set of elements as integrated circuit pattern 112 and auxiliary elements such as identification symbols 114 (F), 116 (X2, Y1) or other information such as a distinguishing code of the integrated circuit. The symbol 114 e.g. the letter "F" is an area identification symbol. These identification symbols e.g. "F" of the group of dies 110, 118, 126, 132 represent the location of the areas of the projection onto the wafer surface.
All dies 110,118, 126, 132 formed by a projection or projections in area 102 on the wafer thus have the same identification symbol e.g. the letter "F" in this case. The identification symbols 116, 122, 130,134 e.g. X1 Y1, X2Y1 etc. are used to represent the locations of the dies 110,118, 126, 2$ 132, within the area 102 of the wafer and relative to imaginary XY axes.
The same identification technique is applied to the individual dies in the remaining projection areas 104, 106, 108 on the wafer. This particular example shows each reticle with four dies. As is well known one reticle can contain thousands of dies each with an integrated circuit pattern.
In the embodiment shown, the pattern on the wafer 100 is located in the area 102 which is formed by separate projections in sequence of three reticles. FIG 2 depicts a schematic view of three reticles 200, 210, 220 and final pattern of the area 102 (FIG 1 ) of the wafer 100.
Reticles 200, 210, 220 have a pattern which is formed onto the wafer.
According to one embodiment of this method, the integrated circuits pattern 112, 120, 133, 135 and identification symbols e.g. X1Y1, X2Y1, X1Y2, X2Y2 are formed by the first projection of the reticle 200 in the area of the wafer 102. The reticle 200 comprises the pattern of integrated circuits 201, 202, 203, 204 and identification symbols X1Y1, X2Y1, X1Y2, X2Y2. The identification symbols 205, 206, 207, 208 represent the location of each die 110, 118, 126, 132 in the area 102. The first projection of reticle 200 is completed with an equal or greater than full exposure dose. A full exposure dose is defined as the dose required to fully activate the photoactive compound in the resist coating of a wafer so that the photosensitive polymer becomes fully soluble in the developer solution.
The projection of reticle 200 transfers all patterns of reticle 200 onto the area 102 of the wafer. Identification symbols e.g. "F" are formed by alternate projection of reticles 210 and 220. The projection order of reticles 200, 210 and 220 is irrelevant. The wafer is placed in the step-and-repeat apparatus during a cycle of process of forming the pattern by proj ections and reticles are changed. Projections of reticle 200 and reticles 210, 220 onto wafer 230 In this particular embodiment of the invention , the sequence of individual reticles projections is following: the first projection - reticle 200, the second - reticle 210 and third - reticle 220 into the wafer's photoresist coating.
The pattern of reticle 210 comprises the plurality of elements 212, 214, 216, 218. Each of them is an open aperture with identical size and shape. All elements are located in the same position of die.
The quantity elements are equal to the quantity of dies to be formed onto the wafer during one technological cycle of forming pattern.
The pattern of reticle 220 comprises the sets of identification symbols 222, 224, 226, 228 wherein the number of individual symbols eg. "A", "B", "E", "F" in this set corresponds to the number of the projections required to cover the surface of the wafer. This particular example is shown with four projections 102, 104, 106,108 (FIG.1) and reticle 220 has four identification symbols (eg. A, B, C, D) in each set 222, 224, 226, 228 correspondingly. The projection of two reticles 210 and 220 are transferred only one identification symbol eg. "F"
from sets of identification symbols 222, 224, 226, 228 of reticle 220.
FIG. 3 schematically shows a mutual location of reticles 200, 210, 220 and the wafer 102.
The combination of the three reticle projections forms the distinguished pattern of identification symbols which determine an exact position of each individual die on the wafer during manufacturing process by step-and-repeat apparatus. The pattern of the identification symbol eg. X1 Y1 associated with a die location into one projection is formed by projection reticle 200 with full dose of light radiation 300. The mutual positions of the reticle 210 and the wafer 100 in the step-and-repeat apparatus are arranged in such manner that the pattern of the area identification symbol 207 eg. XlYl of the reticle 200 is projected into the predefined area 341 of the wafer 100. The image of the identification symbol 136 eg. "F"
is associated with the area location of the projection onto the wafer. This identification symbol eg. "F" is formed by separate projections of reticles 210, 220. The projection of each reticle is accomplished with a dose of light radiation less than a full dose, but such the total of the two projections equals at least a full exposure dose. The reticle 210 and the wafer 100 are located in a such manner that the open aperture 216 is proj ected onto the predefined area 346 for an identification symbol which is associated with a projection location on the wafer.
During the next projection the position reticle220 and wafer 100 are located in a such manner that the identification symbol eg. "F" to be formed onto the wafer 100 is projected onto the area 346 which was earlier irradiated by the projection of reticle 210. The size and shape of the projection of the open aperture 216 of reticle 210 on the area 346 of the wafer 100 is such that only one identification symbol can be fitted in. In this particular example this is the letter "F" which is associated with the projection area 102 (FIG.1).
For a better understanding of the arrangement of the reticle with the area identification symbols and the wafer FIG. 5 shows the fragmentary plan view of the reticle 502 and the wafer 506 with the earlier proj ected but undeveloped image of open aperture 508. In the area 102 (FIG.1) all dies are labeled by the same identification symbols "F". This symbol is formed by projection of the reticle 502 with identification symbols in such manner that during proj ection the reticle 502 letter "F" overlaps with the previous irradiated area 530 onto the photosensitive coating of the wafer.
In the area 104 (FIG.l) all dies are labeled by the same identification symbols "B". This symbol is formed by projection of the reticle with identification symbols in such manner that during proj ection the reticle 502 letter "B" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
In the area 106 (FIG.1) all dies are labeled by the same identification symbols "A". This symbol is formed by projection of the reticle with identification symbols in such manner that during projection the reticle 502 letter "A" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
In the area 108 (FIG.1) all dies are labeled by the same identification symbols "E". This symbol is formed by projection of the reticle with identification symbols in such manner that during proj ection the reticle 502 letter "E" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
As a result of the overlapping said overlapped area receives at least a full exposure dose and can be developed further.
Refernng now to FIG. 6, there is a schematically shown method of forming a layer with a pattern on the wafer surface by the separate projection of two reticles during the manufacture of semiconductor devices by a step-and-repeat type apparatus according to one embodiment of the present invention.
FIG. 6, the case that an image which size is the same as the pattern formed on a reticle is transmitted to the surface of the wafer will be described in order to understand a method of forming a photoresist pattern. In another embodiment, the size of image on the reticle can be enlarged up to 10 times bigger than the image being forming onto the wafer.
In the present embodiment a lithographic process is being shown in the attached drawings as a positive.
During the first exposure, light 600 is irradiated onto a separate projection reticle 620. The reticle 620 used in this embodiment has a projection pattern 622 consisting of a light-absorbing material, for example, chromium, which is formed on the underside of, for example, a transparent basic glass plate 619 . Light passed through the reticle 620 is partially interrupted by the projection pattern 622 . Light passed through the reticle 620 is focused by a lens 625, and thus is irradiated onto a semiconductor wafer 630. On the upper surface of the wafer 630, a photoresist film 631 is applied. By the irradiation of said light 600, the photoresist coating 131 is exposed corresponding to the projection pattern formed on the reticle 620. Thus, a desired pattern can be projected onto the wafer 130.
The dose of exposure of the first reticle has to be at least 10% and no more than 90% full exposure dose. Therein the full dose is defined as the dose required to activate the photoactive compound in the resist coating 631of a wafer 630 so that the photosensitive polymer becomes fully soluble in the developer solution.
During the second exposure, light 600 is irradiated onto a projection reticle 602. The reticle 602 used in this embodiment has a projection pattern 622 consisting of a light-absorbing material, for example, chromium, which is formed on the underside of, for example, a transparent basic glass plate 619. Light passed through the reticle 620 is partially interrupted by the projection pattern 622. Light passed through the reticle 620 is focused by a lens 125, and thus is irradiated onto said semiconductor wafer 630.. By the irradiation of said light, the photo-resist film is exposed corresponding to the projection pattern formed on the reticle 620. Thus, a desired pattern can be proj ected onto said wafer 630. The dose of exposure have to be at least 10% and less than 90% of a full exposure dose.
In United States Patent 6,040,892 for "Multi Image Reticle for Forming Layers", Pierrat, discloses a method for forming a layer of the wafer using a combination of reticles. The first reticle consists of a two dimensional array of patterns and the second reticle has an aperture which allows for the transfer of a selected image from the array of the first reticle. This method cannot solve the problem of forming a small unique label onto a die.
Therefore, there is a need for a die labeling method that can provide a distinct label for each die or particular group of dies during the step-and-repeat process for the production of semiconductor devices. Labels must be associated with a die location on the wafer during a step-and-repeat process of manufacturing semiconductor devices. An important requirement is that the label must consume as little space on a die as possible. Another very important requirement is that the labeling method must use existing step-and-repeat technology without the need for additional equipment implementation into the step-and-repeat apparatus.
Summary of the Invention According to the present invention, the foregoing and other objects and advantages are attained by a method of identifying individual semiconductor devices during the manufacturing process of the semiconductor devices. Each individual semiconductor device is marked during a lithographic stepping exposure with a projection of three masks in the step-and-repeat lithographic system.
Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of one embodiment of the invention in conjunction with the accompanying drawings.
Brief Description of the Drawings The invention will be described with reference to the accompanying drawings, wherein:
FIG. 1 is a schematic plan view of a wafer coated by photoresist and the arrangement of particular dies, labels, and projected stepper field onto a wafer surface;
FIG.2 is an schematic fragmentary isometric view of masks and final pattern on a wafer;
FIG.3 is an enlarged schematic fragmentary isometric view of masks with labels pattern and final labels pattern on a wafer;
FIG. 4 is a graph of a functional dependence resist thickness from exposure dose for positive lithographic process. The graph shows a preferred exposure dose range;
FIG. 5 illustrates various enlarged fragmentary schematic plan views of the second mask with identification symbols and the wafer surface;
FIG. 6 is a cross section schematic view of two separate mask projection into a same photoresist on a wafer surface and the wafer after developing;
Detailed Description of the Invention In order to understand the method of forming the photoresist pattern herein, in this description all drawings are shown with the scale of masks pattern and pattern to be forming $ onto the wafer being equal. In an actual embodiment, as is well known, the scale of the image on the reticle is many times larger than the image being formed onto the wafer. A
positive lithographic process is described hereafter.
Referring first to FIG. 1, there is schematically shown the final pattern to be formed on the wafer photoresist coating 100. In the integrated circuit technology the pattern of integrated circuits becomes very complicated. As a result of that complexity, the pattern scale of the reticle is much larger than the pattern to be formed onto the wafer. The step-and-repeat technology provides an opportunity of forming the pattern by projection of the same reticle or by projecting the same set of reticles. Each individual area 102, 104, 106, 108 is divided 1$ into discrete areas - die 110. The die is that part of the wafer which at the end of the manufacturing process will be an integrated circuits device. Each die 110 comprises the identical set of elements as integrated circuit pattern 112 and auxiliary elements such as identification symbols 114 (F), 116 (X2, Y1) or other information such as a distinguishing code of the integrated circuit. The symbol 114 e.g. the letter "F" is an area identification symbol. These identification symbols e.g. "F" of the group of dies 110, 118, 126, 132 represent the location of the areas of the projection onto the wafer surface.
All dies 110,118, 126, 132 formed by a projection or projections in area 102 on the wafer thus have the same identification symbol e.g. the letter "F" in this case. The identification symbols 116, 122, 130,134 e.g. X1 Y1, X2Y1 etc. are used to represent the locations of the dies 110,118, 126, 2$ 132, within the area 102 of the wafer and relative to imaginary XY axes.
The same identification technique is applied to the individual dies in the remaining projection areas 104, 106, 108 on the wafer. This particular example shows each reticle with four dies. As is well known one reticle can contain thousands of dies each with an integrated circuit pattern.
In the embodiment shown, the pattern on the wafer 100 is located in the area 102 which is formed by separate projections in sequence of three reticles. FIG 2 depicts a schematic view of three reticles 200, 210, 220 and final pattern of the area 102 (FIG 1 ) of the wafer 100.
Reticles 200, 210, 220 have a pattern which is formed onto the wafer.
According to one embodiment of this method, the integrated circuits pattern 112, 120, 133, 135 and identification symbols e.g. X1Y1, X2Y1, X1Y2, X2Y2 are formed by the first projection of the reticle 200 in the area of the wafer 102. The reticle 200 comprises the pattern of integrated circuits 201, 202, 203, 204 and identification symbols X1Y1, X2Y1, X1Y2, X2Y2. The identification symbols 205, 206, 207, 208 represent the location of each die 110, 118, 126, 132 in the area 102. The first projection of reticle 200 is completed with an equal or greater than full exposure dose. A full exposure dose is defined as the dose required to fully activate the photoactive compound in the resist coating of a wafer so that the photosensitive polymer becomes fully soluble in the developer solution.
The projection of reticle 200 transfers all patterns of reticle 200 onto the area 102 of the wafer. Identification symbols e.g. "F" are formed by alternate projection of reticles 210 and 220. The projection order of reticles 200, 210 and 220 is irrelevant. The wafer is placed in the step-and-repeat apparatus during a cycle of process of forming the pattern by proj ections and reticles are changed. Projections of reticle 200 and reticles 210, 220 onto wafer 230 In this particular embodiment of the invention , the sequence of individual reticles projections is following: the first projection - reticle 200, the second - reticle 210 and third - reticle 220 into the wafer's photoresist coating.
The pattern of reticle 210 comprises the plurality of elements 212, 214, 216, 218. Each of them is an open aperture with identical size and shape. All elements are located in the same position of die.
The quantity elements are equal to the quantity of dies to be formed onto the wafer during one technological cycle of forming pattern.
The pattern of reticle 220 comprises the sets of identification symbols 222, 224, 226, 228 wherein the number of individual symbols eg. "A", "B", "E", "F" in this set corresponds to the number of the projections required to cover the surface of the wafer. This particular example is shown with four projections 102, 104, 106,108 (FIG.1) and reticle 220 has four identification symbols (eg. A, B, C, D) in each set 222, 224, 226, 228 correspondingly. The projection of two reticles 210 and 220 are transferred only one identification symbol eg. "F"
from sets of identification symbols 222, 224, 226, 228 of reticle 220.
FIG. 3 schematically shows a mutual location of reticles 200, 210, 220 and the wafer 102.
The combination of the three reticle projections forms the distinguished pattern of identification symbols which determine an exact position of each individual die on the wafer during manufacturing process by step-and-repeat apparatus. The pattern of the identification symbol eg. X1 Y1 associated with a die location into one projection is formed by projection reticle 200 with full dose of light radiation 300. The mutual positions of the reticle 210 and the wafer 100 in the step-and-repeat apparatus are arranged in such manner that the pattern of the area identification symbol 207 eg. XlYl of the reticle 200 is projected into the predefined area 341 of the wafer 100. The image of the identification symbol 136 eg. "F"
is associated with the area location of the projection onto the wafer. This identification symbol eg. "F" is formed by separate projections of reticles 210, 220. The projection of each reticle is accomplished with a dose of light radiation less than a full dose, but such the total of the two projections equals at least a full exposure dose. The reticle 210 and the wafer 100 are located in a such manner that the open aperture 216 is proj ected onto the predefined area 346 for an identification symbol which is associated with a projection location on the wafer.
During the next projection the position reticle220 and wafer 100 are located in a such manner that the identification symbol eg. "F" to be formed onto the wafer 100 is projected onto the area 346 which was earlier irradiated by the projection of reticle 210. The size and shape of the projection of the open aperture 216 of reticle 210 on the area 346 of the wafer 100 is such that only one identification symbol can be fitted in. In this particular example this is the letter "F" which is associated with the projection area 102 (FIG.1).
For a better understanding of the arrangement of the reticle with the area identification symbols and the wafer FIG. 5 shows the fragmentary plan view of the reticle 502 and the wafer 506 with the earlier proj ected but undeveloped image of open aperture 508. In the area 102 (FIG.1) all dies are labeled by the same identification symbols "F". This symbol is formed by projection of the reticle 502 with identification symbols in such manner that during proj ection the reticle 502 letter "F" overlaps with the previous irradiated area 530 onto the photosensitive coating of the wafer.
In the area 104 (FIG.l) all dies are labeled by the same identification symbols "B". This symbol is formed by projection of the reticle with identification symbols in such manner that during proj ection the reticle 502 letter "B" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
In the area 106 (FIG.1) all dies are labeled by the same identification symbols "A". This symbol is formed by projection of the reticle with identification symbols in such manner that during projection the reticle 502 letter "A" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
In the area 108 (FIG.1) all dies are labeled by the same identification symbols "E". This symbol is formed by projection of the reticle with identification symbols in such manner that during proj ection the reticle 502 letter "E" overlaps with the previous irradiated area onto the photosensitive coating of the wafer.
As a result of the overlapping said overlapped area receives at least a full exposure dose and can be developed further.
Refernng now to FIG. 6, there is a schematically shown method of forming a layer with a pattern on the wafer surface by the separate projection of two reticles during the manufacture of semiconductor devices by a step-and-repeat type apparatus according to one embodiment of the present invention.
FIG. 6, the case that an image which size is the same as the pattern formed on a reticle is transmitted to the surface of the wafer will be described in order to understand a method of forming a photoresist pattern. In another embodiment, the size of image on the reticle can be enlarged up to 10 times bigger than the image being forming onto the wafer.
In the present embodiment a lithographic process is being shown in the attached drawings as a positive.
During the first exposure, light 600 is irradiated onto a separate projection reticle 620. The reticle 620 used in this embodiment has a projection pattern 622 consisting of a light-absorbing material, for example, chromium, which is formed on the underside of, for example, a transparent basic glass plate 619 . Light passed through the reticle 620 is partially interrupted by the projection pattern 622 . Light passed through the reticle 620 is focused by a lens 625, and thus is irradiated onto a semiconductor wafer 630. On the upper surface of the wafer 630, a photoresist film 631 is applied. By the irradiation of said light 600, the photoresist coating 131 is exposed corresponding to the projection pattern formed on the reticle 620. Thus, a desired pattern can be projected onto the wafer 130.
The dose of exposure of the first reticle has to be at least 10% and no more than 90% full exposure dose. Therein the full dose is defined as the dose required to activate the photoactive compound in the resist coating 631of a wafer 630 so that the photosensitive polymer becomes fully soluble in the developer solution.
During the second exposure, light 600 is irradiated onto a projection reticle 602. The reticle 602 used in this embodiment has a projection pattern 622 consisting of a light-absorbing material, for example, chromium, which is formed on the underside of, for example, a transparent basic glass plate 619. Light passed through the reticle 620 is partially interrupted by the projection pattern 622. Light passed through the reticle 620 is focused by a lens 125, and thus is irradiated onto said semiconductor wafer 630.. By the irradiation of said light, the photo-resist film is exposed corresponding to the projection pattern formed on the reticle 620. Thus, a desired pattern can be proj ected onto said wafer 630. The dose of exposure have to be at least 10% and less than 90% of a full exposure dose.
5 The total exposure dose being projected into the photoresist by the abovementioned two reticles 602 and 620 separate projections has to be greater than a full exposure dose.
As a result of the two reticles 602, 620 exposure onto the photoresist coating 631, the wafer surface (630) areas receive three different quantities of light radiation. The photoresist coating 631 thus contains areas 634 which receives a full exposure, areas 636 receives half 10 of exposure dose, and area 632 does not receive any exposure dose.
After developing the wafer 630 with the radiated photoresist coating 631 on the wafer surface, the only areas that remain are those receiving less than the full exposure dose. The result is shown in FIG. 6 wherein the wafer 630 has remaining areas 642.
Ordinary developers can be used for the above described method, but the best result requires the use of a high contrast developer. FIG 4 depicts a graph of functional dependence wherein resist thickness (axis 412) is plotted against required exposure dose (axis 414) for a positive lithographic process. The slope 418 a portion of curve 410 and the more steep by slope a portion 416 of curve 410 are associated with the types developers used. The high contrast developers provide a steep curve portion 416 while an ordinary developer provides the less steeply sloped curve 418.
The above described method of forming a pattern on a wafer surface by projections at least three reticles in present embodiment be used for the die labeling during manufacturing semiconductor devices without limiting other areas of semiconductor manufacturing, including a negative lithographic process.
As a result of the two reticles 602, 620 exposure onto the photoresist coating 631, the wafer surface (630) areas receive three different quantities of light radiation. The photoresist coating 631 thus contains areas 634 which receives a full exposure, areas 636 receives half 10 of exposure dose, and area 632 does not receive any exposure dose.
After developing the wafer 630 with the radiated photoresist coating 631 on the wafer surface, the only areas that remain are those receiving less than the full exposure dose. The result is shown in FIG. 6 wherein the wafer 630 has remaining areas 642.
Ordinary developers can be used for the above described method, but the best result requires the use of a high contrast developer. FIG 4 depicts a graph of functional dependence wherein resist thickness (axis 412) is plotted against required exposure dose (axis 414) for a positive lithographic process. The slope 418 a portion of curve 410 and the more steep by slope a portion 416 of curve 410 are associated with the types developers used. The high contrast developers provide a steep curve portion 416 while an ordinary developer provides the less steeply sloped curve 418.
The above described method of forming a pattern on a wafer surface by projections at least three reticles in present embodiment be used for the die labeling during manufacturing semiconductor devices without limiting other areas of semiconductor manufacturing, including a negative lithographic process.
Claims (2)
1. A method of compact chip labelling using stepper technology as substantially described.
2. A method of forming an image on a wafer surface by transferring patterns from a plurality of reticles into a photosensitive coating on a wafer surface during the manufacture of integrated circuits as substantially described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002320612A CA2320612A1 (en) | 2000-09-21 | 2000-09-21 | Compact chip labelling using stepper technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002320612A CA2320612A1 (en) | 2000-09-21 | 2000-09-21 | Compact chip labelling using stepper technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2320612A1 true CA2320612A1 (en) | 2002-03-21 |
Family
ID=4167207
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002320612A Abandoned CA2320612A1 (en) | 2000-09-21 | 2000-09-21 | Compact chip labelling using stepper technology |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2320612A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1286219A2 (en) * | 2001-08-09 | 2003-02-26 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1291722A2 (en) * | 2001-09-05 | 2003-03-12 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1589578A1 (en) * | 2004-04-19 | 2005-10-26 | STMicroelectronics S.r.l. | Method and structures for indexing dice |
-
2000
- 2000-09-21 CA CA002320612A patent/CA2320612A1/en not_active Abandoned
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1286219A2 (en) * | 2001-08-09 | 2003-02-26 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1286219A3 (en) * | 2001-08-09 | 2003-11-19 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| US6924090B2 (en) | 2001-08-09 | 2005-08-02 | Neomax Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1291722A2 (en) * | 2001-09-05 | 2003-03-12 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1291722A3 (en) * | 2001-09-05 | 2003-11-19 | Sumitomo Special Metals Co., Ltd. | Method of recording identifier and set of photomasks |
| US6897010B2 (en) | 2001-09-05 | 2005-05-24 | Neomax Co., Ltd. | Method of recording identifier and set of photomasks |
| EP1589578A1 (en) * | 2004-04-19 | 2005-10-26 | STMicroelectronics S.r.l. | Method and structures for indexing dice |
| US7348682B2 (en) | 2004-04-19 | 2008-03-25 | Stmicroelectronics S.R.L. | Method and structures for indexing dice |
| US7491620B2 (en) | 2004-04-19 | 2009-02-17 | Stmicroelectronics S.R.L. | Method and structures for indexing dice |
| US7868474B2 (en) | 2004-04-19 | 2011-01-11 | Stmicroelectronics, S.R.L. | Method and structures for indexing dice |
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