CA2304249A1 - Circuit arrangement and method for forward error correction - Google Patents
Circuit arrangement and method for forward error correction Download PDFInfo
- Publication number
- CA2304249A1 CA2304249A1 CA002304249A CA2304249A CA2304249A1 CA 2304249 A1 CA2304249 A1 CA 2304249A1 CA 002304249 A CA002304249 A CA 002304249A CA 2304249 A CA2304249 A CA 2304249A CA 2304249 A1 CA2304249 A1 CA 2304249A1
- Authority
- CA
- Canada
- Prior art keywords
- unit
- error correction
- forward error
- trn
- transport frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000012937 correction Methods 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims description 10
- 230000005540 biological transmission Effects 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 5
- 230000037431 insertion Effects 0.000 claims description 5
- 101100458361 Drosophila melanogaster SmydA-8 gene Proteins 0.000 claims description 3
- 230000006978 adaptation Effects 0.000 claims 1
- 238000012544 monitoring process Methods 0.000 claims 1
- 102100040496 Collagen alpha-2(VIII) chain Human genes 0.000 description 7
- 101000749886 Homo sapiens Collagen alpha-2(VIII) chain Proteins 0.000 description 7
- 230000001360 synchronised effect Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 2
- 102100040791 Zona pellucida-binding protein 1 Human genes 0.000 description 1
- 101710174294 Zona pellucida-binding protein 1 Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Error Detection And Correction (AREA)
- Time-Division Multiplex Systems (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
In order to allow forward error correction in data transport systems, the data of a transport framework are gathered in error correction blocks and parity check bits are specially provided for that purpose. Such parity check bits are then integrated into a free area in the section overhead of the same error correction block.
Description
SPECIFICATION
CIRCUIT ARRANGEMENT AND METHOD FOR FORWARD ERROR
CORRECTION
s In a synchronous optical network (SONET) or a synchronous digital-hierarchy (SDH) network, data to be transmitted are placed in virtual containers in a payload region of transport frames. Memory locations for operation and maintenance tasks of the transport system are reserved in a part of the transport frame, what is referred to as the section overhead.
to In the synchronous optical SONET, the data transmission rate begins with 51 Mbit/s; in a network with synchronous digital hierarchy, the data transmission rate begins with 155 Mbit/s. The data transmission rate can be increased by a multiple in both networks. Network operators demand low bit error rates even given high data transmission rates.
15 A low bit error rate was hitherto achieved by high-grade optical components and by short transmission links. An increase in the transmission quality and, thus, a reduction of the bit error rate can become possible on the basis of optimization processes in the reception units following a transmission link whereby a forward error correction.
CIRCUIT ARRANGEMENT AND METHOD FOR FORWARD ERROR
CORRECTION
s In a synchronous optical network (SONET) or a synchronous digital-hierarchy (SDH) network, data to be transmitted are placed in virtual containers in a payload region of transport frames. Memory locations for operation and maintenance tasks of the transport system are reserved in a part of the transport frame, what is referred to as the section overhead.
to In the synchronous optical SONET, the data transmission rate begins with 51 Mbit/s; in a network with synchronous digital hierarchy, the data transmission rate begins with 155 Mbit/s. The data transmission rate can be increased by a multiple in both networks. Network operators demand low bit error rates even given high data transmission rates.
15 A low bit error rate was hitherto achieved by high-grade optical components and by short transmission links. An increase in the transmission quality and, thus, a reduction of the bit error rate can become possible on the basis of optimization processes in the reception units following a transmission link whereby a forward error correction.
2 o The invention is based on the object of specifying a circuit arrangement and a method for forward error correction.
This object is achieved by the features of patent claims 1 and 10.
The invention yields the advantage that a reduction of the bit error rate to 10''5 is achieved given a simultaneous increase in the length of the 2 s transmission sections between repeater sections that become necessary.
The invention yields the further advantage that errors can be corrected at any arbitrary location of a transport frame, i.e. even under the parity bits.
The invention yields the further advantage that bungling errors can be 3 o corrected giving bit rates from 622 Mbit/s.
Over and above this, the invention yields the further advantage that only a minimal, computer caused delay occurs in the further-transport of the data to be transmitted, occurring due to the forward error correction.
Further particulars are recited in the subclaims.
s The circuit arrangement and the method can be seen from the following, more detailed explanation of an exemplary embodiment on the basis of drawings.
Shown are:
Figure 1 a portion of a transport system with an involvement of a 1 o forward error correction;
Figure 2 an involvement of forward error correction units connected parallel into a data transmission path;
Figure 3 a division of the transport frame into a section overhead region and a payload region; and 15 Figure 4 the arrangement and allocation of parity bits to line sections within a transport frame.
Figure 1 shows a portion of a synchronous transport system having an involvement of a forward error correction coding unit FECC, of a forward error correction decoding unit FECD with appertaining units. A data editing 2 o by the forward error correction coding unit FECC in a transmitter Sn is a pre-condition for the forward error correction in a receiver unit En with the forward error correction decoding unit FECD. Error correction blocks FBn are formed in the forward error correction coding unit FECC by a block formation unit BSE. Respective data sequences are respectively combined 25 with a check information in the error correction blocks FBn. The check information, which, for example, can be parity bits, are generated according to the criterion of a computer procedure. The data sequence with the attached parity bits has the property of being a whole multiple of a specific number, what is referred to as the generator polynomial. A modulo division 3 o is implemented with the same generator polynomial in the receiver unit En, whereby a transmission error has occurred in the transmitted data when a remainder derived. The value of the remainder in the division given a suitable selection of the generator polynomial yields a clear information about the position of the error in the transmitted data.
After a first multiplexing unit MSTA, the critical units of the transmission unit Sn shown in Figure 1 are a first and second series-s arranged insertion unit E1 B2, E2B1 for inserting B1 and B2 bytes into a transport frame TRn, whereby the B1, B2 bytes are respectively inserted into a transport frame TRn+1 following the transport frame TRn; the forward error correction coding unit FECC with the block formation unit BSE for forming error correction blocks FBn in a transport frame TRn; a first feedback branch 1 o having a first check unit UE1 B2 for modification of the B2 bytes; a scrambler unit SCR; a second feedback branch having a formation unit BB1; an interleaving unit INTL for multiplexing data sequences conducted parallel to form a data stream; a physical, first interface unit SPI; and a transmission path S that can, for example, be formed of a plurality of optical fiber lines.
15 The following units are arranged in the receiver En: a physical, second interface unit ESPI for the reception of, for example, optically transmitted data; a frame synchronization unit RS for frame synchronization; a de-interleaving unit DIL for the de-interleaving of the data stream; a second check unit UE2B1 for checking the B1 byte; a descrambler unit DESCR; a 2 o forward error correction decoding unit FECD for correcting individual errors, including parity bits and B1, B2 bytes within error correction blocks FB1,...,FB9 that are formed in a transport frame TRn; and a further check unit UE that is composed of a scrambler SCRUE that is composed of a scrambler unit SCRUE and of a third check unit UE3B1. The result of the 2s second and third check unit UE2B1, UE3B1 is forwarded to a system management SM that is not shown here. The forward error correction decoding unit FECD is followed by a second multiplexing unit MSTB for checking the B2 byte and for multiplexing the data.
Following the transmission-side termination of a multiplex section by 3 o the first multiplexer unit MSTA, the modified B2 bytes that belong to a transport frame TRn are inserted into a following transport frame TRn+1 by the first insertion unit E1 B2. The block forming unit BSE in the forward error correction coding unit FECC determines error correction blocks FBn for the transport frame GRn, calculates the appertaining parity bits and stores them in the section overhead SOH of the transport frame TRn. Subsequently, a check of the B2 byte is implemented for the transport frame TRn in the first s check unit UE1 B2 and this is inserted in the following transport frame TRn+1.
The data of the transport frame TRn are superimposed with a pseudo random data sequence in the scrambler unit SCR. The B1 byte is then formed in the formation unit BB1 for the data in the transport frame TRn that are superimposed with a pseudo-random data sequence and are 1 o subsequently inserted into the following transport frame TRn+1 in the second insertion unit E2B1.
A plurality of transmission units S1,...Sn are to be arranged parallel for processing a data stream with a higher data rate. In order to be able to transmit the data conducted parallel to a receiver unit E1,....,En, these are 1 s converted into a serial data stream by multiplexers in the interleaving unit INTL. The physical, first interface SPI adapts the serial data stream to the physical demands of a transmission line S or, respectively, of a transmission channel.
The transmitted data are converted into a serial data stream in the 2 o receiver En. Due to quality loss and disturbances on the transmission path S, the received data can deviate from the transmission-side data. A frame synchronization unit RS for the frame synchronization enables a re-organization and conversion of the data stream in the transport TRn. The data stream is converted into a data stream several bits wide by the D-2 s interleaving unit DIL. Bit errors of the B1 byte for each transport frame TRn are determined by a first check unit UEB1 and are forwarded to the system management SM. The bit-pseudo-random sequence superimposed on the data in the transmission unit Sn is in turn removed in the descrambler unit DESCR. Subsequently, a data are forwarded to the forward error correction 3 o decoding unit FECD. Potential bit errors are recognized by the procedure set forth at the outset and are corrected in the forward error correction decoding unit FECD. Errors at a random location of the transport frame TRn can be recognized. The correct data in the transport frame TRn are subjected to a renewed B1 check in the unit UE. Following a further scrambler unit SCRUE, the data are supplied to a third check unit UE3B1 in the unit UE.
Following the receiver En, the outgoing data (DB) are forwarded to the s second multiplexes MSTB.
Figure 2 shows a parallel circuit of a plurality of forward error correction coding units FECC1,....,FECCn and forward error correction decoding units FECD1,...,FECDn with the appertaining scrambler units SRC1,...,SCRCn at the transmitter side and the descrambler units to DESCR1,...,DESCRn at the reception side. The parallel connection of transmission units Sn can be interpreted - at least logically - as a bit-by-bit demultiplexing. The data stream within a transmission unit Sn is clocked at 155 MHz.
Given a data transmission rate of 622 MBit/s, for transmission units S1,...,S4 and four reception units E1,...,E4 are to be arranged in parallel.
Given a data transmission rate of 10 GBit/s, 64 transmission units S1,...,S64 and 64 reception units E1,...,E64 are required. 64 [sic] errors that occur sequentially given a 10 G-bit data carry [sic] rate can be recognized and corrected given a data stream conducted parallel by bits. A division of the 2 o data stream can, as indicated, ensue either bit-by-bit or byte-by-byte.
The concept shown in Figure 2 can be inserted in a simple way, as indicated in Figure 1.
The division of a transport TRn is reproduced in Figure 3. As initially set forth, the transport TRn, which is divided into rows Zn and columns SPn, 2 s is subdivided into the section overhead SOH and into the payload region PL.
By definition, specific line sections are reserved in the section overhead SOH
for an expanded operation, administration and maintenance region. In addition to fixed, pre-occupied memory locations, regions for an operator for free disposition are reserved in the section overhead SOH. These regions 3 o are indicated in Figure 3 with hatched surfaces or, respectively, surfaces that are marked light. The section overhead SOH extends from column Sp1 through column Sp72. The data to be transmitted are stored in the transport frame TRn in the region beginning from column Sp73 through column Sp2160. The transport frame TRn is divided into nine rows Z1,...,Z9.
The check information, particularly the parity bits PBn, required for the implementation of the forward error correction are stored in the free areas of s the section overhead SOH. The parity information requires 12 bits per error correction block FBn.
Figure 4 shows the division of a transport frame TRn into rows Z1,...,Z9 and columns SPn,....,Sp2160. Row sections are continea to error correction blocks FB1,..,FB9 for the determination of the parity bit FBn. The 1 o error correction block FB2, FBS, FB6, FB7 and FB8 respectively extends from column Sp73 of a row Zn up to the column Sp72 of the following row Zn+1. The parity bits PBn for the error correction blocks FB2, FBS, FB6, FB7, and FB8 are respectively arranged at the block end of column Sp61 and column Sp72 of the error correction block FB2, FB, FB6, FB7 and FBB.
15 The error correction block FB1, extends from row Z1, column Sp62 [sic] up to the following row Z2, column Sp72. The error correction block FB1 is interrupted in row Z2 from column Sp37 [sic] through Sp49. This region is allocated to the error correction block FB9. The parity bits PB9 of the error correction block FB9 are stored in it. The parity bits Pb1 of the error 2 o correction block FB1 are arranged in row Z2 from column Sp61 through column Sp72. The division of the error correction block FB4 corresponds to that of the error correction block FB1. The error correction block FB4 is arranged in row Z4 and Z5. The parity bits PB3 of the error correction block FB3 are arranged in row Z5 from column Sp38 and [sic] Sp49. The error 2s correction block division of the error correction block FB9 comprises the same division pattern as the error correction block FB3. The error correction block FB9 begins in row Z9, column Sp73 and continues in row Z1, column Sp60 and in row Z2, column Sp37 through column Sp49. The parity bit PB9 for the error correction block FB9 are stored in row Z2 from column Sp37 3 o through column Sp49.
Given a division of the transport frame TRn into error correction blocks FB1,...,FB9, parity bits PB1,....PB9 can be calculated block-by-block at the transmission side with, for example, a maximum of two computer units that can be realized with little outlay. The same computing outlay at the reception side enables a fast and dependable localization and illumination of errors in the transport frame TRn.
This object is achieved by the features of patent claims 1 and 10.
The invention yields the advantage that a reduction of the bit error rate to 10''5 is achieved given a simultaneous increase in the length of the 2 s transmission sections between repeater sections that become necessary.
The invention yields the further advantage that errors can be corrected at any arbitrary location of a transport frame, i.e. even under the parity bits.
The invention yields the further advantage that bungling errors can be 3 o corrected giving bit rates from 622 Mbit/s.
Over and above this, the invention yields the further advantage that only a minimal, computer caused delay occurs in the further-transport of the data to be transmitted, occurring due to the forward error correction.
Further particulars are recited in the subclaims.
s The circuit arrangement and the method can be seen from the following, more detailed explanation of an exemplary embodiment on the basis of drawings.
Shown are:
Figure 1 a portion of a transport system with an involvement of a 1 o forward error correction;
Figure 2 an involvement of forward error correction units connected parallel into a data transmission path;
Figure 3 a division of the transport frame into a section overhead region and a payload region; and 15 Figure 4 the arrangement and allocation of parity bits to line sections within a transport frame.
Figure 1 shows a portion of a synchronous transport system having an involvement of a forward error correction coding unit FECC, of a forward error correction decoding unit FECD with appertaining units. A data editing 2 o by the forward error correction coding unit FECC in a transmitter Sn is a pre-condition for the forward error correction in a receiver unit En with the forward error correction decoding unit FECD. Error correction blocks FBn are formed in the forward error correction coding unit FECC by a block formation unit BSE. Respective data sequences are respectively combined 25 with a check information in the error correction blocks FBn. The check information, which, for example, can be parity bits, are generated according to the criterion of a computer procedure. The data sequence with the attached parity bits has the property of being a whole multiple of a specific number, what is referred to as the generator polynomial. A modulo division 3 o is implemented with the same generator polynomial in the receiver unit En, whereby a transmission error has occurred in the transmitted data when a remainder derived. The value of the remainder in the division given a suitable selection of the generator polynomial yields a clear information about the position of the error in the transmitted data.
After a first multiplexing unit MSTA, the critical units of the transmission unit Sn shown in Figure 1 are a first and second series-s arranged insertion unit E1 B2, E2B1 for inserting B1 and B2 bytes into a transport frame TRn, whereby the B1, B2 bytes are respectively inserted into a transport frame TRn+1 following the transport frame TRn; the forward error correction coding unit FECC with the block formation unit BSE for forming error correction blocks FBn in a transport frame TRn; a first feedback branch 1 o having a first check unit UE1 B2 for modification of the B2 bytes; a scrambler unit SCR; a second feedback branch having a formation unit BB1; an interleaving unit INTL for multiplexing data sequences conducted parallel to form a data stream; a physical, first interface unit SPI; and a transmission path S that can, for example, be formed of a plurality of optical fiber lines.
15 The following units are arranged in the receiver En: a physical, second interface unit ESPI for the reception of, for example, optically transmitted data; a frame synchronization unit RS for frame synchronization; a de-interleaving unit DIL for the de-interleaving of the data stream; a second check unit UE2B1 for checking the B1 byte; a descrambler unit DESCR; a 2 o forward error correction decoding unit FECD for correcting individual errors, including parity bits and B1, B2 bytes within error correction blocks FB1,...,FB9 that are formed in a transport frame TRn; and a further check unit UE that is composed of a scrambler SCRUE that is composed of a scrambler unit SCRUE and of a third check unit UE3B1. The result of the 2s second and third check unit UE2B1, UE3B1 is forwarded to a system management SM that is not shown here. The forward error correction decoding unit FECD is followed by a second multiplexing unit MSTB for checking the B2 byte and for multiplexing the data.
Following the transmission-side termination of a multiplex section by 3 o the first multiplexer unit MSTA, the modified B2 bytes that belong to a transport frame TRn are inserted into a following transport frame TRn+1 by the first insertion unit E1 B2. The block forming unit BSE in the forward error correction coding unit FECC determines error correction blocks FBn for the transport frame GRn, calculates the appertaining parity bits and stores them in the section overhead SOH of the transport frame TRn. Subsequently, a check of the B2 byte is implemented for the transport frame TRn in the first s check unit UE1 B2 and this is inserted in the following transport frame TRn+1.
The data of the transport frame TRn are superimposed with a pseudo random data sequence in the scrambler unit SCR. The B1 byte is then formed in the formation unit BB1 for the data in the transport frame TRn that are superimposed with a pseudo-random data sequence and are 1 o subsequently inserted into the following transport frame TRn+1 in the second insertion unit E2B1.
A plurality of transmission units S1,...Sn are to be arranged parallel for processing a data stream with a higher data rate. In order to be able to transmit the data conducted parallel to a receiver unit E1,....,En, these are 1 s converted into a serial data stream by multiplexers in the interleaving unit INTL. The physical, first interface SPI adapts the serial data stream to the physical demands of a transmission line S or, respectively, of a transmission channel.
The transmitted data are converted into a serial data stream in the 2 o receiver En. Due to quality loss and disturbances on the transmission path S, the received data can deviate from the transmission-side data. A frame synchronization unit RS for the frame synchronization enables a re-organization and conversion of the data stream in the transport TRn. The data stream is converted into a data stream several bits wide by the D-2 s interleaving unit DIL. Bit errors of the B1 byte for each transport frame TRn are determined by a first check unit UEB1 and are forwarded to the system management SM. The bit-pseudo-random sequence superimposed on the data in the transmission unit Sn is in turn removed in the descrambler unit DESCR. Subsequently, a data are forwarded to the forward error correction 3 o decoding unit FECD. Potential bit errors are recognized by the procedure set forth at the outset and are corrected in the forward error correction decoding unit FECD. Errors at a random location of the transport frame TRn can be recognized. The correct data in the transport frame TRn are subjected to a renewed B1 check in the unit UE. Following a further scrambler unit SCRUE, the data are supplied to a third check unit UE3B1 in the unit UE.
Following the receiver En, the outgoing data (DB) are forwarded to the s second multiplexes MSTB.
Figure 2 shows a parallel circuit of a plurality of forward error correction coding units FECC1,....,FECCn and forward error correction decoding units FECD1,...,FECDn with the appertaining scrambler units SRC1,...,SCRCn at the transmitter side and the descrambler units to DESCR1,...,DESCRn at the reception side. The parallel connection of transmission units Sn can be interpreted - at least logically - as a bit-by-bit demultiplexing. The data stream within a transmission unit Sn is clocked at 155 MHz.
Given a data transmission rate of 622 MBit/s, for transmission units S1,...,S4 and four reception units E1,...,E4 are to be arranged in parallel.
Given a data transmission rate of 10 GBit/s, 64 transmission units S1,...,S64 and 64 reception units E1,...,E64 are required. 64 [sic] errors that occur sequentially given a 10 G-bit data carry [sic] rate can be recognized and corrected given a data stream conducted parallel by bits. A division of the 2 o data stream can, as indicated, ensue either bit-by-bit or byte-by-byte.
The concept shown in Figure 2 can be inserted in a simple way, as indicated in Figure 1.
The division of a transport TRn is reproduced in Figure 3. As initially set forth, the transport TRn, which is divided into rows Zn and columns SPn, 2 s is subdivided into the section overhead SOH and into the payload region PL.
By definition, specific line sections are reserved in the section overhead SOH
for an expanded operation, administration and maintenance region. In addition to fixed, pre-occupied memory locations, regions for an operator for free disposition are reserved in the section overhead SOH. These regions 3 o are indicated in Figure 3 with hatched surfaces or, respectively, surfaces that are marked light. The section overhead SOH extends from column Sp1 through column Sp72. The data to be transmitted are stored in the transport frame TRn in the region beginning from column Sp73 through column Sp2160. The transport frame TRn is divided into nine rows Z1,...,Z9.
The check information, particularly the parity bits PBn, required for the implementation of the forward error correction are stored in the free areas of s the section overhead SOH. The parity information requires 12 bits per error correction block FBn.
Figure 4 shows the division of a transport frame TRn into rows Z1,...,Z9 and columns SPn,....,Sp2160. Row sections are continea to error correction blocks FB1,..,FB9 for the determination of the parity bit FBn. The 1 o error correction block FB2, FBS, FB6, FB7 and FB8 respectively extends from column Sp73 of a row Zn up to the column Sp72 of the following row Zn+1. The parity bits PBn for the error correction blocks FB2, FBS, FB6, FB7, and FB8 are respectively arranged at the block end of column Sp61 and column Sp72 of the error correction block FB2, FB, FB6, FB7 and FBB.
15 The error correction block FB1, extends from row Z1, column Sp62 [sic] up to the following row Z2, column Sp72. The error correction block FB1 is interrupted in row Z2 from column Sp37 [sic] through Sp49. This region is allocated to the error correction block FB9. The parity bits PB9 of the error correction block FB9 are stored in it. The parity bits Pb1 of the error 2 o correction block FB1 are arranged in row Z2 from column Sp61 through column Sp72. The division of the error correction block FB4 corresponds to that of the error correction block FB1. The error correction block FB4 is arranged in row Z4 and Z5. The parity bits PB3 of the error correction block FB3 are arranged in row Z5 from column Sp38 and [sic] Sp49. The error 2s correction block division of the error correction block FB9 comprises the same division pattern as the error correction block FB3. The error correction block FB9 begins in row Z9, column Sp73 and continues in row Z1, column Sp60 and in row Z2, column Sp37 through column Sp49. The parity bit PB9 for the error correction block FB9 are stored in row Z2 from column Sp37 3 o through column Sp49.
Given a division of the transport frame TRn into error correction blocks FB1,...,FB9, parity bits PB1,....PB9 can be calculated block-by-block at the transmission side with, for example, a maximum of two computer units that can be realized with little outlay. The same computing outlay at the reception side enables a fast and dependable localization and illumination of errors in the transport frame TRn.
Claims (12)
1. Circuit arrangement for forward error correction in a transmission of data (DA), comprising a forward error correction coding unit (FECC) arranged in a transmission unit (Sn) and a forward error correction decoding unit (FECD) arranged in a receiver unit (En) corresponding to the transmission unit (Sn), characterized in that the forward error correction coding unit (FECC) and the forward error correction decoding unit (FECD) respectively comprise a block forming unit (BSE) for the formation of error correction blocks (FBn) in a transport frame (TRn), whereby data of the payload and section overhead area of the transport frame (TRn) are combined in the error correction blocks.
2. Circuit arrangement according to claim 1, characterized in that the block forming unit (BSE) forms error correction blocks (FBn) that comprise at least the row length of the transport frame (TRn).
3. Circuit arrangement according to claim 1 or 2, characterized in that the block forming unit (BSE) forms error correction blocks (FBn) that extend over at least two sub-row regions (Z1,....Zj+1) of the transport frame (TRn).
4. Circuit arrangement according to one of the preceding claims, characterized in that the forward error correction coding unit (FECC) determines a check information for the error correction blocks (FBn) and stores the check information (PB(n)) for an error correction block (FBn) therein.
5. Circuit arrangement according to one of the preceding claims, characterized in that a scrambler unit (SRC) for addition of a pseudo-random data sequence onto the data sequence of the transport frame (TRn) output by the forward error correction coding unit (FECC) is arranged in the transmission unit (Sn) following the forward error correction coding unit (FECC);
a first check unit (UE1B2) for B2-byte checking of the transport frame (TRn) is arranged following the forward error correction coding unit (FECC);
a formation unit (BB1) for forming a B-1 byte for the transport frame (TRn) is arranged following the scrambler unit (SCR); and a first insertion unit (E1B2) for inserting the checked B2-byte and a second insertion unit (E2B1) for inserting the B1-byte that has been formed into a respective transport frame (TRn+1) following the transport frame (TRn) is arranged preceding the forward error correction coding unit (FECC).
a first check unit (UE1B2) for B2-byte checking of the transport frame (TRn) is arranged following the forward error correction coding unit (FECC);
a formation unit (BB1) for forming a B-1 byte for the transport frame (TRn) is arranged following the scrambler unit (SCR); and a first insertion unit (E1B2) for inserting the checked B2-byte and a second insertion unit (E2B1) for inserting the B1-byte that has been formed into a respective transport frame (TRn+1) following the transport frame (TRn) is arranged preceding the forward error correction coding unit (FECC).
6. Circuit arrangement according to one of the preceding claims, characterized in that an output of the scrambler unit (SRC) is connected to an input of a second check unit (UE2B1) for checking the B1-byte in the receiver unit (En), being connected thereto via - an interleaving unit (INTL) for multiplexing parallel data sequences to form a data stream;
- a physical, first interface unit (SPI) for adaptation of the data stream to a transmission path (S);
- a physical, second interface unit (ESPI) for reception of the transmitted data; and - a frame synchronization unit (RS) for demultiplexing the data stream.
- a physical, first interface unit (SPI) for adaptation of the data stream to a transmission path (S);
- a physical, second interface unit (ESPI) for reception of the transmitted data; and - a frame synchronization unit (RS) for demultiplexing the data stream.
7. Circuit arrangement according to one of the preceding claims, characterized in that an output of the second check unit (UE2B1) is connected to a descrambler unit (DESCR) and the latter is connected to the forward error correction decoding unit (FECD); in that a further check unit (UE) for checking the B1-byte of the transport frame (TRn) forwarded from the forward error correction decoding unit (FECD) is provided following the forward error correction decoder unit (FECD).
8. Circuit arrangement according to one of the preceding claims, characterized in that a system management (SM) is provided for monitoring the B1-byte checking.
9. Circuit arrangement according to one of the preceding claims, characterized in that the incoming data (DA) are conducted to a first multiplexes (MSTA) preceding the transmission unit (Sn), and the outgoing data (DB) are conducted to a second multiplexing unit (MSTB) following the reception unit (En).
10. Method for forward error correction in a transmission of data (DA), comprising a forward error correction coding unit (FECC) arranged in a transmission unit (SEn) and a forward error correction decoding unit (FECD) arranged in a reception unit (En) corresponding to the transmission unit (SEn), characterized in that error correction blocks (FBn) are formed from the data transported in the transport frame (TRn), being formed in the forward error correction coding unit (FECC) and the forward error correction decoding unit (FECD), whereby data of the payload and section overhead area of the transport frame (TRn) are combined in the error correction blocks.
11. Method according to claim 10, characterized in that the error correction blocks (FBn) comprise at least a row length of a transport frame (TRn).
12. Method according to claim 11, characterized in that the error correction blocks (FBn) extend over at least two sub-row areas (Z1,...,Zj+1) of the transport frame (TRn).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE1997140935 DE19740935A1 (en) | 1997-09-17 | 1997-09-17 | Circuitry and method for forward error correction |
| DE19740935.0 | 1997-09-17 | ||
| PCT/DE1998/002743 WO1999014884A2 (en) | 1997-09-17 | 1998-09-16 | Circuit and method for forward error correction in a digital synchronous hierarchical system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2304249A1 true CA2304249A1 (en) | 1999-03-25 |
Family
ID=7842677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002304249A Abandoned CA2304249A1 (en) | 1997-09-17 | 1998-09-16 | Circuit arrangement and method for forward error correction |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2001517019A (en) |
| CA (1) | CA2304249A1 (en) |
| DE (1) | DE19740935A1 (en) |
| WO (1) | WO1999014884A2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6683855B1 (en) * | 1998-08-31 | 2004-01-27 | Lucent Technologies Inc. | Forward error correction for high speed optical transmission systems |
| DE102008004728A1 (en) | 2008-01-16 | 2009-07-23 | Henkel Ag & Co. Kgaa | Phosphated steel sheet and method for producing such a sheet |
-
1997
- 1997-09-17 DE DE1997140935 patent/DE19740935A1/en not_active Ceased
-
1998
- 1998-09-16 JP JP2000512306A patent/JP2001517019A/en not_active Withdrawn
- 1998-09-16 CA CA002304249A patent/CA2304249A1/en not_active Abandoned
- 1998-09-16 WO PCT/DE1998/002743 patent/WO1999014884A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO1999014884A2 (en) | 1999-03-25 |
| DE19740935A1 (en) | 1999-04-08 |
| WO1999014884A3 (en) | 1999-06-17 |
| JP2001517019A (en) | 2001-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2278820C (en) | Forward error correction for high speed optical transmission systems | |
| EP3013008B1 (en) | Transmitting data traffic in a communication network | |
| EP0874487B1 (en) | Transparent transport in a telecommunication system | |
| EP0874488B1 (en) | Transparent multiplexer/demultiplexer | |
| US7024616B2 (en) | Method for encoding/decoding error correcting code, transmitting apparatus and network | |
| EP2109239B1 (en) | Method of communicating data in communication systems | |
| EP1777845B1 (en) | Service protecting method for optical transmission network and node device | |
| CA2131265C (en) | Out-of-band embedded overhead architecture for a transmission network | |
| US7573871B2 (en) | Apparatus for processing OTN frames utilizing an efficient forward error correction | |
| US7953095B2 (en) | Transmission system and transmission method | |
| CA2304249A1 (en) | Circuit arrangement and method for forward error correction | |
| US7526197B2 (en) | Utilizing the protecting bandwidth in a SONET network | |
| US7002957B2 (en) | Method of transporting frames of information between parts of a network through an intermediate network | |
| US7126943B2 (en) | Method and apparatus for interfacing a parallel connection | |
| FI98771C (en) | A method for examining the operation of a network element of a data transmission network | |
| US20060153231A1 (en) | Method for transmitting data signals by means of virtually linked partial signals via synchronous data networks | |
| Henderson | Forward Error Correction in Optical Network | |
| EP3247058B1 (en) | Transmission circuit, reception circuit, optical transfer system, and method for transmitting multiframes | |
| CN1988470B (en) | Service protecting method and device | |
| Kartalopoulos et al. | The Optical Transport Network |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Dead |