CA2217262C - Enhanced integrated rate based available bit rate scheduler - Google Patents
Enhanced integrated rate based available bit rate scheduler Download PDFInfo
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- CA2217262C CA2217262C CA002217262A CA2217262A CA2217262C CA 2217262 C CA2217262 C CA 2217262C CA 002217262 A CA002217262 A CA 002217262A CA 2217262 A CA2217262 A CA 2217262A CA 2217262 C CA2217262 C CA 2217262C
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- profile
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Abstract
An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network in which each cell is characterized by a virtual circuit communication channel and in which each virtual circuit is characterized by one or more profiles. Each profile has a group of sub-profiles, with each sub-profile having a unique bandwidth allocation component. The scheduler incorporates a profile queue buffer for receiving, pairing and storing the profiles and sub-profiles and, a link list processor coupled to the profile queue buffer to receive the profile, sub-profile pairs. The link list processor detects null profile, sub-profile pairs in the buffer and, over-write them with a selected one of the virtual circuit profile, sub-profile pairs. A valid pending register of length p bits, and a memory are coupled to the link list processor. The memory stores pointers to link lists of virtual circuits associated with each of the profile, sub-profile pairs received by the link list processor. The pointers comprise, for each of the link lists, a head pointer to a first entry in the link list and a next pointer to a virtual circuit in the link list last associated by the link list processor with one of the profile, sub-profile pairs.
Claims (15)
1. An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network, each of said cells characterized by a virtual circuit communication channel, said scheduler comprising:
a. an MCR scheduler for receiving MCR-rate virtual circuits requiring m;n;mllm cell rate transmission service through said network and for outputting said MCR-rate virtual circuits at a constant bit rate; and, b. an ABR' scheduler for receiving ABR-rate virtual circuits requiring available bit rate transmission service through said network and for outputting said ABR-rate virtual circuits at an effective allowed cell rate ACR'i = ACR i-MCR i where 0 ~ i ~ (n-1) and n is the total number of said virtual circuits.
a. an MCR scheduler for receiving MCR-rate virtual circuits requiring m;n;mllm cell rate transmission service through said network and for outputting said MCR-rate virtual circuits at a constant bit rate; and, b. an ABR' scheduler for receiving ABR-rate virtual circuits requiring available bit rate transmission service through said network and for outputting said ABR-rate virtual circuits at an effective allowed cell rate ACR'i = ACR i-MCR i where 0 ~ i ~ (n-1) and n is the total number of said virtual circuits.
2. An available bit rate scheduler as defined in claim 1, further comprising a first arbitrator coupled to said MCR scheduler and to said ABR' scheduler to receive said MCR-rate virtual circuits and said ABR-rate virtual circuits, said first arbitrator outputting said MCR-rate virtual circuits and said ABR-rate virtual circuits in merged priority sequence by outputting any of said MCR-rate virtual circuits received from said MCR scheduler before outputting any of said ABR-rate virtual circuits received from said ABR' scheduler.
3. An available bit rate scheduler as defined in claim 2, said first arbitrator further comprising a buffer for storing said ABR-rate virtual circuits received from said ABR' scheduler while said first arbitrator outputs said MCR-rate virtual circuits received from said MCR scheduler.
4. An available bit rate scheduler as defined in claim 3, wherein said buffer is of a size sufficient to store two of said ABR-rate virtual circuits received from said ABR' scheduler while said first arbitrator outputs said MCR-rate virtual circuits received from said MCR scheduler.
5. An available bit rate scheduler as defined in claim 2, further comprising a second arbitrator coupled to said first arbitrator to receive said MCR-rate virtual circuits and said ABR-rate virtual circuits output by said first arbitrator, and coupled to a UBR source of UBR-rate virtual circuits requiring unspecified bit rate transmission service through said network, said second arbitrator further comprising:
a. a first buffer for receiving and storing said MCR-rate and ABR-rate virtual circuits received from said first arbitrator;
b. a second buffer for receiving and storing said UBR-rate virtual circuits received from said UBR
source;
c. first programmable means for outputting said MCR-rate and ABR-rate virtual circuits from said first buffer at a user-programmable priority rate between 0% and 100%; and, d. second programmable means for outputting said UBR-rate virtual circuits from said second buffer at a priority rate of 100% - said user-programmable priority rate.
a. a first buffer for receiving and storing said MCR-rate and ABR-rate virtual circuits received from said first arbitrator;
b. a second buffer for receiving and storing said UBR-rate virtual circuits received from said UBR
source;
c. first programmable means for outputting said MCR-rate and ABR-rate virtual circuits from said first buffer at a user-programmable priority rate between 0% and 100%; and, d. second programmable means for outputting said UBR-rate virtual circuits from said second buffer at a priority rate of 100% - said user-programmable priority rate.
6. An available bit rate scheduler as defined in claim 5, wherein:
a. said first buffer is a first-in-first-out buffer of a size sufficient to store two of said MCR-rate or ABR-rate virtual circuits received from said first arbitrator; and, b. said second buffer is a first-in-first-out buffer of a size sufficient to store two of said UBR-rate virtual circuits received from said UBR
source.
a. said first buffer is a first-in-first-out buffer of a size sufficient to store two of said MCR-rate or ABR-rate virtual circuits received from said first arbitrator; and, b. said second buffer is a first-in-first-out buffer of a size sufficient to store two of said UBR-rate virtual circuits received from said UBR
source.
7. An available bit rate scheduler for asynchronous transfer mode communication of a plurality of cells over a communication network, each of said cells characterized by a virtual circuit communication channel, each of said virtual circuits characterized by one or more profiles, said profiles each comprising a group of sub-profiles, each of said sub-profiles having a unique bandwidth allocation component, said scheduler comprising:
a. a profile queue buffer for receiving, pairing and storing said profiles and said sub-profiles;
b. a link list processor coupled to said profile queue buffer to receive said profile, sub-profile pairs, said link list processor further comprising:
i. means for detecting a null profile, sub-profile pair in said buffer; and, ii. means for over-writing said null profile, sub-profile pair with a selected one of said virtual circuit profile, sub-profile pairs.
a. a profile queue buffer for receiving, pairing and storing said profiles and said sub-profiles;
b. a link list processor coupled to said profile queue buffer to receive said profile, sub-profile pairs, said link list processor further comprising:
i. means for detecting a null profile, sub-profile pair in said buffer; and, ii. means for over-writing said null profile, sub-profile pair with a selected one of said virtual circuit profile, sub-profile pairs.
8. An available bit rate scheduler as defined in claim 7, further comprising a valid pending register of length p bits, and memory means coupled to said link list processor, said memory means for storing pointers to link lists of virtual circuits associated with each of said profile, sub-profile pairs received by said link list processor, said pointers further comprising, for each of said link lists, a head pointer to a first entry in said link list and a next pointer to a virtual circuit in said link list last associated by said link list processor with one of said profile, sub-profile pairs.
9. A method of scheduling available bit rate cell transmission over an asynchronous transfer mode communication network characterized by a plurality of virtual circuit communication channels, each of said virtual circuits characterized by an allowed cell rate ACR, said method comprising:
a. generating MCR-rate virtual circuits requiring minimum cell rate transmission service through said network;
b. generating ABR-rate virtual circuits requiring available bit rate transmission service through said network;
c. outputting said MCR-rate virtual circuits at a constant bit rate; and, d. outputting said ABR-rate virtual circuits at an effective allowed cell rate ACR'i = ACRi-MCRi where 0 ~ i ~ (n-1) and n is the total number of said virtual circuits.
a. generating MCR-rate virtual circuits requiring minimum cell rate transmission service through said network;
b. generating ABR-rate virtual circuits requiring available bit rate transmission service through said network;
c. outputting said MCR-rate virtual circuits at a constant bit rate; and, d. outputting said ABR-rate virtual circuits at an effective allowed cell rate ACR'i = ACRi-MCRi where 0 ~ i ~ (n-1) and n is the total number of said virtual circuits.
10. A method as defined in claim 9, further comprising outputting said MCR-rate virtual circuits and said ABR-rate virtual circuits in merged priority sequence by outputting any of said generated MCR-rate virtual circuits before outputting any of said generated ABR-rate virtual circuits.
11. A method as defined in claim 10, further comprising applying a bandwidth allocation criteria:
to said virtual circuits whenever:
to said virtual circuits whenever:
12. A method as defined in claim 11, further comprising reducing said bandwidth allocation criteria to:
whenever:
whenever:
13. A method as defined in claim 10, further comprising:
a. receiving said MCR-rate virtual circuits and said ABR-rate virtual circuits together with UBR-rate virtual circuits requiring unspecified bit rate transmission service through said network;
b. outputting said MCR-rate and ABR-rate virtual circuits at a user-programmable priority rate between 0% and 100R; and, c. outputting said UBR-rate virtual circuits at a priority rate of 100% - said user-programmable priority rate.
a. receiving said MCR-rate virtual circuits and said ABR-rate virtual circuits together with UBR-rate virtual circuits requiring unspecified bit rate transmission service through said network;
b. outputting said MCR-rate and ABR-rate virtual circuits at a user-programmable priority rate between 0% and 100R; and, c. outputting said UBR-rate virtual circuits at a priority rate of 100% - said user-programmable priority rate.
14. A method of scheduling available bit rate cell transmission over an asynchronous transfer mode communication network characterized by a plurality of virtual circuit communication channels, each of said virtual circuits characterized by one or more profiles, said profiles each comprising a group of sub-profiles, each of said sub-profiles having a unique bandwidth allocation component, said method comprising:
a. pairing said profiles with said sub-profiles and storing said profile, sub-profile pairs;
b. sequentially processing each one of said profile, sub-profile pairs by:
i. comparing said one profile, sub-profile pair with a null profile, sub-profile pair to determine whether said one profile, sub-profile pair is null;
ii. transmitting said one profile, sub-profile pair if said one profile, sub-profile pair is not null; and, iii. over-writing said one profile, sub-profile pair with a selected non-null virtual circuit profile, sub-profile pair if said one profile, sub-profile pair is null.
a. pairing said profiles with said sub-profiles and storing said profile, sub-profile pairs;
b. sequentially processing each one of said profile, sub-profile pairs by:
i. comparing said one profile, sub-profile pair with a null profile, sub-profile pair to determine whether said one profile, sub-profile pair is null;
ii. transmitting said one profile, sub-profile pair if said one profile, sub-profile pair is not null; and, iii. over-writing said one profile, sub-profile pair with a selected non-null virtual circuit profile, sub-profile pair if said one profile, sub-profile pair is null.
15. A method of scheduling available bit rate cell transmission over an asynchronous transfer mode communication network characterized by an MCR queue, an ABR' queue, an ABR' buffer and an ABR merged queue, said method comprising the steps of:
a. removing from said MCR queue and transmitting to said ABR merged queue any data values contained in said MCR queue;
b. if said MCR queue contains no data values and if said ABR' buffer contains no data values then transmitting a null data value to said ABR merged queue;
c. if, prior to performing said step (a), said MCR
queue contained at least one data value and if said ABR' queue contains at least one data value then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue;
d. if said MCR queue contains no data values and if said ABR' buffer contains at least one data value then:
i. removing from said ABR' buffer and transmitting to said ABR merged queue said data values contained in said ABR' buffer;
ii. if said ABR' queue contains at least one data value after performing said step (d)(i) then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue; and, e. if, prior to performing said step (a), said MCR
queue contained at least one data value and if said ABR' buffer is not full and if said ABR' queue contains at least one data value then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue.
6. A method of scheduling available bit rate cell transmission over an asynchronous transfer mode communication network characterized by a plurality of virtual circuit communication channels, each of said virtual circuits having one or more prioritized profiles, each of said profiles having one or more prioritized sub-profiles, and further characterized by a pending pointer for indicating the highest priority one of said profiles for which any of said virtual circuits are pending, said method comprising the steps of:
a. selecting a pair of said profile, sub-profile values;
b. if both of said selected profile, sub-profile values are null, determining whether any virtual circuits are pending, as indicated by said pending pointer;
c. if no virtual circuits are pending, as indicated by said pending pointer, dispatching a null pointer and then terminating performance of said method;
d. if any virtual circuits are pending, as indicated by said pending pointer, then in highest priority sequence for each of said profiles:
i. selecting the highest priority one of said sub-profiles associated with said selected profile, as indicated by said pending pointer;
ii. determining whether any virtual circuits associated with said selected sub-profile are pending;
iii. if any virtual circuits associated with said selected sub-profile are pending, dispatching said pending virtual circuits;
iv. repeating said steps (d)(i) through (d)(iii) in highest priority sequence for every sub-profile associated with said selected profile and then terminating performance of said method;
e. if either of said profile, sub-profile values are not null, then:
i. for each of said profiles, determining whether any virtual circuits associated with any of said profiles are pending, as indicated by said pending pointer;
ii. if no virtual circuits associated with any of said profiles are pending, proceeding to step (e)(iii)(6);
iii. if any virtual circuits associated with any of said profiles are pending, then:
(1) selecting said one of said profiles indicated by said pending pointer;
(2) selecting the highest priority one of said sub-profiles associated with said selected profile;
(3) dispatching the highest priority pending virtual circuit associated with said selected sub-profile;
(4) repeating said steps (e)(iii)(2) and (e)(iii)(3) in highest priority sequence for every sub-profile associated with said selected profile until all pending virtual circuits associated with said respectively selected sub-profiles are dispatched;
(5) resetting said pending pointer to indicate that no virtual circuits associated with said selected profile are pending;
(6) reselecting said highest priority one of said sub-profiles associated with said selected profile;
(7) dispatching, from a virtual circuit queue, one virtual circuit in association with said reselected sub-profile;
(8) repeating said steps (e)(iii)(6) and (e)(iii)(7) once, in highest priority sequence, for every sub-profile associated with said selected profile;
(9) if no virtual circuits remain in said queue, resetting said pending pointer to indicate that no virtual circuits associated with said selected profile are pending; and, (10) terminating performance of said method.
a. removing from said MCR queue and transmitting to said ABR merged queue any data values contained in said MCR queue;
b. if said MCR queue contains no data values and if said ABR' buffer contains no data values then transmitting a null data value to said ABR merged queue;
c. if, prior to performing said step (a), said MCR
queue contained at least one data value and if said ABR' queue contains at least one data value then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue;
d. if said MCR queue contains no data values and if said ABR' buffer contains at least one data value then:
i. removing from said ABR' buffer and transmitting to said ABR merged queue said data values contained in said ABR' buffer;
ii. if said ABR' queue contains at least one data value after performing said step (d)(i) then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue; and, e. if, prior to performing said step (a), said MCR
queue contained at least one data value and if said ABR' buffer is not full and if said ABR' queue contains at least one data value then removing from said ABR' queue and transmitting to said ABR' buffer said data values contained in said ABR' queue.
6. A method of scheduling available bit rate cell transmission over an asynchronous transfer mode communication network characterized by a plurality of virtual circuit communication channels, each of said virtual circuits having one or more prioritized profiles, each of said profiles having one or more prioritized sub-profiles, and further characterized by a pending pointer for indicating the highest priority one of said profiles for which any of said virtual circuits are pending, said method comprising the steps of:
a. selecting a pair of said profile, sub-profile values;
b. if both of said selected profile, sub-profile values are null, determining whether any virtual circuits are pending, as indicated by said pending pointer;
c. if no virtual circuits are pending, as indicated by said pending pointer, dispatching a null pointer and then terminating performance of said method;
d. if any virtual circuits are pending, as indicated by said pending pointer, then in highest priority sequence for each of said profiles:
i. selecting the highest priority one of said sub-profiles associated with said selected profile, as indicated by said pending pointer;
ii. determining whether any virtual circuits associated with said selected sub-profile are pending;
iii. if any virtual circuits associated with said selected sub-profile are pending, dispatching said pending virtual circuits;
iv. repeating said steps (d)(i) through (d)(iii) in highest priority sequence for every sub-profile associated with said selected profile and then terminating performance of said method;
e. if either of said profile, sub-profile values are not null, then:
i. for each of said profiles, determining whether any virtual circuits associated with any of said profiles are pending, as indicated by said pending pointer;
ii. if no virtual circuits associated with any of said profiles are pending, proceeding to step (e)(iii)(6);
iii. if any virtual circuits associated with any of said profiles are pending, then:
(1) selecting said one of said profiles indicated by said pending pointer;
(2) selecting the highest priority one of said sub-profiles associated with said selected profile;
(3) dispatching the highest priority pending virtual circuit associated with said selected sub-profile;
(4) repeating said steps (e)(iii)(2) and (e)(iii)(3) in highest priority sequence for every sub-profile associated with said selected profile until all pending virtual circuits associated with said respectively selected sub-profiles are dispatched;
(5) resetting said pending pointer to indicate that no virtual circuits associated with said selected profile are pending;
(6) reselecting said highest priority one of said sub-profiles associated with said selected profile;
(7) dispatching, from a virtual circuit queue, one virtual circuit in association with said reselected sub-profile;
(8) repeating said steps (e)(iii)(6) and (e)(iii)(7) once, in highest priority sequence, for every sub-profile associated with said selected profile;
(9) if no virtual circuits remain in said queue, resetting said pending pointer to indicate that no virtual circuits associated with said selected profile are pending; and, (10) terminating performance of said method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/916,342 US6049526A (en) | 1996-03-27 | 1997-08-22 | Enhanced integrated rate based available bit rate scheduler |
| US08/916,342 | 1997-08-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2217262A1 CA2217262A1 (en) | 1999-02-22 |
| CA2217262C true CA2217262C (en) | 2001-08-14 |
Family
ID=25437108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002217262A Expired - Fee Related CA2217262C (en) | 1997-08-22 | 1997-10-01 | Enhanced integrated rate based available bit rate scheduler |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA2217262C (en) |
-
1997
- 1997-10-01 CA CA002217262A patent/CA2217262C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2217262A1 (en) | 1999-02-22 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |
Effective date: 20131001 |