JPH1065709A - Atm cell transmitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FIFO memory with a capacitance satisfying the whole quality classes without providing the FIFO memories at every virtual channel and also to prevent a hardware quality from being vast by providing quality classes in accordance with transmission delay permission quantity in ATM. SOLUTION: Cells are classified by quality class and stored in buffers 1n∼n and 21∼n . The cells are read out of the buffer of the quality class with high priority and shift is successively executed to the low-order ones. Otherwise a cell of the low-order class is inserted between the cells when there is a room in the transmission schedule of the cells in the high quality class with high priority. Thus, cell transmission which satisfies request quality as against transmission delay is executed with a small hardware quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ATM (Asynchronou).
s Transfer Mode: Used for communication.
The present invention is suitable for use in cell transmission by radio signals.
The present invention relates to a technique for reducing transmission delay and delay fluctuation of a cell. Although the present invention has been developed for use in wireless communication, it can be widely applied to wired communication and other general communication systems.

[0002] In this specification, the delay fluctuation is defined as a transmission delay time from a transmission end to a reception end and a time including a fluctuation of the transmission delay time.

[0003]

2. Description of the Related Art In recent years, paying attention to the mobility of wireless communication, ATM transmission is performed by a wireless system and integrated with a wired ATM system centered on an optical fiber to provide a seamless multimedia service. Attention has been paid to wireless ATMs for realizing communication services. In a wireless communication system, in order to effectively use limited frequency resources, it is effective to extract only cells containing information from input cells and wirelessly transmit only cells having significant information.

[0004] One terminal generally has a plurality of connections, and transmission quality characteristics required for each connection, that is, QOS (Quality Of Services) are different.
In general, CBR (Constant Bit Rate) and VBR (Var
iable Bit Rate) requires strict characteristics against delay fluctuation, and ABR (Available Bit Rate) and UBR
As for (Unspecified Bit Rate), strict characteristics are required for cell discarding, and the cell rate often fluctuates dynamically with time.

FIG. 12 is a diagram for explaining band or time slot allocation, in which the horizontal axis represents time and the vertical axis represents cell rate. Generally, in an ATM, a peak value (peak cell rate) and an average value (average cell rate) of a transmission rate (number of cells / second) are declared for each connection. If the peak value and the average value are different, it means that the transmission speed fluctuates. Similarly, the delay fluctuation amount (second) allowed for each connection is reported for the delay fluctuation. Therefore, it is necessary to provide a quality class for each of these required qualities and allocate a band or a time slot for each quality class.

However, if too many quality classes are provided, the quality control in the network becomes complicated. For example, with respect to delay fluctuation, a class requiring a delay fluctuation of 3 ms or less and a required value for the delay fluctuation are provided. It is currently under consideration to classify the data into two classes. In general, the transmission speed of a connection of a quality class having no required value for delay fluctuation also varies.

Here, a case where the number of quality classes of delay fluctuation is N = 2 will be described. There are two quality classes: quality class 1 in which high quality is required for delay fluctuation, and quality class 2 in which there is no quality requirement for delay fluctuation. R1 is the total value of the maximum cell rate (number of cells / second) declared for each connection of quality class 1, R2 is the total value of the average cell rate declared for each connection of quality class 2, and is declared for each connection of quality class 2. Assuming that the total value of the obtained maximum cell rates is R3, a time slot or a transmission band corresponding to a transmission rate corresponding to the sum of the cell rates R4 and R1 satisfying R2 ≦ R4 ≦ R3 is allocated. If R4 = R3 and a band of R1 + R4 is assigned, ATM cells with small delay fluctuations can be transmitted regardless of the quality class, but many bands or time slots are required. On the other hand, R4 = R
When the band of R1 + R4 is assigned as 2, the time slot or the band can be effectively used in the transmission system, and the finite frequency spectrum can be effectively used in the wireless communication system. However, if the transmission rate fluctuates in the connection of the quality class 2, the delay fluctuation also occurs in the connection of the quality class 1 and the quality is deteriorated.

FIG. 13 is a diagram showing the relationship between input cells and output cells in a conventional example. In FIG. 13, 15 time slots are provided for each time T, and cells of quality class 1 and quality class 2 are mixed. In addition, the number of time slots on the transmission line between the input and the output is six for each time T. When the number of cells of quality class 2 is small, the cells of quality class 1 are output without delay. However, when the number of cells of quality class 2 increases rapidly, the cells of quality class 2 interrupt the transmission timing of the cells of quality class 1 and a delay occurs. In the example of FIG. 13, the quality classes 1 and 2 have an average cell rate of 3 cells / T.

FIG. 14 shows a block configuration of a conventional apparatus. In FIG. 14, the transmitting unit TX includes a cell extraction circuit 91 that removes empty cells from input cells and extracts cells having significant information, and an extraction circuit 91 that absorbs fluctuations in the cell rate of the extracted cells. It comprises a transmission buffer circuit 92 for storing cells and a transmission circuit 93, and only cells having significant information extracted from input cells are transmitted at a constant rate. The identification of a cell having this significant information is determined by VPI (Vir) which is a connection identifier included in the header of the cell.
tual Path Identifier and / or VCI (Virtual Channel Identifier) is a fixed VPI and / or VCI indicating an empty cell.
This is performed by detecting that they do not match.

The receiving unit RX outputs the cells received by the receiving circuit 94 according to the transmission speed of each connection. The simplest method is to use a FIFO (First-I
There is a leaky bucket method in which n-First-Out) memories 96 _{1 to} 96 _n are provided and read out according to the average speed of each connection. In this FIFO read control method, each of the FIFO memories 96 _{1 to} 96 _n is accessed in order, and if there is a cell to be read, it is output.
There is a method of reading the next FIFO memory, a method called a so-called round robin method, and the like. The receiving unit RX in the case of the round robin method includes a cell separating circuit 95 that separates cells received by the receiving circuit 94 for each connection according to VPI and / or VCI, and n number of cells connected to the cell separating circuit 95. FIFO memory 96 ₁
To 96 _n and a FIFO read control circuit 97 for controlling the reading of the FIFO memories 96 _{1 to} 96 _n . The cell read speed of the FIFO read control circuit 97 depends on the interface speed with the terminal or the network, and the transmission speed between the transmitting and receiving units is equal to or lower than the interface speed.

[0011]

In the prior art, the receiving side requires an individual FIFO memory for each connection, and the individual FIFO memory needs to have a capacity corresponding to the maximum transmission rate allowed for one connection. There is. For this reason, a very large capacity FIFO memory is required on the receiving side, resulting in an increase in the amount of hardware.

In order to reduce the amount of hardware, a method of arranging a common memory without providing a FIFO memory for each connection and controlling the address of the memory is conceivable. It becomes extremely complicated and difficult to realize. Further, in these methods, the memory of a connection having no required quality for delay fluctuation may be read before the memory of a connection having a required quality characteristic for delay fluctuation is severe. The connection delay fluctuation may increase.

Since the cell rate of a connection having no required quality characteristic with respect to delay fluctuation often fluctuates, when a cell rate larger than the average cell rate R2 shown in FIG. 12 is input, the required quality characteristic with respect to delay fluctuation is severe. The transmission of the cell of the connection will be delayed, which will increase the delay fluctuation.
This can be improved by increasing the buffer capacity of the receiving unit and increasing the average transmission delay, but the required buffer capacity of the FIFO memory is further increased.

The present invention has been made in view of such a background, and an AT which can satisfy required quality characteristics with respect to delay fluctuations by using simple and small-scale hardware.
An object is to provide an M cell transmission device. SUMMARY OF THE INVENTION An object of the present invention is to provide an ATM cell transmission device capable of effectively utilizing a spectrum of a radio frequency. SUMMARY OF THE INVENTION An object of the present invention is to provide an ATM cell transmission device capable of effectively utilizing an allocated band or time slot.

[0015]

The first feature of the present invention is to separate input cells into quality classes based on an allowable time for delay fluctuations in both a transmitting unit and a receiving unit. The second feature of the present invention is the output control of the cells separated for each quality class, for example, output from a cell of a strict quality class of required quality characteristics, sequentially,
Control to shift to the output of the cell of the quality class with the required quality characteristic, or embed the cell of the quality class with the required quality characteristic in the gap between the cells of the quality class with the required quality characteristic and send it. To control.

As described above, various control methods can be conceived, which are classified according to the required quality and arranged in descending order of priority and utilize the accumulated data. For example, N of quality classes 1 to N is assigned in descending order of the quality required for delay fluctuation.
Separate and accumulate cells into individual classes. The read cells are transmitted with priority on the stored cells in the order of 1 to N. As a result, the cells required for the quality of the delay fluctuation are transmitted in order from the cell of the quality class having the highest quality.

That is, the present invention relates to an ATM cell transmitting apparatus, which comprises a transmitting section (TX) for transmitting a cell and a receiving section (RX) for receiving a cell. An ATM cell transmission device including a plurality of types of cells having different quality classes. According to a feature of the present invention, the transmitting unit allocates a transmission cell according to the quality class.
A transmission buffer circuit (1) for storing the cells sorted by the transmission cell separation circuit separately,
A transmission buffer read control circuit (13) for reading out the cells stored in the transmission buffer circuit in descending order of priority determined by the quality class, wherein the reception unit temporarily stores reception cells. Circuit (2)
And a reception buffer read control circuit (17) for reading out from the reception buffer circuit in descending order of priority.
And where it is.

[0018] Further, the receiving unit may be configured to sort a reception cell according to the quality class.
It is preferable that the reception buffer circuit (2) is configured to distinguish and accumulate the cells sorted by the reception cell separation circuit.

As described above, by separating a cell for each quality class, it becomes possible to perform appropriate cell output control for each quality class.

The quality class is VPI and / or VC
A different value is set for each I, and the transmission cell separation circuit (1
1) and / or the receiving cell separation circuit (12) includes:
It is desirable to include a table (31, 32) in which the classification of the quality class is recorded in accordance with this value, and means for distributing incoming cells with reference to this table.

A quality class determined for each VPI and / or VCI is determined in an upper layer when setting up communication connection.

A different value is set for the quality class for each VPI and / or VCI. The transmission cell separation circuit (11) includes a table (31) in which the classification of the quality class is recorded according to the value, and a table (31). Means for allocating incoming cells with reference to a table, and means for adding an identifier indicating a quality class to the allocated cells, wherein the receiving cell separating circuit (12) receives the incoming cell according to the identifier of the receiving cell. A configuration including means for allocating cells may be employed.

Thus, the quality class of the cell can be divided without providing a table for the receiving unit.

The transmitting unit includes a clock, and a time stamp adding circuit for adding an arrival time of an incoming cell as a time stamp to the cell according to the clock. The receiving unit includes a clock of the transmitting unit. A clock that generates the same time information; and a time stamp detection circuit that detects a time stamp from a cell stored in the reception buffer circuit. The reception buffer read control circuit uses the clock of the reception unit as a reference. It is also possible to adopt a configuration including means for reading the cells stored in the reception buffer circuit according to the time stamp.

Alternatively, the receiving section includes a clock and a time stamp detecting circuit for detecting a time stamp from cells stored in the receiving buffer circuit, and the receiving buffer read control circuit keeps a clock of the receiving section. Means for reading the cells stored in the reception buffer circuit according to the time stamp as a reference, wherein the transmission unit generates a time information identical to the clock of the reception unit; A configuration may also be provided that includes a time stamp adding circuit that adds the arrival time of the cell to the cell as a time stamp.

As described above, by managing cell transmission by the time stamp, delay fluctuation can be reduced. In addition, since the receiving unit and the transmitting unit perform time stamp addition and time stamp detection using the same clock,
It is possible to suppress the reversal of the cell order that occurs due to the clock skew.

[0027] Furthermore, a plurality of the transmitting units are provided, the receiving cell separating circuit includes means for distributing cells for each of the quality class and the transmitting unit, and the receiving buffer circuit stores the distributed cells. The receiving buffer read control circuit includes a means for preferentially reading from the highest priority determined by the quality class regardless of the transmitting unit. Can also. In this case, since the plurality of transmitting units use the same clock as the clock managed by the receiving unit, the receiving unit can multiplex cells from the plurality of transmitting units only by managing one clock.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

[0029]

【Example】

(First Embodiment) The configuration of the first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the first embodiment of the present invention.

The present invention relates to an ATM cell transmission device, which comprises a transmitting unit TX for transmitting cells and a receiving unit RX for receiving cells.
An ATM including a plurality of types of cells having different quality classes distinguished by required transmission quality.
It is a cell wireless transmission device. In the first to fourth embodiments of the present invention, a description will be given assuming that a wireless line is used between the transmitting unit TX and the receiving unit RX. However, the present invention can be similarly implemented even if the wireless line is a wired line, or if a network is provided in the middle.

Here, it is a feature of the present invention that the transmitting section TX separates a transmission cell separation circuit 11 for distributing transmission cells according to the quality class and a cell allocated by the transmission cell separation circuit 11. a transmission buffer circuit 1 ₁ to 1 _n of Betsushite storing, and transmission buffer read control circuit 13 reads the stored cells in the transmission buffer circuit 1 ₁ to 1 _n of priority determined by said quality class comprising a receiver RX includes a receive buffer circuit 2 ₁ to 2 _n for temporarily storing received cell, preferentially reading out the reception buffer read control from the highest from the reception buffer circuit 2 ₁ to 2 _n of said priority And a circuit 17.

Further, the receiving section RX includes a receiving cell separating circuit 12 for sorting received cells according to the quality class.
Includes a receive buffer circuit 2 ₁ to 2 _n has a structure in which a cell that has been distributed by this receiving cell demultiplexer 12 accumulates individually distinguished.

The quality class is VPI and / or VC
A different value is set for each I, and the transmission cell separation circuit 11 and / or the reception cell separation circuit 12 have tables 31 and 32 recording quality class divisions according to this value.
The transmission cell separation circuit 11 and / or the reception cell separation circuit 12 refer to the tables 31 and 32 and sort incoming cells.

Next, the operation of the first embodiment of the present invention will be described. The transmission cell separation circuit 11 detects a VPI and / or VCI, which is a connection identifier included in a cell header, from cells extracted from the input cell stream, and removes cells having fixed VPI and / or VCI indicating empty cells. I do. The quality class of the cell is determined based on the correspondence between the VPI and / or VCI and the declared quality classes 1 to n, and the transmission buffer circuit 1 corresponding to the quality classes 1 to n is determined.
And inputs the cell to the ₁ to 1 _n. As a result, the cells classified for each quality class are stored in the transmission buffer circuits ₁₁ to 1 _n . The transmission cell separation circuit 11 has a table 31 for storing VPI and / or VCI information for detecting empty cells and classifying cells containing significant information for each quality class.

A transmission timing of a cell predetermined for a radio channel is transmitted from the transmission circuit 14 to the transmission buffer read control circuit 13. The transmission buffer read control circuit 13 controls which of the n transmission buffer circuits ₁₁ to 1 _n is to be read according to the transmission timing. Specifically, searches whether there is a cell to be transmitted to the transmission buffer circuit 1 _1, reads it if any cell. Without searches whether there is a cell to be transmitted to the transmission buffer circuit 1 ₂ having a next priority, reads it if any cell. This is sequentially repeated, and if there is no cell to be transmitted also in the transmission buffer circuit 1 _n having the last priority, a dummy cell is transmitted. The same bit pattern as the dummy cell can be used for the dummy cell.
The read cell is transmitted to the transmission circuit 14 and transmitted to a wireless line. This makes it difficult for cells to stay in the transmission unit TX in the order of the quality classes 1 to n.

In the receiving cell separating circuit 12, the receiving circuit 15
VP included in the cell header from the cell received at
Detect I and / or VCI and remove cells with fixed VPI and / or VCI indicating dummy cells. Also, the quality class of the cell is determined based on the correspondence between the VPI and / or VCI and the declared quality classes ₁ to _n, and the cells are input to the reception buffer circuits 21 to 2 _n corresponding to the quality classes ₁ to _n . The receiving cell separation circuit 12 includes a table 32 for detecting VPI and / or VCI information for detecting dummy cells and classifying cells containing significant information for each quality class.

The output timing generation circuit 18 sends to the reception buffer read control circuit 17 a transmission timing of a cell determined in advance for a terminal or network following the subsequent stage. According to the received buffer read control circuit 17 in this transmission timing, n-number of the receiving buffer circuit 2 ₁
２2 _n is controlled. Specifically, searches whether there is a cell to be sent to the reception buffer circuit 2 _1, reads, if any cell. Without it, searches whether there is a cell to be sent to the reception buffer circuit 2 ₂ with the following priority, reads it if any cell. This is sequentially repeated, and if there is no cell to be transmitted to the reception buffer circuit 2 _n having the last priority, an empty cell is transmitted. The read cell is sent to the output timing generation circuit 18 and sent to the terminal or network following the subsequent stage. Thereby, the receiving units RX in the order of the quality classes 1 to n
Cell hardly occurs at the time.

The operation of the transmission buffer read control circuit 13 and the reception buffer read control circuit 17 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a flowchart showing the operation of the transmission buffer read control circuit 13 according to the first embodiment of the present invention. FIG. 3 is a flowchart showing the operation of the reception buffer read control circuit 17 according to the first embodiment of the present invention. As shown in FIG. 2, the transmission buffer read control circuit 13
Means that transmission buffer circuits 11 ₁ to 1 _{n in} which cells of quality classes ₁ to _n are respectively stored are transmitted from transmission buffer circuits ₁₁ to 1
Read cells in order of _n . That is, the transmission buffer circuit 1
Reading is started from ₁ (i = 1) (S1). If there is a cell in the transmission buffer circuit ₁ 1 (S2), reads out the cell from the transmission buffer circuit ₁ 1 (S3). If the transmission buffer circuit 1 ₁ is empty (S2), the transmission buffer circuit 1 ₂
Reading is started from (i = 2) (S4 → S5 → S2 →
S3). Read from the transmission buffer circuit 1 _n inserts a dummy when finished (S6). As a result, the cells are transmitted to the receiving unit RX in order from the cell having the higher quality required for the delay fluctuation.

As shown in FIG. 3, the reception buffer read control circuit 17 converts the reception buffer circuits 2 ₁ to 2 _{n in} which cells of quality classes ₁ to _n are respectively stored into the reception buffer circuits 2 _1.
Are read out in the order of 2 _n from. That is, reading is started from the reception buffer circuit 2 ₁ (i = 1) (S11).
If the cell in the receive buffer circuit 2 ₁ (S12), reads the cells from the reception buffer circuit 2 ₁ (S1
3). If the receiving buffer circuit 2 ₁ is empty (S12), it starts reading from the receive buffer circuit _{2 2 (i = 2) (} S14 → S15 → S12 → S13). When reading from the receiving buffer circuit 2 _n is completed, an empty cell is inserted (S
16). As a result, cells with higher quality required for delay fluctuation are sequentially transmitted to the terminal or the network.

FIG. 4 is a diagram showing the relationship between input cells and output cells according to the first embodiment of the present invention. There are three types of input cells: quality class 1, quality class 2, and empty cell. 1 is a fixed cell rate, quality class 2 is a variable cell rate, and the average cell rates of quality classes 1 and 2 are the same at 3 cells / T. The transmission cell is 6 cells / T (second). As can be seen from the above, in the conventional example shown in FIG. 12, if the cells of quality class 2 increase instantaneously, the transmission side causes a long-term stagnation of the cells of quality class 1, so that the cells of quality class 1 A large delay fluctuation occurs in the cell. This delay fluctuation is represented by R1 in FIG.
It becomes even larger in the case of 大 き く R2. On the other hand, according to the present invention, even if cells of quality class 2 increase instantaneously, delay fluctuation of quality class 1 can be kept constant.

Therefore, for example, in a wireless communication system, when one transmission frame length is T seconds, quality class 1 is always transmitted with priority regardless of how the cells to be transmitted after quality class 2 change. Therefore, the delay fluctuation of the cell of quality class 1 does not occur for T seconds or more.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of the second embodiment of the present invention.

The apparatus of the second embodiment of the present invention has the tables 31 and 32 only, whereas the apparatus of the first embodiment of the present invention has the tables 31 only in the transmission section TX.

The above-mentioned allowable time is VPI and / or V
Different criteria are set for each CI, and the transmission cell separation circuit 11
Has a table 31 in which quality class divisions are recorded in accordance with this criterion. The transmission cell separation circuit 11 refers to the table 31 to sort incoming cells, and displays the quality class in the sorted cells. An identifier is added, and the receiving cell separating circuit 12 sorts an incoming cell according to the identifier of the receiving cell.

As described above, by adding the identifier indicating the quality class to the header of the cell, the table 32 of the receiving unit RX can be omitted.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram of the device according to the third embodiment of the present invention. FIG. 7 is a flowchart showing the operation of the reception buffer read control circuit 17 according to the third embodiment of the present invention. The third embodiment of the present invention is characterized in that the transmitting section TX includes a time stamp adding circuit 20 and a clock 22, and the receiving section RX includes a time stamp detecting circuit 21 and a time information generating circuit 23. Here, the time information generation circuit 23 is a circuit that generates the same time information as the clock 22 of the transmission unit TX, and can be realized by a clock that measures time in synchronization with the clock 22 of the transmission unit TX.

The time stamp adding circuit 20 includes a transmitting unit T
When a cell arrives at X, a time stamp of the arrival time of the cell is added to the cell according to the clock 22. Also,
The clock 22 transmits the reference time to the receiving unit RX.

The cells stored in the transmission buffer circuits 1 ₁ to 1 _n are transferred to the reception unit RX according to the same procedure as described in the first embodiment of the present invention, and the reception buffer circuit 2
It is stored in the ₁ to 2 _n.

Time stamp detection circuit 21 of receiving section RX
Detects a time stamp corresponding to the stored cell in the receive buffer circuit 2 ₁ to 2 _n, and generates a read timing of the reception buffer read control circuit 17. This read timing is different from the output timing sent from the output timing generation circuit 18 to the reception buffer read control circuit 17, and is a cell read schedule generated according to the time stamp detected by the time stamp detection circuit 21.

The time information generating circuit 23 includes a transmitting unit T
Time information is generated based on the reference time received from X.
The output timing generation circuit 18 sends the output timing to the reception buffer read control circuit 17 according to the time information.

When the output timing is T0 and the read timing of the quality class i generated by the time stamp detection circuit 21 is T1i, the operation of the reception buffer read control circuit 17 is as shown in FIG. ~ N
Receive buffer circuits 2 ₁ to 2 in which the cells are stored respectively
The _n from the reception buffer circuit 2 ₁ reads cells in the order of 2 _n. That is, cell output is started from quality class 1 (i = 1) (S21). If the read scheduled time of the cell of quality class 1 be read from the receiving buffer circuit 2 ₁ by the reading timing T11 are scheduled are consistent or delay the scheduled time of the next output timing T0 (S22), the cell read out from the reception buffer circuit 2 ₁ (S23). If the read timing T11 is earlier than the output timing T0 (S22), the reception buffer circuit 2 ₂
Start reading from (i = 2) (S24 → S25)
→ S22 → S23). If no cell is read by the reception buffer circuit 2 _n , an empty cell is inserted (S2
6).

FIG. 8 is a diagram showing the relationship between input cells and output cells according to the third embodiment of the present invention. In FIG. 8, the conditions of the input cell and the radio link are the same as in FIG. 4, the clock 22 of the transmitting unit TX transmits the reference time to the receiving unit RX at every time T, and the clocks of the transmitting unit TX and the receiving unit RX This is an example of resetting every time. The cells of quality class 2 are output after a fixed delay T from the input time so that the cell order is not reversed. As can be seen from the above, according to the present invention, the arrival interval of cells input to the transmission unit TX can be reproduced by the reception unit RX by the time stamp, and in particular, transmission delay and delay fluctuation of quality class 1 cells can be reduced. In addition, delay fluctuation of cells of quality class 2 can be reduced. In addition, since the receiving unit RX uses the same clock as the transmitting unit TX, it is possible to avoid reversal of the cell order due to the clocks of the transmitting unit TX and the receiving unit RX being shifted.

In the third embodiment of the present invention, only the transmitting section TX is provided with a table 31, and the transmitting cell separating circuit 11 sorts incoming cells by referring to the table 31,
An identifier indicating a quality class is added to the allocated cells, and the receiving cell separating circuit 12 allocates incoming cells according to the identifiers of the receiving cells, whereby the table 32 of the receiving unit RX can be omitted.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a block diagram of a device according to the fourth embodiment of the present invention. FIG. 10 is a flowchart showing the operation of the reception buffer read control circuit 17 according to the fourth embodiment of the present invention. In the fourth embodiment of the present invention, the transmitting unit TX1
To TXm, a time stamp adding circuit 20 and a time information generating circuit 23 are provided.
Receive buffer circuit 21 _(TX1) corresponding to TXm
2 _{n (TX1)} , 2 _{1 (TX2) n2 n (TX2)} , ... _{21 (TXm) ２2
n (TXm)} , the time stamp detection circuit 21 and the clock 22
It is characterized by having.

The cells arriving at the transmitters TX1 to TXm are:
The data is transmitted to the receiver RX according to the same procedure as described in the third embodiment of the present invention. In addition, each transmission unit TX1 to TXm
The time information generation circuit 23 generates time information based on the reference time received from the receiving unit RX.

The receiving cell separating circuit 12 of the receiving unit RX sorts the cells received from the transmitting units TX1 to TXm for each quality class and each transmitting unit, and receives the cells according to the quality classes 1 to n and the transmitting units TX1 to TXm. Circuit _{21 (TX1)} -
2 _{n (TX1)} , 2 _{1 (TX2) n2 n (TX2)} , ... _{21 (TXm) ２2}
Enter a cell in _{n (TXm)} .

The time stamp detecting circuit 21 performs the receiving buffer circuits 21 _(TX1) to _{2n (TX1)} and 21 _(TX2) to _{2n (TX2 )} according to the same procedure as described in the third embodiment of the present invention. ₎ ,
... Read timings corresponding to _{21 (TXm)} to _{2n (TXm)} are generated. The clock 22 transmits the reference time to the transmission units TX1 to TXm.

As shown in FIG. 10, reception buffer read control circuit 17 includes quality classes 1 to n and transmission units TX1 to TX
Receive buffer circuit 2 in which cells of Xm are respectively stored
_{1 (TX1)} to _{2n (TX1)} , _{21 (TX2)} to _{2n (TX2)} , ..., _{21 (TXm)
２2 n (TXm)} to the reception buffer circuits 21 _(TX1) ２2 corresponding to the quality class 1 irrespective of the transmission units TX1 to TXm.
Receive buffer circuit 2 corresponding to quality class n from _{1 (TXm)
The} cells are read out in the order of _{n (TX1)} or 2 _{n (TXm)} . That is, when the transmission unit TXj is prioritized over TXj + 1 (j = 1, m-1), the cell is received from the reception buffer circuit 2 _{1 (TX1)} (i = 1, j = 1) corresponding to the quality class 1 and TX1. Is read (S31).

If T1 _{1 (TX1)} ≦ T0 (S32), the cell is transferred to the reception buffer circuit 2
_{1 (TX1) is} read (S33).

[0060] T1 _{1 (TX1)>} T0 if (S32), the reception buffer circuit 2 ₁ corresponding to quality class 1 and TX2 and _{(TX2) (i = 1,} j = 2) read timing T1 ₁ of _(TX2) The output timing T0 is compared, and if T1 _{1 (TX2)} ≦ T0, the cell is read from the reception buffer circuit _{11 (TX2)} (S34 → S35 → S32 → S33).

If T1 _{1 (TXm)} > T0 (i = 1, j = m) (S32), the read timing _{T12 (TX1)} of the receiving buffer circuit _{22 (TX1)} (i = 2, j = 1) And the output timing T0 (S34 → S35 → S36 → S37)
(→ S31 → S32), if no cell is read by the reception buffer circuit 2 _{n (TXm)} , an empty cell is inserted (S38).

FIG. 11 is a diagram showing the relationship between input cells and output cells according to the fourth embodiment of the present invention. In FIG. 11, the transmission unit is 2
That is, an example is shown in which cells of quality class 1 are input to the transmission units TX1 and TX2, respectively. As shown in FIG. 11, the transmission units TX1 and TX2 use a time information generation circuit 23 that is a clock that measures the same time information as the clock 22 of the reception unit RX, so that the reception unit RX manages one clock 22. Alone can multiplex cells from transmitters TX1 and TX2. Further, delay fluctuation can be reduced by the time stamp.

In the apparatus according to the fourth embodiment of the present invention, the transmitting section T
A table 31 is provided only for X1 to TXm, and the transmission cell separation circuit 11 refers to the table 31 to sort incoming cells, adds an identifier indicating a quality class to the sorted cells, and 12 sorts incoming cells according to the identifiers of the received cells, so that the table 32 of the receiving unit RX can be omitted.

[0064]

As described above, according to the present invention,
The required quality characteristics for delay fluctuation can be satisfied by simple and small-scale hardware. This allows
The spectrum of the radio frequency can be effectively used. Further, it is possible to effectively use the allocated band or time slot.

[Brief description of the drawings]

FIG. 1 is a block diagram of a device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the transmission buffer read control circuit according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the reception buffer read control circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing the relationship between input cells and output cells according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a device according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a device according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of a reception buffer read control circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a relationship between an input cell and an output cell according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a device according to a fourth embodiment of the present invention.

FIG. 10 is a flowchart showing the operation of a reception buffer read control circuit according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between input cells and output cells according to a fourth embodiment of the present invention.

FIG. 12 is a diagram for explaining band or time slot allocation.

FIG. 13 is a diagram showing a relationship between an input cell and an output cell in a conventional example.

FIG. 14 is a block diagram of a conventional device.

[Explanation of symbols]

₁ 1 ~1 _n, 92 transmission buffer circuit _{2 1 ~2 n, 2 1 (} TX1) ~2 n (TX1), 2 1 (TX2) ~
2 _{n (TX2)} ,... 2 _{1 (TXm)} to 2 _{n (TXm)} reception buffer circuit 11 transmission cell separation circuit 12 reception cell separation circuit 13 transmission buffer read control circuit 14, 93 transmission circuit 15, 94 reception circuit 17 reception Buffer read control circuit 18 Output timing generation circuit 20 Time stamp addition circuit 21 Time stamp detection circuit 22 Clock 23 Time information generation circuit 31, 32 Table 91 Cell extraction circuit 95 Cell separation circuit 96 _{1 to} 96 _n FIFO memory 97 FIFO read control circuit RX receiver TX, TX1 to TXm transmitter

Continuation of front page (72) Inventor Atsushi Ota 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yuichi Sagawa 3- 19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Telephone Co., Ltd.

Claims (7)

[Claims] 1. A transmission unit (TX) for transmitting a cell and a reception unit (RX) for receiving a cell, wherein the cell includes a plurality of types of cells having different quality classes distinguished by required transmission quality. In the ATM cell transmission device, the transmission unit is configured to distribute transmission cells according to the quality class, and a transmission buffer circuit that distinguishes and accumulates the cells distributed by the transmission cell separation circuit. (1) and a transmission buffer read control circuit (13) for reading the cells stored in the transmission buffer circuit from those having the highest priority determined by the quality class. A receiving buffer circuit (2) for temporarily storing, and a receiving buffer read control circuit for preferentially reading from the higher priority one from the receiving buffer circuit. (17) and the ATM cell transmission apparatus characterized by comprising a. 2. The receiving section includes a receiving cell separating circuit (12) for sorting received cells according to the quality class, and the receiving buffer circuit (2) separates the cells sorted by the receiving cell separating circuit. 2. The ATM cell transmission device according to claim 1, wherein the ATM cell transmission device is configured to store the data in a distinguished manner. 3. The quality class is VPI and / or V
A different value is set for each CI, and the transmission cell separation circuit (11) and / or the reception cell separation circuit (12) have tables (31, 32) recording quality class divisions according to the values, Means for allocating incoming cells by referring to a table.
M cell transmission device. 4. The quality class is VPI and / or V
A different value is set for each CI, and the transmitting cell separating circuit (11) has a table (31) in which the classification of the quality class is recorded in accordance with the value, and means for sorting incoming cells by referring to this table. And a means for adding an identifier indicating a quality class to the sorted cells, and wherein the received cell separating circuit (12) includes means for sorting incoming cells according to the identifiers of the received cells. ATM cell transmission device. 5. The transmitting unit includes a clock, and a time stamp adding circuit that adds an arrival time of an arriving cell as a time stamp to the cell according to the clock, and the receiving unit includes a clock of the transmitting unit. A time stamp detection circuit 21 for detecting a time stamp from cells stored in the reception buffer circuit; and a reception buffer read control circuit,
5. A according to claim 1, further comprising means for reading out cells stored in said reception buffer circuit in accordance with said time stamp with reference to a clock of said reception unit.
TM cell transmission device. 6. The receiving section includes a clock and a time stamp detecting circuit (21) for detecting a time stamp from cells stored in the receiving buffer circuit, and the receiving buffer read control circuit controls the clock. Means for reading out cells stored in the reception buffer circuit according to the time stamp as a reference, wherein the transmission unit generates a time information identical to the clock of the reception unit; 5. The ATM cell transmission device according to claim 1, further comprising a time stamp adding circuit for adding a cell arrival time to the cell as a time stamp. 7. The receiving cell separating circuit includes a plurality of the transmitting units, the receiving cell separating circuit includes a unit for distributing cells for each of the quality class and the transmitting unit, and the receiving buffer circuit includes the distributed cells. 7. The receiving buffer read control circuit includes means for distinctively accumulating the data, and the receiving buffer read control circuit includes means for reading out data having a higher priority determined by the quality class irrespective of the transmitting unit. ATM cell transmission device.