CA2187817A1 - Railway interlocking system with software architecture and its implementation process - Google Patents

Abstract

Railway interlocking system with software architecture and its implementation method A railway interlocking system, which is used for the traffic of trains in safety on a network made up of a plurality of track equipments, comprises a set of tasks (Trc -AEA, ...) respectively associated with the track equipment constituting the network. The tasks implement a distributed logic of establishment and release of routes by propagation of messages through successions of communication logic channels (6) interconnecting the tasks according to an arrangement corresponding to a certain geographical topology of the railway network under control . The implementation of the system is done by computer processing of a network description file and a library of generic modules each implementing a state machine.

Description

~ l8 ~ l7 Architectural rail interlocking system software and its implementation method The invention relates to safe train traffic on a rail network, and more particularly a rail interlocking system based on a software architecture.
Such a system is already known from the patent application European N0581281. This system includes a rule base, lo an inference engine, and a data model on which the rules are applied to establish and release routes. The data model represents the equipment of track constituting the network by kinds of doors logical. Each rule defines conditions to be verified by 15 a logic gate before a train entry on the corresponding network equipment of the network is permitted.
This interlocking system has the advantage of being much more flexible than traditional solutions to relay base. In particular, such a system 20 interlocking can be implemented by processing computer a high level description file abstraction of the network and the base of rules of fa, con build the data model corresponding to the network to control. If the rule base is designed, cue fairly 25 generic, it can be used for the implementation of other interlocking systems without modification. Despite that flexibility, this known rail interlocking system requires for its execution, a processing resource centralized in which the rule base resides, the 30 data model and inference engine. The capabilities of processing this resource should be that much more important that the rail network under control is complex since the complexity of the data model is growing with that of the network. It is also suggested in the 35 document cited above, to exploit a resource multiprocessors which allows to parallelize certain -treatments with the disadvantage of making maintenance of the more complex system.
The object of the invention is to propose a system rail interlocking based on architecture software of another design and likely to be distributed across a plurality of processing resources low cost like microcomputers. In particular, the invention aims to provide such an interlocking system railway able to exploit processing resources 10 already in place in the monitoring / control installations existing rail networks and used for the acquisition signals from the track equipment.
To this end, the invention relates to a system rail interlocking based on architecture software and used for safe train traffic on a network made up of a plurality of track equipment.
This system includes a set of associated tasks respectively to the track equipment constituting the network. Tasks implement distributed logic 20 establishing and releasing routes by propagation messages through successions of logical channels of communication interconnecting tasks according to a arrangement corresponding to a certain topology of the rail network under control. In 25 particular, this distributed logic of propagation of messages is implemented in tasks in the form of finite state machines. Finite state machines interact with each other by spreading messages along logical communication channels.
According to this software architecture, tasks have a asynchronous behavior. High complexity of a network rail to control results in a large number of tasks to be performed. However, since the tasks have a asynchronous behavior, it is not useful to provide a 35 very high-capacity treatment resource for their execution because tasks can be distributed on a ~ 1 8 ~ 81 ~

low capacity processing resource set of execution if only a small number of tasks reside in each low-capacity processing resource, the cost of such a low processing resource set 5 capacity being in addition much lower than that of a unique processing resource of equivalent capacity. In plus, the autonomous and asynchronous operation of the tasks of the solution according to the invention allows simple control of the proper functioning of each task which contributes to 10 decrease system maintenance costs of engagement.
The invention extends to a method for implementing a such a rail interlocking system on the basis of a computer processing of a high description file 15 level of abstraction of the railway network to be checked and a library of generic software modules each implementing a corresponding finite state machine to a type of track equipment. The module library generic software can be used, without modification, to implement different interlocking systems for control different corresponding rail networks.
An embodiment of the invention is described above with reference to the figures.
Figure 1 schematically shows a center of integrated electronic control including system according to the invention.
Figure 2 is a block diagram of a rail network.
Figure 3 illustrates the software architecture of the system according to the invention adapted to the rail network 30 shown in Figure 2.
Figure 4 is a diagram illustrating the propagation of streams of messages through tasks associated with a succession of corresponding track equipment.
Figure 5 illustrates the process for implementing a system according to the invention.

218 / gl ~

Figure 6 is a block diagram of a rail network from which a description file is made high level of network abstraction.
Figure 1, the rail interlocking system 1 according to the invention is part of a more complex set (integrated electronic control center) including a control station 2 from which an operator monitors the situation on the rail network 3 under the control of interlocking system.
A rail interlocking system is used to establish (activate ~ and release routes in such a way as to maintain traffic security on a network. In particular, it is to avoid the collision of trains on the network. However, a collision can occur if, for example, interlocked routes intersect.
The interlocking system 1 according to the invention includes a set of tasks associated respectively with corresponding track equipment constituting the network to control and communicate with each other by messages from asynchronously as described below.
More specifically, the tasks implement a distributed logic for establishing and releasing routes by propagation of messages through successions of logical communication channels each interconnecting a message output of a task and message input of a other task. The logical communication channels are implemented between tasks according to a layout corresponding to a certain geographic topology of the network so that each succession of channels communication logic actually corresponds to a route predefined train circulation on the network. In other words, for a route passing successively by a succession of track equipment, there is a corresponding succession of logical channels of communication that interconnect tasks associated with these equipment.

2l878l 7 Figure 2 schematically shows a network railway which serves as an example to explain the invention and Figure 3 shows the software architecture of the system rail engagement corresponding to this example of 5 network.
Figure 2, the rail network has two AE tracks and AB coupled by a switch and serving a station G.
This network is made up, from a functional point of view, of a plurality of track equipment, the arrangement relative of track equipment defining a certain network topology.
On the AE channel, there are arranged in sequence (from left to right in Figure 2), a first track circuit referenced AEA, a second track circuit AEB, a signal 15 multi-aspect MP263 (traffic light for example), a first MP2205B switch (electrically operated), a second MP2206A switch, an MP1002 operating signal (traffic light two-color in particular), a third AED track circuit, a second multi-aspect signal MP265, a fourth circuit of 20 AEE channel and a fifth AEF channel circuit.
On track AB, we find arranged in sequence (from right to left in Figure 2), a first track circuit ABE, a second ABG channel circuit, a first multi-signal MP262 aspects, a third ABJ track circuit, a first 25 MP2206B switch, a second MP2205A switch, a second multi-aspect signal MP261, a fourth ABP channel circuit and a fifth ABR track circuit.
On this network, trains can enter different predefined routes, each starting from a signal 30 multi-aspect like MP261 signal or signal maneuvering and passing through different successions track equipment. For example, the route referenced R261 in Figure 2, part of the multi-aspect signal MP261 and passes successively through the switch MP2205A, 35 MP2206B switch, 1 MP2206A switch, circuit AED channel and finally by the multi-aspect MP26S signal. It is 21 ~ 7 ~ 7 heard whether the signals are part of a route or not according to their orientation relative to the direction of circulation of the train on the route.
Figure 3, the software architecture of the system 5 railway interlocking corresponding to the network rail in Figure 2 shows the geographic topology of this network. in this figure, the tasks are represented by blocks between which channels appear communication logics represented by arrows 6. A
10 logical communication channel implemented between two tasks corresponds to part of a route passing through both track equipment associated with these two tasks. If a train can take this part of the route in both directions traffic, the corresponding tasks are interconnected by two logical communication channels parallel. This is the case for example for the two channels communication logic interconnecting tasks referenced dPnt-2205A and dPnt-2206B.
For clarity, the blocks representing the tasks are presented in different forms depending on the type of track equipment associated with each task because the tasks associated with the same type of track equipment have a identical logic operation. We can see in the figure 3, associated tasks Sig-261, Sig-262, Sig-263 and Sig-265 25 each with a multi-aspect signal, tasks Trc-AEA, Trc-AEB, Trc-AED, Trc-AEE, Trc-AEF, Trc-ABE, Trc-ABG, Trc-ABJ, Trc-ABP
and Trc-ABR each associated with a track circuit, a task Shi-1002 associated with a maneuvering signal and tasks dPnt-2205A, dPnt-2205B, dPnt-2206A and dPnt-2206B associated each to a switch.
The operating principle of distributed logic by message propagation is described below based on of route R261 and with reference to Figures 3 and 4.
Route R261 corresponds to a succession of canals communication logic interconnecting in sequence the tasks Sig-261, dPnt-2005A, dPnt-2006B, dPnt-2005B, Trc-AED and ~ 1878 ~

Sig-265 whose corresponding blocks are shown hatched on figure 3. The entry of route R261 corresponds to the Sig-261 task.
Establishment of route R261 The establishment of an itinerary is required from checkpoint 1. A request to establish this route sent from checkpoint 1 (symbolized by sys in Figure 4) is received by the input task of the route in the form of an entry message including a 10 route identifier. In the example, the task Sig-261 receives the message Req (R261), the identifier of route being symbolized by R261. A first process propagation of the establishment request message the route, from the route entry task and following a loop through the series of tasks corresponding to this route and returning to the task of the route, is implemented by all of these tasks. In particular, the message R261 is propagated by tasks Sig-261, dPnt-2005A, dPnt-2006B, dPnt-2005B, Trc-20 AED and Sig-265 following a loop called allocation loop during which each task in question is allocated for route R261 on receipt of the Req message (R261) sau ~ en presence of a conflict situation (the task is already allocated for another route). In the case of a conflict situation detected by a task, a message Conf (R261) is raised, from task to task, from the task in question to the route entry task like the task Sig-261, which transmits this message to the control. Figure 4, if all the tasks corresponding to the R261 route are allocated for the R261 route, the last task Sig-265 returns the message Req (R261) to the entry task Sig-261 of route R261. The Sig task 261 sends an Alloc message (R261) to the control station to confirmation. This first process ensures that each task allocates itself for a single predefined route of which establishment is required.

A second process is then implemented by the tasks that are allocated for a route, in order to check that all track equipment the route are placed in a correct position (positioning of the needles in particular) before opening the running of a train on the route and, in the case otherwise, order them to place them in the position required. This second process still consists in the propagation of a Ctrl message from task to task, from the 10 route entry task and following a so-called loop control loop. upon receipt of this message, each task commands the correct positioning of the equipment channel with which it is associated and recovers in a signal status information about the current position 15 occupied by this equipment. In particular, the task Sig-261 upon receipt of the Req message (R261) from the task Sig-265 commands the MP261 signal to be red, recovers the information relating to the current state of the signal MP261 and propagate this information in an rtechk parameter included 20 in the Ctrl message (R261, rtechk). The message Ctrl (R261, rtechk) is propagated from task to task while the rtechk parameter is updated by each task and each track equipment is controlled to occupy the correct position before route opening.
25 Finally, task Sig-265 returns the message Ctrl (R261, rtechk) to task Sig-261. When the Sig-261 task receives the message Ctrl (R261, rtechk), it performs a processing to control, based on information contained in the rtechk parameter, if all of the 30 track devices are positioned correctly. Yes all track equipment is not positioned correctly, the message Ctrl (R261, rtechk) is again propagated according to the control loop. In case the track equipment are all positioned correctly, the 35 task Sig-261 sends the message Set (R261) to the check to confirm that route R261 is now

2 1 ~ 7 ~ 1 7 g established ~ or engaged) until the occurrence of a condition of release. The Ctrl message may be propagated several times following the front control loop all track equipment is positioned correctly due to the fact that the time required to certain track equipment to change position (change of needle position) is longer than the time required to propagate the Ctrl message following the control loop.
lo Upon receipt of the message Ctrl (R261, rtechk), the task Sig-261 begins a process of periodic control of the condition of the track equipment. This process consists of propagation of the message Chk (R261, rtechk), from task to task, following a loop called control loop during 15 from which each task retrieves information relating to the current state of the associated track equipment and feed this information back into the rtechk parameter via the message Chk (R261, rtechk) up to the input task of the route. Task Sig-265 returns the message Chk (R261, rtechk) to task Sig-261 which controls, from the rtechk parameter, the current state of the track equipment, so that a malfunction of the track equipment the started route can easily be detected. This process is carried out periodically, with a fairly high frequency.
Automatic release of the established route When a train sets off on route R261 which has been established, its progress on this route results in information changes in the rtechk parameter of the 30 Chk message. Normally only the multi-aspect signal of the route R261 may change over time, between the moment when the route is established and the moment when he is released, passing successively through the states red, orange and green. From the moment the task Sig-261 detects that the train has crossed a certain number of track circuits in the route by identifying the 218781 ~

changes in the rtechk parameter with each loop of control she begins a process of releasing from the route R261 which still consists in the propagation of a message, here the Free message (R261), from task to task following a loop called release loop during which each task reallocates for the route on receiving the Free message. In the example in Figure 4, when task Sig-261 receives the message Free (R261) from the task Sig-265, the set of tasks for the route R261 lo are deallocated and task Sig-261 sends this message to checkpoint for information. From now on, traffic on the R261 route is no longer authorized until this route is established again.
It is understood that this logic of propagation of 15 messages can be refined, following the principle indicated above on it, to implement other features like release of routes at the operator's request, permanent maintenance of an established route, etc.
According to the invention, the propagation logic of 20 messages is advantageously made up of automata finite states which are implemented in the tasks. Each PLC of a task is triggered on reception of a message expected, transits from a current state to another state in performing some processing and returns a message in exit. The successive states of each PLC
correspond to the successive processes of propagation of different messages. According to this solution, the implementation of the rail interlocking system 1 can be carried out semi-automatically from a 30 computer processing of a description file 5 of high level of abstraction from the rail network to be checked and a library 6 of generic software modules each implementing a corresponding finite state machine to a type of track equipment.
More specifically, Figure 5, from a diagram 4 of the rail network to be checked, a -technician expresses the characteristics of the network in data a language of high level of abstraction, these data being recorded in the description file 5. An example of the content of a high-level description file 5 of abstraction for the rail network shown in figure 6 is given in Annex 1 (note that this rail network is similar to that shown in Figure 2). The content of this description file is analogous to that used for implement the known rail interlocking system 10 European patent N0581281 indicated as state of the art technical. We find in this file different sections (indicated by "Level 0, Level 1, ....") which define the network characteristics, list all the track equipment and identify routes. So at the section referenced "Level 2A", there is a description of route R261 which served as an example for the description of how distributed logic works propagation of messages.
An example of the source code of a software module 20 generic implementing a finite state automaton corresponding to a multi-aspect signal is provided to appendix 2. Another example of the source code of a module generic corresponding to a track circuit is still provided in Annex 3. The source code for each module is 25 given here in a semantic high level language. he includes several sections and in particular a section of declaration of input messages "Input Messages", a output message declaration section Messages "and a status reporting section 30 "States" transition. In the declaration sections of input or output messages, the transmitter or the receiver of the message is represented by a generic identifier such as "Sig", "Tim", "Sys", "Up", "Dn", "Back". Annex 4 illustrates the flow of messages Req, Ctrl, Chk etc ... by resuming the 35 message terminology used in source code for generic modules given in appendices 2 and 3.

~ 12 2187 ~ 17 At the time of the computer processing indicated above with reference to Figure 5, the source code for each task is generated from the source code of a generic module corresponding to the track equipment which must be associated with 5 the task and the generic identifiers of transmitter and message receiver are "replaced" by appropriate task identifiers retrieved from the description of the network to establish the logical channels of communication. We will easily understand that each channel communication logic is a connection that is established, in the source code of each task, by a primitive transmission or reception of a communication protocol point ~ point of the first in first out (FIFO) type. The task source code is then compiled to get the lS executable tasks communicating by system messages according to the invention. It is understood that processing units supporting the tasks should be connected together via a network communication physics, like a field network, which 20 supports a communication protocol as defined above above.

Claims (4)

1 / A rail interlocking system based on a software architecture and used for train traffic in safety on a railway network made up of a plurality track equipment, characterized in that it comprises a set of tasks (Trc-AEA, Trc-AEB, ...) associated respectively to track equipment (AEA, AEB, ...) correspondent constituting the network, in that the tasks implement distributed logic for establishment and release of routes by message propagation (Req, Ctrl, Chq, Free) through successions of channels communication logic (6) each interconnecting a message output of a task and message input of a other task, and in that the logical channels of communication are implemented between tasks following a arrangement corresponding to a certain topology network geography. 2 / The system according to claim 1, in which the distributed message propagation logic is made up by finite state automata implemented in tasks. 3 / The system according to claim 1, in which the distributed logic is arranged to propagate messages to through a succession of tasks including the equipment associated lanes define a route, so that these messages follow logical communication channels interconnecting these tasks in a loop starting from the first task of this succession, passing successively by the other tasks of this estate and returning to the first task. 4 / A method for implementing a system rail engagement according to claim 2, consisting in the computer processing of a file high level description of network abstraction railway and a library of software modules generics each implementing a finite state machine corresponding to a type of track equipment.

Annex 1 / * LDL Layout Specification * /
@@@ SCHEME PLAN @@
DIAGRAM PLAN:: Layout _ 1 _ 02;
{
INTERLOCKING: MANAIR;
VERSION: V4.0;
DATE: 18.DEC.93;
SOURCE: "BC - Conforms to Issue 4 LDL BNF Spec.";
L0: 3;
L1: 16;
L2A: 15;
L2B: 3;
L2C: 0;
L3A: 43;
L3B: 10;
L3C: 0;
]
@@@@

/ * Level 0 - Network * /
@@@ L0-1 @@
LINE_OF_WAY :: branch1;
(( NODE_0: manchester_airport_station;
NODE_1: boundaryl;
) @@@@
@@@ L0-2 @@
BOUNDARY :: boundaryl;
(( LINE_OF_WAY: branch1;
TEXT: "To Heald Green";
}
@@@@
@@@ L0-3 @@
FEATURE:: manchester_airport_station;
(( LINE_OF_WAY-LIST: branch1;
TEXT: "Manchester Airport Station";
]
@@@@
/ * Level 1 - Track * /
@@@ L1-1 @@
TRACK:: track1;
(( NODE_0: trkend1;
NODE_1: pn1;
LENGTH: 258.50YDS;
]
@@@@
@@@ L1-2 @@

TRACK:: track2;
(( NODE_0: pn2;
NODE_1: trkend2;
LENGTH: 393.25YDS;
}
@@@@
@@@ L1-3 @@
TRACK:: track3;
(( NODE_0; pn1;
NODE_1: pn3;
LENGTH: 288.75YDS;
]
@@@@
@@@ L1-4 @@
TRACK:: track4;
(( NODE_0: pn1;
NODE_1: pn2;
LENGTH: 140.25YDS;
) @@@@
@@@ L1-5 @@
TRACK:: track5;
(( NODE_0: pn4;
NODE_1; pn3;
LENGTH: 118.25YDS;
) @@@@
@@@ L1-6 @@
TRACK:: track6;
{
NODE_0: pn4;
NODE_1: pn2;
LENGTH: 41.25YDS;
) @@@@
@@@ L1-7 @@
TRACK:: track7;
{
NODE_0: pn3;
NODE_1: trkbnd1;
LENGTH: 1017.5YDS;
) @@@@
@@@ L1-8 @@
TRACK:: track8;
{
NODE_0: trkbnd2;
NODE_1: pn4;
LENGTH: 1130.25YDS;
}
@@@@

@@@ L1-9 @@
TRACK_END_NODE:: trkend1) {
TRACK: track1;
}
@@@@
@@@ L1-10 @@
TRACK_END_NODE:: trkend2 [
TRACK: track2;
}
@@@@
@@@ L1-11 @@
TRACK_BOUNDARY_NODE:: trkbnd1;
{
TRACK: track7;
]
@@@@
@@@ L1-12 @@
TRACK_BOUNDARY_NODE:: trkbnd2;
[
TRACK: track8;
}
@@@@
@@@ L1-13 @@
POINTS_NODE:: pn1;
(( TYPE: CONTROLLED;
PATH_1: (track1, track3);
PATH_2: (track1, track4);
POINT_MACHINE-LIST: PMP2205B;
]
@@@@
@@@ L1-14 @@
POINTS_NODE:: pn2;
{
TYPE: CONTROLLED;
PATH_1: (track6, track2);
PATH_2: (track6, track4);
POINT_MACHINE-LIST: PMP2205A;
) @@@@
@@@ L1-15 @@
POINTS_NODE:: pn3;
(( TYPE: CONTROLLED;
PATH_1: (track7, track3);
PATH_2: (track7, track5);
POINT_MACHINE-LIST: PMP2206A;
}
@@@@
@@@ L1-16 @@
POINTS_NODE:: pn4;
{
TYPE: CONTROLLED;

PATH_1: (track6, track8);
PATH_2: (track6, track5);
POINT_MACHINE-LIST: PMP2206B;
]
@@@@
/ * Level 2A - Signaling Features * /
@@@ L2A-1 @@
INTERLOCKING:: MANAIR;
[
NUMBER: 2;
CONTROL_CENTRE: Manchester_Piccadilly;
CC_ID: MP;
I_SECTION-LIST: ((track1,0,1), (track2,0,1), (track3,0,1), (track4,0,1), (track5,0,1), (track6,0,1), (track7,0,0.814), (track8,0.479.1));
M_SECTION-LIST: ((track1, trkend1, 0YDS, 258.5YDS), (track2, trkend2, 0YDS, 393.25YDS), (track3, pn1, 0YDS, 288.75YDS), (track4, pn1, 0YDS, 140.25YDS), (track5, pn4, 0YDS, 118.25YDS), (track6, pn4, 0YDS, 41.25YDS), (track7, pn3, 0YDS, 827.75YDS), (track8, trkbnd2, 0YDS, 541.75YDS));
}
@@@@
@@@ L2A-2 @@
ROUTE:: R261A (M);
{
TYPE: HAND;
INTERLOCKING: MANAIR;
ENTRANCE: SMP261;
EXIT: SMP265;
OVERLAP: OAEE;
LENGTH: 921.25YDS;
SPEED_RESTRICTION-LIST: airport_station_area, airport_down;
D_I_SECTION: {((track2,0.413,1), pn2), ((track6,0,1), pn4), ((track5,0,1), pn3), ((track7,0,0.589), trkbnd1)};
D_M_SECTION: {((track2, pn2,0YDS, 162.25YDS), pn2), ((track6, pn4,0YDS, 41.25YDS), pn4), ((track5, pn3,0YDS, 118.25YDS), pn3), ((track7, pn3,0YDS, 599.5YDS), trkbnd1));
}
@@@@
@@@ L2A-3 @@
ROUTE:: R261A (S);
(( TYPE: SHUNT;
INTERLOCKING: MANAIR;
ENTRANCE: SMP261;
EXIT: SMP265;
LENGTH: 921.25YDS;

SPEED_RESTRICTION-LIST; airport_station_area, airport_down;
D_I_SECTION: {((track2,0.413,1), pn2), ((track6,0,1), pn4), ((track5,0,1), pn3), ((track7,0,0.589), trkbnd1));
D_M_SECTION: {((track2, pn2,0YDS, 162.25YDS), pn2), ((track6, pn4,0YDS, 41.25YDS), pn4), ((track5, pn3,0YDS, 118.25YDS), pn3), ((track7, pn3,0YDS, 599.5YDS), trkbnd1));
}
@@@@
@@@ L2A-4 @@
ROUTE:: R262A (M);
(( TYPE: HAND;
INTERLOCKING: MANAIR;
ENTRANCE: SMP262;
EXIT: bufstop2;
LENGTH: 907.5YDS;
SPEED_RESTRICTION-LIST: airport_up, airport_station_area;
D_I_SECTION: {((track8,0.82,1), pn4), ((track6,0,1), pn2), ((track2,0,1), trkend2));
D_M_SECTION: {((track8, pn4,0YDS, 473YDS), pn4), ((track6, pn2,0YDS, 41.25YDS), pn2), ((track2, trkend2,0YDS, 393.25YDS), trkend2));
) @@@@
@@@ L2A-5 @@
ROUTE:: R262A (C);
{
TYPE: CALL_ON;
INTERLOCKING: MANAIR;
ENTRANCE: SMP262;
EXIT: bufstop2;
LENGTH: 907.5YDS;
SPEED_RESTRICTION-LIST: airport_up, airport_station_area:
D_I_SECTION: [((track8,0.582,1), pn4), ((track6,0,1), pn2), ((track2,0,1), trkend2));
D_M_SECTION: [((track8, pn4,0YDS, 473YDS), pn4), ((track6, pn2,0YDS, 41.25YDS), pn2), ((track2, trkend2,0YDS, 393.25YDS), trkend2));
}
@@@@
@@@ L2A-6 @@
ROUTE:: R262B (M);
(( TYPE: HAND;
INTERLOCKING: MANAIR;
ENTRANCE: SMP262;
EXIT: bufstop1 LENGTH: 913YDS;
SPEED_RESTRICTION-LIST: airport_up, airport_station_area;
D_I_SECTION: {((track8,0.582,1), pn4), ((track6,0,1), pn2), ((track4,0,1), pn1), ((track1,0,1), trkend));
D_M_SECTION: {((track, 8, pn4,0YDS, 473YDS), pn4), ((track6, pn2,0YDS, 41.25YDS), pn2), ((track4, pn1,0YDS, 140.25YDS), pn1), ((track1, trkend1,0YDS, 258.5YDS), trkend1));
) @@@@
@@@ L2A-7 @@
ROUTE:: R262B (C);
(( TYPE: CALL_ON;
INTERLOCKING: MANAIT;
ENTRANCE: SMP262;
EXIT: bufstop1;
LENGTH: 913YDS;
SPEED_RESTRICTION-LIST: airport_up, airport_station_area;
D_I_SECTION: {((track8,0.582,1), pn4), ((track6,0,1), pn2), ((track4,0,1), pn1), ((track1,0,1), trkend1))};
D_M_SECTION: {((track8, pn4,0YDS, 473YDS), pn4), ((track6, pn2,0YDS, 41.25YDS), pn2), ((track4, pn1,0YDS, 140.25YDS), pn1), ((track1, trkend1,0YDS, 258.5YDS), trkend1)};
) @@@@
@@@ L2A-8 @@
ROUTE:: R263A (M);
(( TYPE: HAND;
INTERLOCKING: MANAIR;
ENTRANCE: SMP263;
EXIT: SMP265:
OVERLAP: OAEE;
LENGTH: 915.75YDS;
SPEED_RESTRICTION-LIST: airport_station_area, airport_down;
D_I_SECTION: {((track1,0.894,1), pn1), ((track3,0,1), pn3), ((track7,0,0.589), trkbnd1)};
D_M_SECTION: {((track1, pn1,0YDS, 27.5YDS), pn1), ((track3, pn3,0YDS, 288.75YDS), pn3), ((track7, pn3,0YDS, 599.5YDS), trkbnd1)};
) @@@@
@@@ L2A-9 @@
ROUTE:: R263A (S);
(( TYPE: SHUNT;
INTERLOCKING: MANAIR;
ENTRANCE: SMP263;
EXIT: SMP265;
LENGTH: 915.75YDS;
SPEED_RESTRICTION-LIST: airport_station_area, airport_down;
D_I_SECTION: {((track1,0.894.1), pn1), ((track3,0,1), pn3), ((track7,0,0.589), trkbnd1)};
D_M_SECTION: {((track1, pn1,0YDS, 27.5YDS), pn1), ((track3, pn3,0YDS, 288.75YDS), pn3), ((track7, pn3,0YDS, 599.5YDS), trkbnd1)};
) @@@@

@@@ L2A-10 @@
ROUTE:: R1002A (S);
{
TYPE: SHUNT;
INTERLOCKING: MANAIR;
ENTRANCE: SMP1002;
EXIT: bufstop2;
LENGTH: 563.75YDS;
SPEED_RESTRICTION-LIST: airport_station_area;
D_I_SECTION: [((track7,0,0.011), pn3), ((track5,0,1), pn4), ((track6,0,1), pn2), ((track2,0,1), trkend2));
D_M_SECTION: [((track7, pn3,0YDS, 11YDS), pn3), ((track5, pn4,0YDS, 118.25YDS), pn4), ((track6, pn2,0YDS, 41.25YDS), pn2), ((track2, trkend2,0YDS, 393.25YDS), trkend2));
) @@@@
@@@ L2A-11 @@
ROUTE:: R1002B (S);
{
TYPE: SHUNT;
INTERLOCKING: MANAIR;
ENTRANCE: SMP1002;
EXIT: bufstop1;
LENGTH: 558.25YDS;
SPEED_RESTRICTION-LIST: airport_station_area;
D_I_SECTION: (((track7,0,0,11), pn3), ((track3,0,1), pn1), ((track1,0,1), trkend1)];
D_M_SECTION: [((track7, pn3,0YDS, 11YDS), pn3), ((track3, pn1,0YDS, 288.75YDS), pn1), ((track1, trkend1,0YDS, 258.5YDS), trkend1));
) @@@@
@@@ L2A-12 @@
OVERLAP:: OAEE;
{
INTERLOCKING: MANAIR;
SIGNAL: SMP265;
TYPE_SECTION-LIST: {FULL, {((track7,0.595,0.814), trkbnd1)], {((track7, pn3,605YDS, 827.75YDS), trkbnd1)));
}
@@@@
@@@ L2A-13 @@
SPEED_RESTRICTION:: airport_station_area;
{
TYPE: BI_DIRECTIONAL;
SPEED-LIST: (FITTED, 40MPH);
I_SECTION: [(track1,0,1), (track2,0,1), (track3,0,1), (track4,0,1), (track5,0,1), (track6,0,1), (track7,0,0.158), (track8,0.758.1)];

M_SECTION: {(track1, trkend1,0YDS, 258.5YDS), (track2, pn2,0YDS, 393.25YDS), (track3, pn1,0YDS, 288.75YDS), (track4, pn1,0YDS, 140.25YDS), (track5, pn4,0YDS, 118.25YDS), (track6, pn4,0YDS, 41.25YDS), (track7, pn3,0YDS, 160.75YDS), (track8, pn4,0YDS, 273.5YDS)};
) @@@@
@@@ L2A-14 @@
SPEED_RESTRICTION:: airport_down;
(( TYPE: DIRECTIONAL;
SPEED-LIST: (FITTED, 60MPH);
D_I_SECTION: {((track7,0.158,1), trkbnd1)};
D_M_SECTION: {((track7, pn3,160.75YDS, 1017.5YDS), trkbnd1)};
) @@@@
@@@ L2A-15 @@
SPEED_RESTRICTION:: airport_up;
(( TYPE: DIRECTIONAL;
SPEED-LIST: (FITTED, 60MPH);
D_I_SECTION: {((track8,0,0.758), pn4)};
D_M_SECTION: {((track8, trkbnd2,0YDS, 856.75YDS), pn4)};
) @@@@
/ * Level 2B - Civil Features * /
@@@ L2B-1 @@
OVER_BRIDGE:: bridge1;
(( I_SECTION-LIST: {(track1,0.404,0.553)}, {(track2,0.636,0.734)};
M_SECTION-LIST: {(track1, trkend1,104.5YDS, 143YDS)}, {(track2, trkend2,104.5YDS, 143YDS)};
) @@@@
@@@ L2B-2 @@
PLATFORM:: platform2;
(( FEATURE: manchester_airport_station;
TEXT: "PLATFORM 2";
I_SECTION: {(track1,0.011,0.894)};
M_SECTION: {(track1, trkend1,2.75YDS, 231YDS)};
) @@@@
@@@ L2B-3 @@
PLATFORM:: platform1;
(( FEATURE: manchester_airport_station;
TEXT: "PLATFORM 1";
I_SECTION: [(track2,0.413,0.993}];
M_SECTION: [(track2, trkend2,2.75YDS, 231YDS}];
}
@@@@

/ * Level 2C - Traction Features * /
/ * Level 3A - Signaling Equipment * /
@@@ L3A-1 @@
SIGNAL:: SMP261;
[
TYPE: CONTROLLED;
INTERLOCKING: MANAIR;
SSI_LABEL: S261;
APPEARANCE: RED, YELLOW, GREEN, SUBSIDIARY;
D_I_LOCATION: ((track2,0.413), pn2);
D_M_LOCATION: ((track2, trkend2,231YDS), pn2);
}
@@@@
@@@ L3A-2 @@
SIGNAL:: SMP262;
[
TYPE: CONTROLLED;
INTERLOCKING: MANAIR;
SSI_LABEL: S262;
APPEARANCE: RED, YELLOW, SUBSIDIARY;
MULTI_LAMP: R262 (M), R262A (C), R262B (M), R262B (C);
D_I_LOCATION: ((track8,0.582), pn4);
D_M_LOCATION: ((track8, trkbnd2,657.25YDS), pn4);
]
@@@@
@@@ L3A-3 @@
SIGNAL:: SMP263;
(( TYPE: CONTROLLED;
INTERLOCKING: MANAIR;
SSI_LABEL: S263;
APPEARANCE: RED, YELLOW, GREEN, SUBSIDIARY;
D_I_LOCATION: ((track1,0.894), pn1);
D_M_LOCATION: ((track, trkend1,231YDS), pn1);
) @@@@
@@@ L3A-4 @@
SIGNAL:: SMP265;
(( TYPE: CONTROLLED;
INTERLOCKING: MANAIR;
SSI_LABEL: S265;
APPEARANCE: RED, YELLOW, GREEN;
D_I_LOCATION: ((track7,0.589), trkbnd1);
D_M_LOCATION: ((track7, pn3,599.5YDS), trkbnd1);
]
@@@@
@@@ L3A-5 @@
SIGNAL:: SMP1002;
(( TYPE: SHUNT;
INTERLOCKING: MANAIR;
SSI_LABEL: S1002;
STATE: ON, OFF;
D_I_LOCATION: ((track7,0.011), pn3);

D_M_LOCATION: ((track7, pn3,11YDS), pn3);
}
@@@@
@@@ L3A-6 @@
POINT_MACHINE:: PMP2205B;
{
TYPE: CLAMPLOCK;
INTERLOCKING: MANAIR;
SSI_LABEL: P2205B;
NODE: pn1;
COMMON: track1;
NORMAL: track3;
REVERSE: track4;
]
@@@@
@@@ L3A-7 @@
POINT_MACHINE:: PMP2205A;
(( TYPE: CLAMPLOCK;
INTERLOCKING: MANAIR;
SSI_LABEL: P2205A;
NODE: pn2;
COMMON: track6;
NORMAL: track2;
REVERSE: track4;
) @@@@
@@@ L3A-8 @@
POINT_MACHINE:: PMP2206A;
{
TYPE: CLAMPLOCK;
INTERLOCKING: MANAIR;
SSI_LABEL: P2206A;
NODE: pn3;
COMMON: track7;
NORMAL: track3;
REVERSE: track5;
}
@@@@
@@@ L3A-9 @@
POINT_MACHINE:: PMP2206B;
{
TYPE: CLAMPLOCK;
INTERLOCKING: MANAIR;
SSI_LABEL: P2206B;
NODE: pn4;
COMMON: track6;
NORMAL: track8;
REVERSE: track5;
}
@@@@
@@@ L3A-10 @@
TC_JOINT:: ibj1;
(( TYPE: ORDINARY;
I_LOCATION: (track1,0.011);
M_LOCATION: (track1, trkend1,2.75YDS);

?
@@@@
@@@ L3A-11 @@
TRACK_CIRCUIT:: TMPAEA;
(( TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TAEA;
I_SECTION:? (Track1,0.011,0.447));
M_SECTION:? (Track1, trkend1,2.75YDS, 115.5YDS));
?
@@@@
@@@ L3A-12 @@
TC_JOINT:: ibj2;
?
TYPE: ORDINARY;
I_LOCATION:? Track1,0.447);
M_LOCATION:? Track1, trkend1,115,5YDS);
?
@@@@
@@@ L3A-13 @@
TRACK_CIRCUIT:: TMPAEB;
?
TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TAEB;
I_SECTION: ((track1,0.447,0.968));
M_SECTION: ((track1, trkend1,115.5YDS, 250.25YDS));
) @@@@
@@@ L3A-14 @@
TC_JOINT:: ibj3;
?
TYPE: ORDINARY;
I_LOCATION: (track1,0.968);
M_LOCATION: (track1, trkend1,250.25YDS);
?
@@@@
@@@ L3A-15 @@
TRACK_CIRCUIT:: TMPAEC;
?
TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TAEC;
I_SECTION:? (Track1,0.968,1), (track3,0,1), (track4,0,0.49), (track5,0.512.1), (track7,0,0.02)];
M_SECTION:? (Track1, trkend1,250.25YDS, 258.5YDS), (track3, pn1,0YDS, 288.75YDS), (track4, pn1,0YDS, 68.75YDS), (track5, pn4,60.5YDS, 118.25YDS), (track7, pn3,0YDS, 5.5YDS)};
) @@@@

@@@ L3A-16 @@
TC_JOINT:: ibj4;
(( TYPE: ORDINARY;
I_LOCATION: (track7,0.02);
M_LOCATION: (track7, pn3,5.5YDS);
]
@@@@
@@@ L3A-17 @@
TRACK_CIRCUIT:: TMPAED;
(( TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TAED;
I_SECTION: ((track7,0.02,0.595));
M_SECTION: ((track7, pn3,5.5YDS, 605YDS));
) @@@@
@@@ L3A-18 @@
TC_JOINT:: ibj5;
(( TYPE: ORDINARY;
I_LOCATION: (track7,0.595);
M_LOCATION: (track7, pn3,605YDS);
) @@@@
@@@ L3A-19 @@
TRACK_CIRCUIT:: TMPAEE;
(( TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TAEE;
I_SECTION: ((track7,0.595,0.814));
M_SECTION: ((track7, pn3,605YDS, 827.75YDS));
]
@@@@
@@@ L3A-20 @@
TC_JOINT:: ibj6;
{
TYPE: ORDINARY;
I_LOCATION: (track7,0.814);
M_LOCATION: (track7, pn3,827.75YDS);
) @@@@
@@@ L3A-21 @@
TC_JOINT:: ibj7;
]
TYPE: ORDINARY;
I_LOCATION: (track8,0.479);
M_LOCATION: (track8, trkbnd2,541.75YDS);
}
@@@@
@@@ L3A-22 @@
TRACK_CIRCUIT:: TMPABG;
{
TYPE: DC;

INTERLOCKING: MANAIR;
SSI_LABEL: TABG;
I_SECTION: [(track8,0.479,0.584)];
M_SECTION: [(track8, trkbnd2,541.75YDS, 660YDS));
) @@@@
@@@ L3A-23 @@
TC_JOINT:: ibj8;
(( TYPE: ORDINARY;
I_LOCATION: (track8,0.584);
M_LOCATION: (track8, trkbnd2,660YDS);
) @@@@
@@@ L3A-24 @@
TRACK_CIRCUIT:: TMPABJ;
(( TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TABJ;
I_SECTION: [(track8,0.584,0.759}];
M_SECTION: [(track8, trkbnd2,660YDS, 858YDS)];
) @@@@
@@@ L3A-25 @@
TC_JOINT:: ibj9;
) TYPE: ORDINARY;
I_LOCATION: (track8,0.759);
M_LOCATION: (track8, trkbnd2,858YDS);
) @@@@
@@@ L3A-26 @@
TC_JOINT:: ibj10;
(( TYPE: ORDINARY;
I_LOCATION: (track5,0.512);
M_LOCATION: (track5, pn4,60.5YDS);
) @@@@
@@@ L3A-27 @@
TC_JOINT:: ibj11;
(( TYPE: ORDINARY;
I_LOCATION: (track4,0.49);
M_LOCATION: (track4, pn1,68.75YDS);
) @@@@
@@@ L3A-28 @@
TRACK_CIRCUIT:: TMPABL;
(( TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TABL;
I_SECTION: [(track2,0,0.406), (track4,0.49.1), (track5,0,0.512), (track6,0,1), (track8,0.759.1));
M_SECTION: ((track2, pn2,0YDS, 159.5YDS), (track4, pn1,68.75YDS, 140.25YDS), (track5, pn4,0YDS, 60.5YDS), (track6, pn4,0YDS, 41.25YDS), (track8, trkbnd2,858YDS, 1130.25YDS)};
}
@@@@
@@@ L3A-29 @@
TC_JOINT:: ibj12;
(( TYPE: ORDINARY;
I_LOCATION: (track2,0.406);
M_LOCATION: (track2, pn2,159.5YDS);
}
@@@@
@@@ L3A-30 @@
TRACK_CIRCUIT:: TMPABP;
{
TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TABP;
I_SECTION: {(track2,0.406,0.706)};
M_SECTION: {(track2, pn2,159.5YDS, 277.75YDS)};
) @@@@
@@@ L3A-31 @@
TC_JOINT:: ibj13;
(( TYPE: ORDINARY;
I_LOCATION: (track2,0.706);
M_LOCATION: (track2, pn2,277.75YDS);
}
@@@@
@@@ L3A-32 @@
TRACKC_CIRCUIT:: TMPABR;
[
TYPE: DC;
INTERLOCKING: MANAIR;
SSI_LABEL: TABR;
I_SECTION: [(track2,0.706,0.993)];
M_SECTION: [(track2, pn2,277.75 YDS, 390.5YDS)];
) @@@@
@@@ L3A-33 @@
TC_JOINT:: ibj14;
(( TYPE: ORDINARY;
I_LOCATION: (track2,0.993);
M_LOCATION: (track2, pn2,390.5YDS);
}
@@@@
@@@ L3A-34 @@
BUFFER_STOP:: bufstop1;

(( D_I_LOCATION: ((track1,0), trkend1);
D_M_LOCATION: ((track1, trkend1,0YDS), trkend1);
) @@@@
@@@ L3A-25 @@
(( D_I_LOCATION: ((track2,0), trkend2);
D_M_LOCATION: ((track2, trkend2,0YDS), trkend2);
) @@@@
@@@ L3A-36 @@
AWS_EQUIPMENT :: SMP265I;
(( TYPE: DIRECTIONAL;
INTERLOCKING: MANAIR;
SSI_LABEL: S265;
D_I_LOCATION: ((track7,0.392), trkbnd1);
D_M_LOCATION: ((track7, pn3,398.75YDS), trkbnd1);
) @@@@
@@@ L3A-37 @@
SSI_TFM :: tfm01;
(( TYPE: SIGNAL;
INTERLOCKING: MANAIR:
NUMBER: 1;
LOC_CASE: 1oc2;
) @@@@
@@@ L3A-38 @@
SSI_TFM :: tfm02;
(( TYPE: SIGNAL;
INTERLOCKING: MANAIR;
NUMBER: 2;
LOC_CASE: 1oc2;
) @@@@
@@@ L3A-39 @@
SSI TFM :: tfm05;
(( TYPE: POINTS;
INTERLOCKING: MANAIR;
NUMBER: 5;
LOC_CASE: 1oc3;
) @@@@
@@@ L3A-40 @@
SSI_TFM :: tfm06;
(( TYPE: POINTS;
INTERLOCKING: MANAIR;
NUMBER: 6;
LOC_CASE: 1oc4;

?
@@@@
@@@ L3A-41 @@
SSI_TFM :: tfm07;
(( TYPE: SIGNAL;
INTERLOCKING: MANAIR;
NUMBER: 7;
LOC_CASE: loc4;
?
@@@@
@@@ L3A-42 @@
SSI_TFM :: tfm08;
?
TYPE: SIGNAL;
INTERLOCKING: MANAIR;
NUMBER: 8;
LOC_CASE: loc5;
?
?
@@@@
@@@ L3A-43 @@
SSI_TFM :: tfm09;
?
TYPE: SIGNAL;
INTERLOCKING: MANAIR;
NUMBER: 9;
LOC_CASE: loc6;
?
@@@@
/ * Level 3B - Auxiliary Equipment * /
@@@ L3B-1 @@
DISTANCE_POST :: dp1;
?
TYPE: MILE;
DISTANCE: 0MILES;
D_I_LOCATION:? (Track1,0), pn1);
D_M_LOCATION:? (Track1, trkend1,0YDS), pn1);
?
@@@@
@@@ L3B-2 @@
DISTANCE_POST :: dp2;
?
TYPE: QUARTER_MILE;
DISTANCE: 0.25MILES;
D_I_LOCATION: (? Track3,0.629), pn3);
D_M_LOCATION: (? Track1, pn1,181.5YDS), pn3);
?
@@@@
@@@ L3B-3 @@
POST DISTANCE :: dp3;
(( TYPE: QUARTER_MILE;
DISTANCE: 0.5MILES;
D_I_LOCATION: (? Track7,0.327), trkbnd1);
D_M_LOCATION: (? TRACK7, PN3,332,75YDS), trkbnd1);

) @@@@
@@@
L3B-4 @@
DISTANCE_POST :: dp4;
(( TYPE: QUARTER_MILE;
DISTANCE: 0.75MILES;
D_I_LOCATION: ((track7,0,759), trkbnd1);
D_M_LOCATION: ((track7, pn3,772.75YDS), trkbnd1);
) @@@@
@@@ L3B-6 @@
LOC_CASE :: 1oc2;
INTERLOCKING: MANAIR;
TEXT: "0M22";
ASSOCIATED_WITH: tfm01, tfm02;
I_LOCATION: (track1,0.851);
M_LOCATION: (track1, trkend1,220YDS);
) @@@@
@@@ L3B-7 @@
LOC_CASE :: 1oc3;
(( INTERLOCKING: MANAIR;
TEXT: "0M32";
ASSOCIATED_WITH: tfm051;
I_LOCATION: (track3,0.213);
M_LOCATION: (TRACK3, pn1,61.5YDS);
) @@@@
@@@ L3b-8 @@
LOC_CASE :: 1oc4;
(( INTERLOCKING: MANAIR;
TEXT: "0M49";
ASSOCIATED_WITH: tfm06, tfm07;
I_LOCATION: (track3,0.802);
M_LOCATION: (track3, pn1,231.5YDS);
) @@@@
@@@ L3B-9 @@
LOC_CASE :: 1oc5;
(( INTERLOCKING: MANAIR;
TEXT: "0M90";
ASSOCIATED_WITH: tfm08;

I_LOCATION: (track7,0.347);
M_LOCATION: (track7, pn3,352.75YDS);
) @@@@
@@@ L3B-10 @@
LOC_CASE :: 1oc6;
(( INTERLOCKING: MANAIR;
TEXT: "0M113";
ASSOCIATED WITH: tfm09;
I_LOCATION: (track7,0.573);
M_LOCATION: (track7, pn3,582.75YDS);
) @@@@
/ * Level 3C - Traction Equipment * /

Annex 2 AUTOMATO? EntSigLog ====================

Sets:
----Aut / * Global set of automata Route / * Global set of routes Message / * Global set of messages ? Back / * Local set of automata? Entrance / * Local set of routes ? Exits / * Local set of routes ? Overlap / * Local set of routes ? Last / * Local set of routes Constants:
---------Sig / * Signal Tim / * Timer Sys / * Signalman system Back / * Backstream Up / * Upstream Dn / * Downstream Input Messages:
--------------iChk [Sig] (route, sigchk, filchk) / * Signal checking iOut [Tim] (route) / * Time-out iReq [Sys] (route) / * Route request ifree [sys] (route) / * route release iRelease [Sys] (route) / * Route release !! Warning iMode [Sys] (route, mode) / * Route setting mode iApp [Up] (route, trachk) / * Approach iReq [Up] (route) / * Route request iCtrl [Up] (route, rtechk) / * Route control iChk [Up] (route, rtechk) / * Route checking Ifree [Up] (route) / * Route cancellation iApp [Dn] (route, trschk) / * Approach iConf [Dn] (aut, route, route) / * Route conflict iReq [Back] (route) / * Route request iCtrl? Back? (route? rt? chk) / * Rout? control iCh? ? Back? (Rout?, Rt? Chk) / * Rout? ch? cking ifr ?? ? Back? (Rout?) / * Rout? c? nc? llation Output Messages:
---------------oCtrl [Sig] (rout?,? igctrl) / * Sign? l control Where are we? ] (rout?, ti ??) / * Ti ?? r on oBad? Sy? ] (m ???) / * Bad m ??? age oAlloc [Sys] (rout?) / * Rout? allowance? d oS? t [Sys] (rout?) / * Rout? ?? t oFr ?? ? Sys] (rout?) / * Rout? r? l ???? d oConf [Sys] (? ut, rout?, rout?) / * Rout? conflict oMod? ? Sys? (Rout ?, mod?) / * Rout? s? tting mod?
oApp? Up? (rout?, tr? chk) / * Approach oConf? Up] (aut, rout?, rout?) / * Rout? conflict oApp [Dn? (rout?, tr? chk) / * Appro? ch oR? q? Dn? (rout?) / * Rout? qu? st?
oCtrl? Dn? (rout?, rt? chk) / * Rout? control oChk [Dn] (rout?, rt? chk) / * Rout? ch? cking oFr ?? ? Dn] (rout?) / * Rout? r? l ????
oR? q [back? (rout?) / * Rout? request oCtrl? back] (route, rt? chk) / * Rout? control oChk? back] (route, rt? chk) / * Rout? ch? cking oFr ?? ? back] (rout?) / * Rout? r? as?
? naked? r? t?
---------? Mod? = {??, P?} / * Rout? mod?
? SigCtrl = {Red,? L, Gn} / * Sign? L control ? SigChk = {Red,? L, Gn} / * Sign? L ch? C? Ing ? FilChk = {? LGn,? L, Gn} / * Filament ch? Cking ?? rSig = {nil, Red,? lGn} / * Exit? ign? l ? PntChk = {O?,? O?} / * Point? ch? c? ing ? Tr? Chk = {O?,? O?} / * Tr? Ck ?? ction ch? C? Ing / * ExSig PntChk Bl? Trs F? TTrc S? CTrc ? Rt? Chk =? ExSig x? PntChk x? Tr? Chk x? Tr? Chk x? Tr? Chk Functions:

---------get_time (route) in Integer / * Timer manager get_back (route) in? Back / * Back manager Constant value:
RteChkInit = (nil, OK, OK, OK, OK) in? RtsChk / * Route checking RteChkOkred = (Red, OK, OK, OK, OK) in? RtsChk / * Route checking RteChkOKY1Gn = (YlGn, OK, OK, OK, OK) in? TrsChk / * Route checking AppTrsOK = OK in? TrsChk / * Approach checking AppTrsOK = NOK in? TrsChk / * Approach checking State values:
------------Entr = nil in {nil} U? Entrance / * Route identifier Exit = {} included in? Exit / * Route identifier Over = {} included in? Overlap / * Route identifier Last = {} included in? Last / * Route identifier Mode = AR in? Mode / * Automatic release ExSig = Red in? ExSig / * Exit signal SigChk = Red in? SigChk / * Signal checking FilChk = T1Gn in? FilChk / * Filament Checking States:
------a set request free-request control free-control checking checked first-track second-track canceled cancellation delayed PROGRAM
Local:
aut = nil in {nil} U Aut rte = nil in {nil} U Route mess = nil in {nil} U Message back = nil in {nil} U? Back entr = nil in {nil} U? Entrance exit = nil in {nil} U? Exit over = nil in {nil} U? Overlap last = nil in {nil} U? Last mode = AR in? Mode exsig = Red in? ExSig sigchk = Red in? SigChk filchk = Y1Gn in? FilChk pntchk = OK in? PntChk trschk = OK in? TrsChk ftrcchk = OK in? TrsChk strcchk = OK in? TrsChk rtschk = Ok in? Rtschk FOR EVERY STATE:
receipt: iApp [Up] (rte, trschk) sending: oApp [Dn] (rte, trschk) receipt: iApp [Dn] (rte, trschk) sending: oApp [Up] (rte, trschk) _ receipt: iReq [Up] (exit) condition: exit not in sLast exec: add (exit, Exit) sending: oReq [Dn] (exit) receipt: iReq [Up] (over) condition: over not in sLast exec: add (over, Over) sending: oReq [Dn] (over) recipt: iReq [Up] (last) exec: add (last, Last) back = get_back (last) sending: oReq [back] (last) _ receipt: iCtrl [Up] (exit, rtschk) condition: exit not in sLast exit in Exit exec: rtschk.ex? ig = ExSig sending: oCtrl [Dn] (exit, rtschk) receipt: iCtrl [Up] (over, rtschk) condition: over not in sLast over in over sending: oCtrl [Dn] (over, rtschk) receipt: iCtrl [Up] (last, rtschk) condition: last in Last last in? Exit exec: back = get_back (last) rtschk.exsig = ExSig sending: oCtrl [back] (last, rtschk) receipt: iCtrl [Up] (last, rtschk) condition: last in Last last not in sExit exec: back = get_back (last) sending: oCtrl [back] (last, rtschk) _ receipt: iChk [Up] (exit, rtschk) condition: exit not in sLast exit in Exit exec: oChk [Dn] (exit, rtschk) receipt: iChk [Up] (over, rtschk) condition: over not in sLast over in over sending: oChk [Dn] (over, rtschk) receipt: iChk [Up] (last, rtschk) condition: last in Last last in sExit exec: back = get_back (last) rtschk.exsig = ExSig sending: oChk [back] (last, rtschk) receipt: iChk [Up] (last, rtschk) condition: last in Last last not in sExit exec: back = get_back (last) sending: oChk [back] (last, rtschk) _ receipt: iFree [Up] (exit) condition: exit not in sLast exit in Exit exec: sub (exit, Exit) sending: oFree [Dn] (exit) receipt: iFree [Up] (over) condition: over not in sLast over in over exec: sub (over, Over) sending: oFree [Dn] (over) receipt: iFree [Up] (last) condition: last in Last exec: sub (last, Last) back = get_back (last) sending: oFree [back] (last) receipt: iConf [Dn] (aut, rte, exit) condition: exit not in sLast exit in Exit exec: sub (exit, Exit) sending: oConf [Up] (aut, rte, exit) receipt: iConf [Dn] (aut, rte, over) condition: over not in sLast over in over erec: sub (over, Over) sending: oConf [Up] (aut, rte, over) _ receipt: iFree [Back] (rte) sending: oFree [Sys] (rte) _ ELSE

INITIAL STATE UNSET:
Entr = nil Mode = AR
receipt: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk receipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigchk FilChk = filchk sending: oCtrl [Sig] (Entr, Red]
_ receipt: iReq [Sys] (entr) exec: Entr = entr transit: request sending: oReq [Dn] (Entr) _ receipt: mess sending: oBad [Sys] (mess) _ STATE request:
receipt: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk receipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigchk FilChk = filchk sending: oCtrl [Sig] (Entr, Red) _ receipt: iFree [Sys] (Enter) transit: free-request receipt: iMode [Sys] (Entr, mode) exec: Mode = mode sending: oMode [Sys] (Entr, mode) _ recipt: iConf [Dn] (Entr) transit: unset sending: oConf [Sys] (Entr) _ receipt: iReq [Back] (Entr) transit: control sending: iAlloc [Sys] (Entr) oCtrl [Dn] (Entr, RteChkInit) _ receipt: mess sending: oBad [Sys] (mess) _ STATE en - request:
r? c? ipt: iCh? [Sig] (Entr, R? D, filch?) ? x? c: ExSig = R? d SigCh? = R? D
FilCh? = filch?
receipt: iCh? [Sig] (Entr,? Igch?, Filch?) condition:? igch? ! = R? D
? x? c: ExSig = R? d SigCh? =? igch?
FilCh? = filch?
?? nding: oCtrl [Sig] (Entr, R? d) _ r? c? ipt: iConf? Dn] (? ut, rt?, Entr) tran? it: a ?? t ?? nding: oFr ?? [S ?? ] (Entr) _ r? c? ipt: iR? q? B? c?] (Entr) tr? n? it: a ?? t ?? nding: oFr ?? ? Dn? (Entr) _ r? c? ipt: m ???
?? nding: oB? d [Sys] (mess) _ STATE control:
r? c? ipt: iCh? [Sig] (Entr, R? D, filchk) ? x? c: ExSig = R? d SigCh? = R? D
FilCh? = filch?
r? c? ipt: iCh? [Sig] (Entr,? Igch?, Filch?) condition:? igch? ! = R? D
? x? c: E? Sig = R? d SigCh? =? igch?
FilCh? = filch?
?? nding: oCtrl [Sig] (Entr, R? d) _ r? c? ipt: ifr ?? [Sys] (Entr) tr? n? it: fr ?? - control receipt: iMode [Sys] (Entr, mode) exec: Mode = mode sending: oMode [Sys] (Entr, mode) _ receipt: iCtrl [Back] (Entr, rtschk) condition: rtschk.exsig == nil transit: unset sending: oFree [Dn] (Entr) receipt: iCtrl [Back] (Entr, rtschk) condition: rtechk.exsig! = nil rtschk.pntchk == OK
transit: checked sending: oSet [Sys] (Entr) oCtrl [Sig] (Entr, Red) receipt: iCtrl [Back] (Entr, rtschk) condition: rtschk.exsig! = nil sending: oCtrl [Dn] (Entr, RteChkInit) _ receipt: mess sending: oBad [Sys] (mess) _ STATE free-control:
receipt: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk receipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigcht FilChk = filchk sending: oCtrl [Sig] (Entr, red) _ receipt: iCtrl [Back] (Entr, rtschk) transit: unset sending: oFree [Dn] (Entr) _ receipt: mess ?? nding: oB? d [S ?? ] (????) _ STATE each?
r? c? ipt: iCh? [Sig] (Entr, R? D,? Ilch?) ? x? c: E? Sig = R? d SigCh? = R? D
FilCh? = filch?
tran? it: ch? c? ing ?? nding: oCh? [Dn] (Entr, Rt? Ch? Init) r? c? ipt: iCh? ? Sig] (Entr,? Igch?, Filch?) condition:? igch? ! = R? D
? x? c: E? Sig =? lGn SigCh? =? igch?
FilCh? = filch?
tr? n? it: ch? c? ing ?? nding: oCh? [Dn] (Entr, Rt? Ch? Init) _ r? c? ipt: ifr ?? ? S ?? ] (Entr) tr? n? it: c? nc? ll? tion ?? nding: oCtrl [Sig] (Entr, R? d) oApp? Up] (Entr, AppTr? O?) r? c? ipt: iMod? ? S ?? ? (Entr, mod?) ? x? c: Mod? =? od?
?? nding: oMod? ? S ?? ? (entry, mod?) _ r? c? ipt: ????
?? nding: oB? d? S ?? ] (????) _ STATE ch? C? Ing:
r? c? ipt: iCh? [Sig] (Entr, R? D, filch?) ? x? c: E? Sig = R? d SigCh? = R? D
FilCh? = filch?
r? c? ipt: iCh? ? Sig? (Entr,? Igch?, Filch?) condition:? igch? ! = R? D
? x? c: E? Sig =? lGn SigCh? =? igch?
FilCh? = filch?

receipt: iFree [Sys] (Entr) transit: canceled sending: oCtrl [Sig] (Entr, Red) receipt: iMode [Sys] (Entr, mode) exec: Mode = mode [Sys] (Entr, mode) sending: oMode [Sys] (Entr, mode) _ receipt: iChk [Back] (Entr, RteChkOKYlGn) condition: FilChk == Yl transit: checked sending: oCtrl [Sig] (Entr, Yl) receipt: iChk [Back] (Entr, RteChkOKYlGn) condition: FilChk! = Yl transmit: checked sending: oCtrl [Sig] (Entr, Gn) receipt: iChk [Back] (Entr, RteChkOKRed) condition: SigChk == Gn transit: checked sending: oCtrl [Sig] (Entr, Red) receipt: iChk [Back] (Entr, RteChkOKRed) condition: SigChk! = Gn transit: checked sending: oCtrl [Sig] (Entr, Yl) receipt: iChk [Back] (Entr, rtechk) condition: rtechk! = RteChkOKYlGn rtechk! = RteChkOKRed rtechk.ftrc == OK
transit: checked sending: oCtrl [Sig] (Entr, Red) receipt: iChk [Back] (Entr, rtechk) condition: rtechk.ftrc == NOK
mode == AR
transit: first track sending: oCtrl [Sig] (Entr, Red) _ receipt: mess sending: oBad [Sys] (mess) _ STATE first_track:
recipt: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk sending: oChk [Dn] (Entr, RteChkInit) receipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigchk FilChk = filchk sending: oCtrl [Sig] (Entr, Red) _ receipt: iRelease [Sys] (Entr) transit: unset sending: oFree [Dn] (Entr) receipt: iFree [Sys] (Entr) _ receipt: iChk [Back] (Entr, Rtechk) condition: rtechk. (ftrc, strc) == (NOK, NOK) transit: second_track sending: oChk [Dn] (Entr, RteChkInit) receipt: iChk [Back] (Entr, rtechk) condition: rtechk. (ftrc, strc)! = (NOK, NOK) sending: oChk [Dn] (Entr, RteChkInit) _ recipt: mess sending: oBad [Sys] (mess) _ STATE second_track:
reciept: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk recept: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigCh? =? igch?
FilCh? = filch?
?? nding: oCtrl? Sig] (Entr, R? d) _ r? c? ipt: i ?? l ???? [S ?? ] (Entr) tr? n? it: a ?? t ?? nding: oFr ?? ? Dn] (Entr) r? c? ipt: ifr ?? [S ?? ] (Entr) _ r? c? ipt: iCh? [Back] (Entr, rt? Ch?) condition: rt? ch?. (ftrc, strc) == (OK,? OK) tr? n? it: a ?? t ?? nding: oFr ?? [Dn] (Entr) r? c? ipt: iCh? ? B? Ck] (Entr, rte? H?) condition: rt? ch?. (? trc,? trc)! = (O?,? O?) ?? nding: oCh? [D? ] (Entr, Rt? Ch? Init) _ r? c? ipt: ????
?? nding: o ?? d [S ?? ? (????) _ ST? TE c? Nc? Ll? D:
r? c? ipt: iCh? ? Sig] (Entr, R? D, filch?) ? x? c: E? Sig = R? d SigCh? = R? D
FilCh? = filch?
r? c? ipt: iCh? ? Sig] (Entr,? Igch?, Filchk?
condition:? igch? ! = ?? d ? x? c: E? Sig = R? d SigCh? =? igch?
FilCh? = filch?
?? nding: oCtrl [Sig] (Entr, R? d) _ r? c? ipt: iCh? ? Back] (Entr, rt? Ch?) tr? n? it: c? nc? ll? tion ?? nding: oApp [Up? (Entr, AppTr? O?) _ r? c? ipt: ????
?? nding: oBad [S ?? ? (????) STATE cancellation:
receipt: iChk [Sig] (Entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk receipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigchk sending: oCtrl [Sig] (Entr, Red) _ receipt: iApp [Up] (Entr, AppTrsOK) condition: SigChk == Red transit: unset sending: oFree [Dn] (Entr) receipt: iApp [Up] (Entr, AppTrsOK) condition: SigChk! = Red sending: oApp [Up] (Entr, AppTrsOK) receipt: iApp [Up] (Entr, AppTrs? OK) condition: SigChk == Red transit: delayed sending: oOn [Tim] (Entr, get_time (Entr)) receipt: iApp [Up] (Entr, AppTrs? OK) condition: SigChk! = Red sending: oApp [Up] (Entr, AppTrsOK) _ receipt: mess sending: oBad [Sys] (mess _ State delayed:
receipt: iChk [Sig] (entr, Red, filchk) exec: ExSig = Red SigChk = Red FilChk = filchk recipt: iChk [Sig] (Entr, sigchk, filchk) condition: sigchk! = Red exec: ExSig = Red SigChk = sigchk FilChk = filchk sending: oCtrl [Sig] (Entr, Red) _ receipt: iOut [Tim] (Entr) trasit: unset sending: oFree [Dn] (Entr) _ receipt: mess sending: oBad [Sys] (mess) _ END PROGRAM

Annex 3 ________ AUTOMATO? BlkDevLog =====================
Sets:
----Aut / * Global set of automata Route / * Global set of routes Message / * Global set of messages sApp / * Local set of routes sBlock / * Local set of routes sFirst / * Local set of routes sSecond / * Local set of routes sBerth / * Local set of routes sOverlap / * Local set of routes sLast / * Local set of routes sBuffer / * Local set of routes sBack / * Local set of routes Constants:
---------Dev / * Device Sys / * Signalman system Up / * Upstream Dn / * Downstream Input Messages:
--------------iChk [Dev] (route, devchk, trschk) / * Device checking iRelease [Sys] (route) / * Route release !! Warning iApp [Up] (route, trechk) / * Approach iReq [Up] (route) / * Route request iCtrl [Up] (route, rtechk) / * Route control iChk [Up] (route, rtechk) / * Route checking Ifree [Up] (route) / * Route cancellation iApp [Dn] (route, trechk) / * Approach iConf [Dn] (ant, route, route) / * Route conflict Output Messages:
---------------oCtrl [Dev] (route, devctrl) / * Device control oBad [Sys] (mess) / * Bad message oApp [Up] (route, trschk) / * Approach oConf [Up] (aut, route, route) / * Route conflict oApp [Dn] (route, trschk) / * Approach oReq [Dn] (route) / * Route request oCtrl [Dn] (route, rtechk) / * Route control oChk [Dn] (route, rtechk) / * Route checking oFree [Dn] (route) / * Route release oReq [back] (route) / * Route request oCtrl [back] (route, rtechk) / * Route control oChk [back] (route, rtechk) / * Route checking oFree [back] (route) / * Route release Enumerate:
? DevCtrl = (Rest, Perm) / * Device control eDevChk = {OK,? OK} / * Device checking eExSig = {nil, Red, YlGn} / * Exit signal ePntChk = {OK,? OK} / * Track section checking / * ExSig Pnt BlkTrs FstTrc SecTrc eRteChk = eExSig x ePntChk x eTreChk x sTrsChk x eTrsChk Functions:
ser_rtechk (rts, stechk) in eRteChk / * Route checking manager get_rtechk (route) in eRteChk / * Route checking manager get_back (route) in? Back / * Back manager Constant value:
ApptrsOK = OK in eTrsChk / * Approach checking Apptrs? OK =? OK in etrsChk / * Approach checking Stat values:
Blk = {} included in sBlock / * Route identifier Over = {} included in sOverlap / * Route identifier Last = {} included in sLast / * Route identifier Request = {} / * Set of routes Control = {} / * Set of routes Controll? D = {} / * S? T of rout ??
Ch? C? Ing = {} / * S? T of rout ??
Ch? C ?? d = {} / * S? T of rout ??
Role ???? = {} / * S? T of rout ??
D? VCH? =? Where? in? D? vCh? / * D? Ic? ch? c? ing Very? =? Where? in? Tr? Ch? / * Very? ?? ction ch? c? ing States:
------a ??
request control controll? d checking ch? c ?? d role? ???
PROGR ??
Bl? = {}
O ?? r = {}
L ?? t = {}
Un ?? t = ?? loc? U? O ?? rl? P
Request = {}
Control = {}
Controlled? D = {}
Ch? C? Ing = {}
Check? D = {}
Role ???? = {}
D? VCh? =? Where?
Very? =? Where?
Loc? L:
?? t = nil in {nil} U ?? t rt? = nil in {nil} U Rout?
???? = nil in {nil} UM ???? g?
? pp = nil in {nil} U ?? pp bl? = nil in {nil} U ?? loc?
o ?? r = nil in {nil} U? O ?? rl? p l ?? t = nil in {nil} U? L ?? t b? c? = nil in {nil} U? B? c?

pntch? = Where? in? PntCh?
very = Where? in? Tr? Ch?
ftrcch? = Where? in? Tr? Ch?

strcch? = Where? in? Tr? Ch?
FOR EVERY STATE:
r? c? ipt: iApp [Up? (rt?,? ppTr? O?) condition: Very? == Where?
?? nding: o? pp [Dn] (rt?,? ppTr? O?) r? c? ipt: i? pp [Up] (rt?,? ppTr? O?) ?? nding: o? pp [Dn] (rt?,? ppTr ?? O?) _ r? c? ipt: i? pp [Dn? (rt?,? ppTr ?? O?) condition: Tr? Chk == O?
?? nding: o? pp [Up] (rt?,? ppTr? O?) r? c? ipt: i? pp [Dn] (rt?,? ppTr? O?) condition: Very? ==? Where?
?? nding: o? pp [Dn] (rt?,? ppTr? O?) _ ELSE

STATE an INITIAL:
r? c? ipt: iCh? [D ?? ] (rt?, unveiled, sliced) ? x? c: D ?? Ch? = d? ch?
Very? = very _ r? c? ipt: iR? q? Up] (bl?) condition: bl? not in? L ?? t ? x? c: add (bl?, Bl?) very: request (white) ?? nding: oR? q [Dn] (bl?) r? c? ipt: iR? q? Up] (o ?? r) condition: o ?? r not in? L ?? t ? x? c:? dd (o ?? r, O ?? r) tr? n? it: request (where) ?? nding: oR? q [Dn] (o ??? r) r? c? ipt: iR? q [Up] (l ?? t) exec: add (last, Last) back = get_back (last) transit: reqest (last) sending: oReq (black) (last) _ receipt: mess sending: oBad [Sys] (mess) _ STATE reqest (blk):
receipt: iChk [Dev] (blk, devchk, trschk) exec: DevChk = devchk TrsChk = trschk _ receipt: iCtrl [Up] (blk, retchk) DevChk condition == OK
exec: set_rtechk (blk, rtechk) transit: control (blk) sending: oCtrl [Dev] (blk, Rest) receipt: iCtrl [Up] (blk, rtechk) condition: DevChk == NOK
TrsChk == NOK
exec: set_rtechk (blk, rtechk) transit: control (blk) sending: oCtrl [Dev] (blk, Rest) receipt: iCtrl [Up] (blk, rtechk) condition: DevChk == NOK
condition: TrsChk == OK
exec: set_rtechk (blk, rtechk) transit: control (blk) sending: pCtrl [Dev] (blk, Perm) _ receipt: iFree [Up] (blk) exec: sub (blk, Blk) transit: unset (blk) sending: oFree [Dn] (blk) _ receipt: iConf [Dn] (blk) exec: sub (blk, Blk) transit: unset (blk) sending: oConf [Up] (blk) r? c? ipt: ????
?? nding: oB? d [S ?? ] (????) _ STATE required (ov? R):
r? c? ipt: iCh? [D ?? ] (ov? r, chopped, chopped) ? x? c: D? vCh? = d? vch?
Very? = very _ r? c? ipt: iCtrl? Up] (where ??, rt? ch?) condition: D ?? Ch? == Where?
? x? c: ?? t_rt? ch? (o ?? r, rt? ch?) tr? n? it: control (where?) ?? nding: oCtrl ???? ] (o ?? r, R ?? t) r? c? ipt: iCtrl? Up] (where ??, rt? ch?) condition: D? vCh? ==? Where?
Very? ==? Where?
? x? c: ?? t_rt? ch? (o ?? r, rt? ch?) tr? n? it: control (where?) ?? nding: oCtrl? D ?? ] (o ?? r, R ?? t) r? c? ipt: iCtrl? Up] (where ??, rt? ch?) condition: D ?? Ch? ==? Where?
condition: Very? == Where?
? x? c: ?? t_rt? ch? (o ?? r, rt? ch?) tr? n? it: control (where?) ?? nding: oCtrl [D ?? 0] (o ?? r, P? r?) _ r? c? ipt: ifr ?? [Up] (o ?? r) ? x? c:? ub (o ?? r, O ?? r) tr? n? it: a ?? t (o ?? r) ?? nding: oFr ?? [Dn] (o ?? r) _ r? c? ipt: iConf [Dn] (o ?? r) ? x? c:? ub (o ?? r, O ?? r) tr? n? it: a ?? t (o ?? r) ?? nding: oConf [Up] (o ?? r) _ r? c? ipt: ????
?? nding: oB? d [S ?? ] (????) STATE request (last):
receipt: iChk [Dev] (last, devchk, trschk) exec: DevChk = devchk TrsChk = trschk _ receipt: iCtrl [Up] (last, rtechk) condition: DevChk == OK
exec: set_rtechk (last, rtechk) transit: control (last) sending: oCtrl [Dev] (last, Rest) receipt: iCtrl [Up] (last, rtechk) condition: DevChk == NOK
TrsChk == NOK
exec: set_rtechk (last, rtechk) transit: control (last) sending: oCtrl [Dev] (last, Rest) receipt: iCtrl [Up] (last, rtechk) condition: DevChk == NOK
condition: TrsChk == OK
exec: set_rtechk (last, rtechk) transit: control (last) sending: oCtrl [Dev] (last, Perm) _ receipt: iFree [Up] (last) exec: sub (last, Last) transit: unset (last) exec: back = get_back (last) sending: oFree [back] (last) _ receipt: iConf [Dn] (last) exec: sub (last, Last) transit: unset (last) sending: oConf [Up] (last) _ receipt: mess sending: oBad [Sys] (mess) _ STATE control (bl?):

r? c? ipt: iCh? [D ?? ] (wheat, chopped, chopped) condition: bl? in? Fir? t ? x? c: D ?? Ch? = d? ch?
Very? = very rt? ch? = g? t_rt? ch? (bl?) rt? ch? .pntch? ? = d ?? ch?
rt? ch? .bl? tr? ? = very?
rt? ch? .f? ttrc? = tr? ch?
very: controlled (white) ?? nding: oCtrl? Dn] (bl?, rt? ch?) r? c? ipt: iCh? ? D ?? ] (wheat, chopped, chopped) condition: bl? in? s? cond ? x? c: D ?? Ch? = d? ch?
Very? = very rt? ch? = g? t_r? tch? (bl?) rt? ch? .pntch? ? = d ?? ch?
rt? ch? .bl? tr? ? = very?
rt? ch?.? ndtrc? = tr? ch?
tr? n? it: controll? d (bl?) ?? nding: oCtrl? Dn] (bl?, rt? ch?) _ r? c? ipt: ????
?? nding: oB? d [S ?? ] (????) _ STATE control (o ?? r):
r? c? ipt: iCH? [D ?? ] (o ?? r, chopped, chopped) ? x? c: D ?? Ch = d ?? ch?
Very? = very rt? ch? = g? t_rt? ch? (o ?? r) rt? ch? .pntch? ? = d ?? ch?
tr? n? it: controlled (o ?? r) ?? nding: oCtrl [Dn] (o ?? r, rt? ch?) _ r? c? ipt: ????
?? nding: oB? d [S ?? ] (????) _ STATE control (l ?? t):
r? c? ipt: iCh? [D ?? ] (summer, fall, fall) condition: l ?? t in Bl?
l ?? t in? Buff? r ? x? c: D ?? Ch? = d? ch?
Very? = very rt? ch? = g? t_rt? ch? (l ?? t) rt? ch?. ??? ig? = R? d rt? ch? .pntch? ? = d ?? ch?
rt? ch? .bl? tr? ? = very?
b? c? = g? t_b? c? (l ?? t) tr? n? it: controlled (l ?? t) ?? nding: oCtrl [b? c?] (l ?? t, rt? ch?) r? c? ipt: iCh? [D ?? ] (summer, fall, fall) condition: l ?? t in Bl?
l ?? t not in? Buff? r ? x? c: D ?? Ch? = d? ch?
Very? = very rt? ch? = g? t_rt? ch? (l ?? t) rt? ch? .pntch? ? = d ?? ch?
rt? ch? .bl? tr? ? = very?
b? c? = g? t_b? c? (l ?? t) tr? n? it: controll? d (l ?? t) ?? nding: oCtrl [back] (l, t, rt? ch?) r? c? ipt: iCh? [D ?? ] (summer, fall, fall) condition: l ?? t not in Bl?
? x? c: D ?? Ch? = d? ch?
Very? = very rt? ch? = g? t_rt? ch? (l ?? t) rt? ch? .pntch? ? = d ?? ch?
b? c? = g? t_b? c? (l ?? t) tr? n? it: controll? d (l ?? t) ?? nding: oCtrl [b? c? (l ?? t, rt? ch?) _ r? c? ipt: ????
?? nding: oB? d {S ?? ] (????) _ STATE controlled (bl?):
r? c? ipt: iCh? [D ?? ? (bl?, ch?, tr? ch?) ? x? c: d ?? Ch? = d? ch?
Very? = very _ r? c? ipt: iCtrl [Up] (bl?, rt? ch?) condition: D ?? Ch? == Where?

exec: set_rtschk (blk, rtechk) transit: control (blk) sending: oCtrl [Dev] (blk, Rest) receipt: iCtrl [Up] (blk, rtechk) condition: DevChk == NOK
TrsChk == NOK
exec: set_rtechk (blk, rtechk) transit: control (blk) sending: oCtrl [Dev] (blk, Rest) receitp: iCtrl [Up] (blk, rtechk) condition: DevChk == NOK
TrsChk == OK
exec: set_rtechk (blk, rtechk) transit: control (blk) sending: oCtrl [Dev] (blk, Perm) -receipt: iChk [Up] (blk, rtechk) exec: set_rtechk (blk, rtechk) transit: cheching (blk) sending: oCtrl [Dev] (blk, Rest) _ receipt: iFree [Up] (blk) exec: sub (blk, Blk) transit: unset (blk) sending: oFree (Dn] (blk) _ receipt: mess sending: oBad [Sys] (mess) _ STATE controlled (over):
receipt: iChk [Dev] (over, devchk, trschk) exec: DevChk = devchk TrsChk = trschk -receipt: iCtrl [Up] (over, rtechk) condition: DevChk == OK
exec: set_rtechk (over, rtechk) transit: control (over) sending: oCtrl [Dev] (over, Rest) receipt: iCtrl [Up] (over, rtechk) condition: DevChk == NOK
TrsChk == NOK
exec: set_rtechk (over, rtechk) transit: control (over) sending: oCtrl [Dev] (over, Rest) receipt: iCtrl [Up] (over, rtechk) condition: DevChk == NOK
TrsChk == OK
exec: set_rtechk (over, retchk) transit: control (over) sending: oCtrl [Dev] (over, Perm) _ receipt: iChk [Up] (over, rtechk) exec: set_rtechk (over, rtechk) transit: checking (over) sending: oCtrl [Dev] (over, Rest) _ receipt: iFree [Up] (over) exec: sub (over, Over) transit: unset (over) sending: oFree [Dn] (over) _ receipt: mess sending: oBad [Sys] (mess) _ STATE controlled (last):
receipt: iChk [Dev] (last, devchk, trschk) exec: devChk = devchk TrsChk = trschk _ receipt: iCtrl [Up] (last, rtschk) condition: DevChk == OK
exec: set_rtechk (last, rtechk) transit; control (last) sending: oCtrl [Dev] (last, Rest) receipt: iCtrl [Up] (last, rtechk) condition: DevChk == NOK
TrsChk == NOK
exec: set_rtechk (last, rtechk) transit: control (last) sending: oCtrl [Dev] (last, Rest) receipt; iCtrl [Up] (last, rtechk) condition: DevChk == NOK
TrsChk == OK
exec: set_rtechk (last, rtechk) transit: control (last) sending: oCtrl [Dev] (last, Perm) _ receipt: iFree [Up] (last) exec: sub (last, Last) back = get_back (last) transit: unset (last) sending: oFree [back] (last) _ receipt: mess sending: oBad [Sys] (mess) _ STATE checking (blk):
receipt: iChk [Dev] (blk, devchk, traschk) condition: blk in sFirst exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (blk) rtechk.pntchk? = devchk rtechk.blktrs? = trschk rtechk.fsttrc? = trschk transit: checked (blk) sending: oChk [Dn] (blk, rtechk) receipt; iChk [Dev] (blk, devchk, trschk) condition: blk in sSecond exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (blk) rtechk.pntchk? = devchk rtechk.blktrs? = trschk rtechk.sndtrc? = trschk transit: Checked (blk) sending: oChk [Dn] (blk, rtechk) _ receipt: mess sending: oBad [Sys] (mess) _ STATE checking (over):
receipt: iChk [Dev] (over, devchk, trschk) exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (over) rtechk.pntchk? = devchk transit: checked (over) sending: oChk [Dn] (over, rtechk) _ receipt: mess sending: oBad [Sys] (mess) _ STATE checking (last):
receipt: iChk [Dev] (last, devchk, traschk) condition: last in Blk last in sBuffer exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (last) rtechk.ersig & = Red rtechk.pnthck & = devchk rtechk.blktrs & = trschk back = get_back (last) transit: checked (last) sending: oChk [back] (last, rtechk) receipt: iChk [Dev] (last, devchk, trschk) condition: last in Blk last not in nBuffer exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (last) rtechk.pntchk & = devchk rtechk.blktrs & = traschk back = get_back (last) transit: checked (last) standing: oChk [back] (last, rtechk) receipt: iChk [Dev] (last, devchk, trschk) condition: last not in Blk exec: DevChk = devchk TrsChk = trschk rtechk = get_rtechk (last) rtechk.ontchk & = devchk back = get_back (last) transit: Checked (last) sending: oChk [back] (last, rtechk) _ receipt: mess sending: oBad [Sys] (mess) _ STATE checked (blk):
receipt: iChk [Dev] (blk, devchk, trschk) exec: DevChk = devchk TrsChk = trschk _ receipt: iChk [Up] (blk, rtechk) exec: set_rtechk (blk, rtechk) transit: checking (blk) sending: oCtrl [Dev] (blk, Rest) _ receipt: iFree [Up] (blk) condition: blk in sBerth transit: release (blk) sending: oOn [Tim] (blk, get_time (blk)) oCtrl [Dev] (blk, Rest) receipt: iFree [Up] (blk) condition: blk not in sBerth transit: release (blk) sending: oCtrl [Dev] (blk, Rest) _ receitp: mess sending: oBad [Sys] (mess) _ STATE checked (over):
receipt: iChk [Dev] (over, devchk, trschk) exec: DevChk = devchk TrsChk = trschk _ receipt: iChk [Up] (over, rtechk) exec: set_rtechk (over, rtechk) transit: checking (over) sending: oCtrl [Dev] (over, Rest) _ receipt: mess sending: oBad [Sys] (mess]
_ STATE checked (last):
receipt: iChk [Dev] (last, devchk, trschk) exec: DevChk = devchk TrsChk = trschk _ receipt: iChk [Up] (last, rtechk) exec: set_rtechk (last, rtechk) transit: checking (last) sending: oCtrl [Dev] (last, Rest) _ receipt: iFree [Up] (last) condition: last in sBlock transit: checking (last) sending: oCtrl [Dev] (last, Rest) _ receitp: ifree [Up] (last) condition: last in sBlock transit: release (last) sending: oCtrl [Dev] (last, Rest) receipt: iFree [Up] (last) condition: last in sOverlap exec: sub (last, Last) back = get_back (last) transit: unset (last) sending: oFree [back] (last) receipt: mess sending: oBad [Sys] (mess) _ STATE release (blk):
receipt: iChk [Dev] (blk, dechk, trschk) condition: trschk == NOK
exec: DevChk = devchk TrsChk = trschk transit: release (blk) sending: oCtrl [Dev] (blk, Rest) receipt: iChk [Dev] (blk, devchk, traschk) condition: trschk == OK
exec: DevChk = trschk sub (blk, Blk) transit: unset (blk) sending: oFree [Dn] (blk) _ receipt: iOut [Tim] (blk) exec: sub (blk, Blk) transit: unset (blk) sending: oFree [Dn] (blk) _ receipt: iRelease [Sys] (blk) exec: sub (blk, Blk) transit: unset (blk) sending: oFree [Dn] (blk) _ receipt: mess sending: oBad [Sys] (mess) _ STATE release (last):
receipt: iCHk [Dev] (last, devchk, trschk) condition: trschk == NOK
exec: DevChk = devchk TrsChk = trschk transit: release (last) sending: oCtrl [Dev] (last, Rest) receipt: iChk [Dev] (last, devchk, trschk) condition: trschk == OK
exec: DevChk = devchk TrsChk = trschk sub (last, Last) transit: unset (last) sending: oFree [Dn] (last) _ receipt: iRelease (Sys] (last) exec: sub (last, Last) back = get_back (last) transit: unset (last) sending: oFree [back] (last) _ receipt: mess sending: oBad [Sys] (mess) _ Annex 4