CA2185559A1 - Process and device for equalising the voltage distribution to gate-controlled, series-connected semiconductors - Google Patents
Process and device for equalising the voltage distribution to gate-controlled, series-connected semiconductorsInfo
- Publication number
- CA2185559A1 CA2185559A1 CA002185559A CA2185559A CA2185559A1 CA 2185559 A1 CA2185559 A1 CA 2185559A1 CA 002185559 A CA002185559 A CA 002185559A CA 2185559 A CA2185559 A CA 2185559A CA 2185559 A1 CA2185559 A1 CA 2185559A1
- Authority
- CA
- Canada
- Prior art keywords
- shutoff
- semiconductors
- current
- series
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0824—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in thyristor switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/105—Modifications for increasing the maximum permissible switched voltage in thyristor switches
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a process and a device (14) for equalising the voltage distribution to gate-controlled, series-connected semiconductors (2).
According to the invention, in the on-conditon, predetermined switch-off delays are called depending on the measured value of a load current (iL) and said delays are updated following switch-off depending on a wrong-voltage distribution found. This provides a process and a device (14) for equalising the voltage distribution to gate-controlled, series-connected semiconductors (2), the regulation being always automatically performed according to the latest operating status.
According to the invention, in the on-conditon, predetermined switch-off delays are called depending on the measured value of a load current (iL) and said delays are updated following switch-off depending on a wrong-voltage distribution found. This provides a process and a device (14) for equalising the voltage distribution to gate-controlled, series-connected semiconductors (2), the regulation being always automatically performed according to the latest operating status.
Description
2 1 8 5 5 5 q [67190/943114 ]
PROCESS AND DEVICE ~OR E2n~T~T~TNG THE
VOLTAGE DISTRIBUTION TO GATE-COI~rRnT.T.T~n, SERIES--Cl l N~:~ . r:l) SENICO~DUCTORS
The invention relates to a method and a device for rendering uniform the voltage division in series-~ ~lnnf~l-tl~ gate-controlled semiconductors that have shuto_f times of different lengths.
The term ~gate-controlled semiconductors"
refers here to all æemiconductors that can be turned off and on through their control tl~rm;n~1 q (gates) .
Increasing the operating voltage makes an important contribution to increasing the power of re~-t;f;~r~; connecting power semiconductors in series is one way of doing this. In particular, gate-turn-off (GT0) thyristors are Yaluable as semiconductors in this regard since they have the highest blocking voltage resistance of any semiconductor valves that can be shut of f The main problem in a series circuit lies in the non-identical shutoff behavior of the semiconductor valves, so that they are loaded nonuniformly with blocking voltage. The di~ferences in shuto~f behavior, which make themselves noticeable primarily as different shutof f times, is caused both by variations between individual semiconductors and external parameters such as the shutof f current and temperature . If no other measures are taken, this results in an overdimensioning of the semiconductor valves as well as their circuits, 80 that such circuits become uneconomical and limited in the number of series - connected semiconductor valves .
The switching - on process of series - connected semiconductor valves is relatively uncritical i_ the LITERAI, 'I'R~NS::T.~TTON
OF PCT APPLICATION
r 21 85559 rectif ier circuit in which a limitation of the current rise is always provided is specif ied by the blocking voltage resistance of the semiconductor valves at the moment they are turned on, and if there are only minor 5 differences in the switching-on behavior of the power semiconductors. The static blocking voltage load can be controlled by passive means. The switchiny-on behavior and static blockage will therefore not be discussed further here.
A way must therefore be found to produce uniform dynamic voltage loading of the semiconductor valves during the shutof f process . Preset boundary conditions that must be considered include the rectif ier having to be operated immediately at full voltage and a 15 selection of semiconductor valves or other manual measures having to be avoided. It is also important to note that the shutof f behavior of the semiconductor valves, i.e. particularly the differences in shutoff time, are af f ected by the shutof f current and the 20 temperature as well as the differences in the semiconductors. Therefore, the influence of a shutoff current that changes suddenly must be compensated in the same way as the inf luence of the slowly changing temperature. Another requirement for such a method for 25 rendering uniform the voltage distribution in series-connected power semiconductors is the operating safety of the circuit in all (even improper) states.
Various methods are known for cf-nn~- t;ng semiconductor valves that can be switched off in series, 30 thus ensuring safe switching off. The proposed solutions extend from purely pas~ive methods through methods that require a manual application, and even extend to methods that operate on the basis of regulation.
The purely passive methods include measures 35 such as overdimensioning of switching capacity and overdimensioning of the blocking voltages of the LITERAL 'IIR~Nf~T.~'rrON
r. ~ 21 8~559 semiconductor valves, selection of semiconductor valves for the same shutoff, as well as selection of the controls and switches. This i9 accomplished with the goal of obtaining a blocking voltage distribution that is 5 as uniform and dynamic as possible Manual intervention methods for the circuit are known that employ manual adjustment of the shutoff time points to produce delays in the controls or different gate inductances and thus achieve a uniform blocking 10 voltage distribution in the semiconductor valves These proposed solutions are evidently unable to meet the requirements listed above for a method for series connection of semiconductor valves. Primarily, they make series connection of semiconductor valves 15 appear unec~nomical.
From BP 0 288 422 B1, a method is known for rendering voltage distribution uniform when a series circuit of control semiconductors is shut of f, based on regulation of the blocking voltages of the semirnnrll~t tnr 20 valves, with the shutoff points of the individual semiconductor valves being delayed accordingly by the control. In this method, the actual amplitudes of the anode voltages of the series-connected semiconductor valves are measured and compared to the amplitude of the 25 total voltage of the seri~s- connected semiconductor valves in such fashion that a correction value is formed that ~ rm; n~C: the shutoff delays for the individual semiconductor valves As a result, the voltage dif f erences between the semiconductors in the ideal case 30 are compensated to ~ero. The shutoff of the power semiconductors is performed with a current that is low at the beginning but rises to a full operating current at the end, with the difference between the shutoff currents of two successive shutof f processes correcting the 35 established delay times for the individual semiconductor valves. To generate the delay times for the individual .
LITERBL 'I'T~AIU'2T.~ION
r ~ 2 1 85559 semiconductor valves, difference formers are provided In this way, a signal is generated that is proportional to the measured voltage difference between the actual and the ideal voltage distributions, said signal 5 simultaneously constituting the value of the shutoff delay for the respective semiconductor valve. The regulator thus described therefore has a purely proportional behavior. Different shutoff currents between successive swltching processes are ;ntPnlqPfl, 10 through a current difference former, to produce an additional delay in the shutoff signals in order to compensate f or the inf luence of a changing current This regulating system is useful in semiconductor valves with only a sl ight dependence of their shutof f times on the 15 shutoff current, and generally sturdy in nature, such as for example, power transistors and insulated gate bipolar transistors (IGPT) . In such semicrn~ rtr,r valves, however, an even simpler purely adjusting regulation appears to be possible which, when an P~tPrn~l ly set or a 20 f irmly set voltage of the semiconductor valve in r~uestion is exceeded, delays the shutof f .
The invention has as its goal a method and a device for rendering uniform the voltage distribution in series-connected gate-controlled semiconductors, with 25 which, at each shutoff, the correct delay times for the series-connected gate-controlled semiconductor valves are known sufficiently exactly to ensure a safe shutoff.
This goal is achieved according to the invention by the method features a) to g) of Claim 1 and 3 0 the characterizing f eatures of Claim 4 .
The method according to the invention is based on the division of an admissible shutoff current range of the series - connected gate- controlled semiconductors into several areas, with predetermined delay times available 35 for each area for each of the series-conr~ected semiconductor valves. As a result, even during the ON
LITERAL TT~N~T ~rrION
state, delay times are available for a ~ry current 90 that at every shutoff moment, sufficiently accurate delay times are available for the semiconductor valves.
Since the predetermined delay times are also always 5 updated after shutoff, the delay times always adjust from one switching maneuver to the next to the operation of the rectifier device, whose rectifier valves consist of series-connected gate-controlled semicnn~llr~r,rs. In this method, changing influential parameters such as shutoff 10 current and temperature are taken into account as well.
Thus a method is obtained for rendering uniform the voltage distribution of series-connected gate-controlled semiconductors that automatically adjusts to the latest operating state, thus obtaining a method that can learn.
In one advantageous method, the predetermined shutoff delay times are de~f~rmlnr~l automatically by means of a learning phase. The learning phase of the system differs from the method according to Claim 1 in that in this case the shutof f current is set or limited by the 20 regulating system. In the simplest case, the learning phase proceeds in such fashion that the current rectifier initially is shut off several times in the smallest current range, 90 that by adjusting the delay times for the individual valves, the unequal voltage distribution 25 is corrected approximately to zero. If this takes place in the first current range, this delay time is transferred as an initial value in the next current range . Then the same regulating process takes place f or this higher current until the unequal voltage 30 distribution is again compensated. With corrected dimensioning, a regulating process does not last more than two switching processes. This described method is repeated up to the highest current range. The fact that the existing incorrect distribution can always be kept 35 within limits is based on the constant relationship between the shutof f current and the shutof f time in LITERAL 'I'RPlN~T.~'rION
~ 2 ~ 85559 semiconductor valves. The maximum incorrect voltage distribution during the learning phase can be ~ rmi n.o~l by establishing the current ranges.
In an advantageous device for working the 5 method according to the invention, a microprocessor is provided for working the method, to which microprocessor a measured current value, voltage measured values of the recorded blocking voltage distribution, and the switch-on and switch-off signalE~ are supplied from a pulse lO modulator. This sof tware solution is advisable when the pulse modulator is already using a microprocessor. Then it is even more advantageous for the pulse modulator and the device for working the method according to the invention to constitute a module The device for working the method according to the invention can also be built using discrete regulators . In this connection, a discrete I - regulator is provided for each current range and for each series-connected gate-controlled semiconductor This type of 20 regulator proYides both compensation of parameters that change slowly (temperature for example), as well as the ability to note the correct delay times for the individual semiconductor valves. Each time the valves are switched of f, delay times are available at the output 25 of the regulator, said times consisting of a correction of the times from the previous switching process, with the correction value constituting an amount that is proportional to the incorrect voltage distribution that was present the last time the device was shut off The fact that an independent regulator is associated with each current range provides assurance that delay times will be available during each shutof f process that correspond to the respective shutoff current. This concept, which is also implemented in the software solution, permits any relationship, even a nonlinear one, between the delay times and the shutoff LITERAL 'I'R~I`TC~T.~'T'ION
r ~ 2 185559 current. In addition, it ensures that the correct delay times are immediately available upon shutof f .
The shutof f current is optimally detected by measuring the output current of the rectifier, since when 5 the current direction corresponds, it is identical with the valve current. The advantage of this method lies in the fact that the load current is readily accessible by measuring technology or is usually already available as a potential-free measured value.
The incorrect voltage distribution can be measured f irstly by measuring the anode voltage through a semiconductor valve and then comparing it with a quotient of the total voltage divided by the valves and the number of semiconductors. A second way to measure voltage is to measure only the voltage difference between the individual cathode potentials and a voltage distributor network connected in parallel. These small voltage differences are linked with one another and compensated to zero by the device. A common feature of the methods is that the static blocking voltages are always recorded, in other words no expensive measured-value recorders for dynamic processes must be used.
For further explanation of the invention, reference is now made to the drawing in which a device according to the invention f or working the method is shown schematically, as used for comparison of the voltage distribution of series - connected gate- controlled semiconductor valves.
Figure 1 shows a schematic diagram of an advantageous embodiment of a device according to the invention for the control times of series-connected gate-controlled semiconductors Figure 2 shows a flowchart for learning-capable regulation of the shutoff delay times for series-connected gate- controlled semiconduc'cors in which LITERAL 'I'R~TqT.~'l'ION
OF PCT APPLICA~ION 7 Figure 3 is a schematic diagram of a simple voltage detection device in which Figure 4 shows typical time curves of control signals and control current as well as anode current and anode voltage, plotted against time for two series-connected gate- controlled semiconductors with a shutof f time difference and without compensation, while in Figure 5 the signal graphs are shown, with compensation of the controlled shutoff times plotted as a function of time t.
Figure 1 shows a schematic diagram of a learning-capable regulating system for rendering uniform the voltage division in a series-connected gate-controlled semiconductor 2 with shutof f times of different lengths. Thyristors that can be shut off (GTO-thyristors) are used as gate-controlled semiconductors 2.
These GTO thyristors 2 form one half of a bridge branch of a rectifier circuit, not shown in greater detail.
This rectifier circuit, for example, a 6-pulse inverter, is fed by a DC source of which only one positive intermediate circuit bus is shown. The part of ~he bridge branch that is shown, in addition to the n GTO
thyristors 2, also has a choke 6 for current limitation.
~oad tPrm; n;~l 8 is connected to the midpoint of the bridge branch, said tPrm;n~l having a current converter 10 to detect load current iL. Each semiconductor valve 2 is provided with a device 12 connected electrically in parallel with the valve.
This device 12 ct~nt;linq a known unloading network, for example an RCD circuit, also generally called a~snubber circuit, a resistance of a voltage divider network, and a measured voltage device with which a value of an improper voltage distribution, can be measured. The known RCD clrcuit consists of a series circuit composed of a switching capacitor and a switching LITE-RAL 'I'RbN.qT.~TION
OF PCT ~PPLICATION 8 ~ 2 1 85559 diode connected electrically and in parallel with an ohmic resistance. Voltage distribution in the series circuit of n semiconductor valves 2 is ensured in the steady state by the resistances that are connected in parallel with each semiconductor 2. This steady state, whose voltage distribution is set only slowly by relatively high resistances connected in parallel, is only of real signlf icance when valves 2 are in a prolonged OFF state. On the other hand, the improper voltage dlstribution that occurs immediately after the shutof f process remains almost unchanged during a normal pulse duration, so that this improper distribution is available on a quasi-steady-state basis during the OFF
phase. In addition, each device 12 also has a free-running diode f or the corresponding semiconductor valve ~
2. The output signal, namely the value ~Ul, ~U2,.~ Un 2~ ~U.-l of the improper voltage distribution, is conducted, potential-separated, through one of the n-1 leads to device 14.
The control of the n semiconductor valves 2 ~or turning on and off is accomplished in each case by means of a known driver circuit 16, connected to a control terminal G and a cathode ~ of the gate- controlled semiconductor 2 in question. On the input side, driver circuits 16 are each cr,nnc~rtP~l, potential-separated, with the outputs of device 14.
For potential separation, it i8 r~rt~mmonrll~rl to use voltage-frequency conversion with optocouplers and light pipes or digitization of the measured value to measured potential, with optical transmission of the digital signal . For simpli~ied signal tr;:lncm~ ~sion, it also appears possible to provide only a very coarse measurement of the improper voltage distribution.
Device 14 for rendering the voltage distribution o~ series-rnnnPrt~-l gate-controlled semiconductors 2 uniform is linked on the input side with hITERAL 'T'R~N~T.7~TION
8~
a pulse modulator 18 of the re2c~ifier, 9from which it obtains a control signal E/A (on and off signal) and a start signal StA. From device 14, this modulator 18 obtains a feedback signal RS or R~ regarding the 5 switching state of semiconductor valves 2 and/or the learning phase. Device 14 consists of an asymmetry monitor 20, a control device 22, a computing device 24, an intermediate storage device 26, and an output device 28. Control device 22 is located on the input side in 10 device 14 and receives start signal ST or control signal B/A from pulse modulator 18. In addition, this control device 22 also receives an OFF signal SG and a current measurement signal for the load current iL. The feedback signals RS and R~ for modulator 18 as well as the status 15 signals SI- and SEA for calculating device 24 and a start signal St for output device 28 are generated by control device 22. Calculating device 24 also receives values ~Ul, ....,~Un 1 of the improper voltage distribution and a current measurement signal f or load current iL -The method according to the invention will be described in greater detail with reference to this schematic diagram and the flowchart in Figure 2, and the method according to Claim 1 and then the learning program will be discussed in greater detail.
In calculating device 24, a table with delay times for k current ranges and n semiconductor valves 2 is provided, with these delay times being generated for example by the learning program, which is a 8ub,uLu~Ldll~ of the method according to the invention. During normal operation, control device 22 of device 14 receives a control signal E or A from pulse modulator 18. Then control device 22 activates status signal SEA, resulting in calculating device 24 being placed in the switching mode. Depending on a clock signal, not shown in greater detail, measured values for load current iL are read continuously into calculating device 24, with LITER~L ~R~N~::T~ ION
corresponding delay times being read out for this current measurement range during the next cycle from table n, said times being stored during the next cycle in intermediate storage device 26. '~'hen the control signal 5 of modulator 18 changes from E to A (OFF state), control device 22 generates start signal St, whereupon the n delay times stored in ;nt~ te storage device 26 are taken over into output device 28, so that the n semiconductor valves 2 are each switched of f with their 10 individual delay times. In addition, the level of status signal SEA changes so that the last delay times to be called up are noted.
After the n series-connected gate-controlled semiconductors 2 are shut of f, the delay times noted f or 15 the shutof f current range are updated. This is accomplished as follows: following a period of time to be specified as a function of voltage values for each valve 2, a value ~UI, .... ,~Un l of the improper voltage distribution is formed and fed to asyiTImetry monitor 22 20 and computing device 24. From these values ~U1, ....,i~Un l of the improper voltage distributions, calculating device 24 computes new delay times for this shutoff current range, with an amount being added for the noted delay times that is proportional to a linking of the values 25 ~UI, .... ,~Un l of the improper voltage distribution.
The values ~UI, ...., ~Un 1 of the improper voltage distribution can be linked with one another for example by the f ollowing equation:
UUnsy=.Vi l!'Un l + ~Ui ~ I~Ui l 3 o where n is the nu~nber of valves 2 connected in series and i is the first, second,..., i-th valve 2.
These updated delay times are stored in the table for this shutoff current range, in other words the new delay times overwrite the corresponding stored delay 35 times for this current range. As a result, device 14 continuously adjusts to variable parameters. If a value ~ITERA~ 'I'R~7.`7qT,~TION
OF PCT APP~ICATION 11 f or the improper voltage distribution exceeds a prede~PrminP~ limit, device 14 is shut o~ and notification is provided by an optical signal. Shutoff prevents exce~sive improper voltage distribution during the next switching process from damaging or destroying series - connected gate- controlled valves 2 .
This is the regulating process of device 14 in normal operation, and makes it clear that device 14 has an integrating behavior, as a result of which the control errors, i.e. the unequal voltage distribution, can be compensated to zero . The clock f re~auency or scanning time of device 14 corresponds to the switching time of valves 2.
Instead oi~ the table in calculating device 24, a discrete I-regulator can be used for each table value, since this type of regulator ensures compensation of parameters that change slowly (temperature, for example) as well as the ability to '~note~ the correct delay times for the individual semiconductor valves 2.
Since no delay times are known for semiconductor valves 2 when the rectifier is first switched on, so that a voltage overload can lead to destruction of semiconductor 2 even when it is first switched on, in the method according to the invention the delay times are determined in a so- called learning phase .
The method in the learning phase differs from the method already described in that in the learning phase the cutoff current is specified or limited by a regulating system .
According to the flowchart in ~igure 2, the voltage is equal to the rated voltage, the current value is approximately zero, and the GTO parameters are unknown. Since the parameters of GT0 valves 2 are not known, no shutoff delay times can be stored in device 14.
In the smallest current range k=1, the gate-controlled semiconductors 2 that are connected in series are shut LITERAL TRI~N~T.~TION
2 1 8555q off. The values ~U1, ....,~Un 1 determined for the incorrect voltage distribution are converted by calculating device 24 into delay times. This process can be repeated several times for the lowest current range 5 k=1 80 that the unequal voltage distribution is corrected approximately to zero. This regulating process preferably does not last more than two switching processes. These n delay times flf~ rm;n~l for the first current range are stored in the table of Qlculating lO device 24 and noted as selected delay times for current range k=2. After shutoff has been performed, these noted delay times of current range k=2 are updated by the values ~Ul, .... ,~Un l ~t~rm;n~ for incorrect voltage distribution and stored in the table for the second 15 current range. At the same time, these delay times again constitute the delay times for the next current range k=3. These processes are repeated until the maximum current range k=k is reached.
In each current range k, the shutoffs can be 20 repeated several times so that a very high accuracy is attained in determining the shutof f delay times . During this learning phase of device 14, the current is increased f rom zero to the maximum shutof f current by a regulating device, not shown in greater detail. When n 25 shutoff delay times have been de~ T;n~d for k current ranges, a switch is made to normal operation.
The incorrect voltage distribution can be measured firstly by measuring the anode voltage Uv~, - ,Uvn through a semiconductor valve 2, which is then compared 3 o with the quotients UBOS/n f rom the total voltage U~os divided by valves 2 and the number n of semiconductors 2.
A second possibility for voltage measurement consists in measuring only the voltage difference ~U1,....,~Un1 between the individual cathode potentials Uvl, . . . ,Uvn and a 35 voltage distribution network connected in parallel (Figure 3). A common feature of these two methods is LITE~ L TR7~7~T~T,~'I'ION
OF PCT l~lPPLICATION 13 2~8555q that the blocking voltage that i9 static and is present af ter shutof f is always recorded, in other words, no expensive measuring recorders need to be used for dynamic processes . In both cases, potential - separated 5 transmission of the measured voltages is required, with a resolution approximately four times higher than in the recording of pure voltage difference being required when the full anode voltage is detected. The potential-separated transmission takes place logically through 10 digiti2ation of the measured signal and occurs basically within the fLd~ rh of the driver feedback messages that are available in any event and can be performed at acceptable expense.
Figure 3 shows the schematic diagram for 15 voltage acquisition using a resistance divider network to measure the incorrect voltage distribution at semiconductor valves 2. It is clear that only an additional feedback RSZ of driver 16 is required, indicating whether ~U=,x has been exceeded or ~U=~x has been 20 undershot. This eliminates A/D conversion and potential separation also becomes very simple.
As a result of this method according to the invention, long- term parameter changes, i . e . those that last for several switching processes, such as a change in 25 temperature for example, are compensated by simple corrective regulation, while the influential parameter that changes rapidly, the shutoff current, acts immediately as a control parameter and hence affects the delay times during the current shutof f process . As a 30 result of this combination of corrective regulation and direct control, a highly advantageous solution can be obtained for the problem recited at the outset.
To clarify the effect of the method according to the invention for making the voltage distribution of 35 series-connected gate-controlled semiconductor valves 2 uniform, Figures 2 and 5 contain time curves for the LITERAL TR~l::T.7~'rION
shutof f of two series - connected semiconductor~ 2 that have different shuto~f times, as a function of time t.
In the graphs, the typical time curves of control signal S, control current IGV11 IGVZ as well as the anode current 5 IAV11 IAV~ and anode voltage UV1, Uvz are shown. The difference in shutoff time ~toff is not equal to zero in the figure, while this difference in ~to~f is ~hown corrected to zero in Figure 5 by means of the method according to the invention. By a corresponding delay in 10 the faster semiconductor valve, the voltage curve on valves 2 is rendered uniform.
Another advantage of the method according to the invention is the ability of the system, without costly calibration, to start automatically and thus to 15 ensure 6afe operation of the rectifier. ~y using the method in the so-called learning phase, the problem of unknown delay times for semiconductor valves 2 at initial startup, after replacement of components, or after a long downtime, is solved LITER~AL ~R~ r,~ION
PROCESS AND DEVICE ~OR E2n~T~T~TNG THE
VOLTAGE DISTRIBUTION TO GATE-COI~rRnT.T.T~n, SERIES--Cl l N~:~ . r:l) SENICO~DUCTORS
The invention relates to a method and a device for rendering uniform the voltage division in series-~ ~lnnf~l-tl~ gate-controlled semiconductors that have shuto_f times of different lengths.
The term ~gate-controlled semiconductors"
refers here to all æemiconductors that can be turned off and on through their control tl~rm;n~1 q (gates) .
Increasing the operating voltage makes an important contribution to increasing the power of re~-t;f;~r~; connecting power semiconductors in series is one way of doing this. In particular, gate-turn-off (GT0) thyristors are Yaluable as semiconductors in this regard since they have the highest blocking voltage resistance of any semiconductor valves that can be shut of f The main problem in a series circuit lies in the non-identical shutoff behavior of the semiconductor valves, so that they are loaded nonuniformly with blocking voltage. The di~ferences in shuto~f behavior, which make themselves noticeable primarily as different shutof f times, is caused both by variations between individual semiconductors and external parameters such as the shutof f current and temperature . If no other measures are taken, this results in an overdimensioning of the semiconductor valves as well as their circuits, 80 that such circuits become uneconomical and limited in the number of series - connected semiconductor valves .
The switching - on process of series - connected semiconductor valves is relatively uncritical i_ the LITERAI, 'I'R~NS::T.~TTON
OF PCT APPLICATION
r 21 85559 rectif ier circuit in which a limitation of the current rise is always provided is specif ied by the blocking voltage resistance of the semiconductor valves at the moment they are turned on, and if there are only minor 5 differences in the switching-on behavior of the power semiconductors. The static blocking voltage load can be controlled by passive means. The switchiny-on behavior and static blockage will therefore not be discussed further here.
A way must therefore be found to produce uniform dynamic voltage loading of the semiconductor valves during the shutof f process . Preset boundary conditions that must be considered include the rectif ier having to be operated immediately at full voltage and a 15 selection of semiconductor valves or other manual measures having to be avoided. It is also important to note that the shutof f behavior of the semiconductor valves, i.e. particularly the differences in shutoff time, are af f ected by the shutof f current and the 20 temperature as well as the differences in the semiconductors. Therefore, the influence of a shutoff current that changes suddenly must be compensated in the same way as the inf luence of the slowly changing temperature. Another requirement for such a method for 25 rendering uniform the voltage distribution in series-connected power semiconductors is the operating safety of the circuit in all (even improper) states.
Various methods are known for cf-nn~- t;ng semiconductor valves that can be switched off in series, 30 thus ensuring safe switching off. The proposed solutions extend from purely pas~ive methods through methods that require a manual application, and even extend to methods that operate on the basis of regulation.
The purely passive methods include measures 35 such as overdimensioning of switching capacity and overdimensioning of the blocking voltages of the LITERAL 'IIR~Nf~T.~'rrON
r. ~ 21 8~559 semiconductor valves, selection of semiconductor valves for the same shutoff, as well as selection of the controls and switches. This i9 accomplished with the goal of obtaining a blocking voltage distribution that is 5 as uniform and dynamic as possible Manual intervention methods for the circuit are known that employ manual adjustment of the shutoff time points to produce delays in the controls or different gate inductances and thus achieve a uniform blocking 10 voltage distribution in the semiconductor valves These proposed solutions are evidently unable to meet the requirements listed above for a method for series connection of semiconductor valves. Primarily, they make series connection of semiconductor valves 15 appear unec~nomical.
From BP 0 288 422 B1, a method is known for rendering voltage distribution uniform when a series circuit of control semiconductors is shut of f, based on regulation of the blocking voltages of the semirnnrll~t tnr 20 valves, with the shutoff points of the individual semiconductor valves being delayed accordingly by the control. In this method, the actual amplitudes of the anode voltages of the series-connected semiconductor valves are measured and compared to the amplitude of the 25 total voltage of the seri~s- connected semiconductor valves in such fashion that a correction value is formed that ~ rm; n~C: the shutoff delays for the individual semiconductor valves As a result, the voltage dif f erences between the semiconductors in the ideal case 30 are compensated to ~ero. The shutoff of the power semiconductors is performed with a current that is low at the beginning but rises to a full operating current at the end, with the difference between the shutoff currents of two successive shutof f processes correcting the 35 established delay times for the individual semiconductor valves. To generate the delay times for the individual .
LITERBL 'I'T~AIU'2T.~ION
r ~ 2 1 85559 semiconductor valves, difference formers are provided In this way, a signal is generated that is proportional to the measured voltage difference between the actual and the ideal voltage distributions, said signal 5 simultaneously constituting the value of the shutoff delay for the respective semiconductor valve. The regulator thus described therefore has a purely proportional behavior. Different shutoff currents between successive swltching processes are ;ntPnlqPfl, 10 through a current difference former, to produce an additional delay in the shutoff signals in order to compensate f or the inf luence of a changing current This regulating system is useful in semiconductor valves with only a sl ight dependence of their shutof f times on the 15 shutoff current, and generally sturdy in nature, such as for example, power transistors and insulated gate bipolar transistors (IGPT) . In such semicrn~ rtr,r valves, however, an even simpler purely adjusting regulation appears to be possible which, when an P~tPrn~l ly set or a 20 f irmly set voltage of the semiconductor valve in r~uestion is exceeded, delays the shutof f .
The invention has as its goal a method and a device for rendering uniform the voltage distribution in series-connected gate-controlled semiconductors, with 25 which, at each shutoff, the correct delay times for the series-connected gate-controlled semiconductor valves are known sufficiently exactly to ensure a safe shutoff.
This goal is achieved according to the invention by the method features a) to g) of Claim 1 and 3 0 the characterizing f eatures of Claim 4 .
The method according to the invention is based on the division of an admissible shutoff current range of the series - connected gate- controlled semiconductors into several areas, with predetermined delay times available 35 for each area for each of the series-conr~ected semiconductor valves. As a result, even during the ON
LITERAL TT~N~T ~rrION
state, delay times are available for a ~ry current 90 that at every shutoff moment, sufficiently accurate delay times are available for the semiconductor valves.
Since the predetermined delay times are also always 5 updated after shutoff, the delay times always adjust from one switching maneuver to the next to the operation of the rectifier device, whose rectifier valves consist of series-connected gate-controlled semicnn~llr~r,rs. In this method, changing influential parameters such as shutoff 10 current and temperature are taken into account as well.
Thus a method is obtained for rendering uniform the voltage distribution of series-connected gate-controlled semiconductors that automatically adjusts to the latest operating state, thus obtaining a method that can learn.
In one advantageous method, the predetermined shutoff delay times are de~f~rmlnr~l automatically by means of a learning phase. The learning phase of the system differs from the method according to Claim 1 in that in this case the shutof f current is set or limited by the 20 regulating system. In the simplest case, the learning phase proceeds in such fashion that the current rectifier initially is shut off several times in the smallest current range, 90 that by adjusting the delay times for the individual valves, the unequal voltage distribution 25 is corrected approximately to zero. If this takes place in the first current range, this delay time is transferred as an initial value in the next current range . Then the same regulating process takes place f or this higher current until the unequal voltage 30 distribution is again compensated. With corrected dimensioning, a regulating process does not last more than two switching processes. This described method is repeated up to the highest current range. The fact that the existing incorrect distribution can always be kept 35 within limits is based on the constant relationship between the shutof f current and the shutof f time in LITERAL 'I'RPlN~T.~'rION
~ 2 ~ 85559 semiconductor valves. The maximum incorrect voltage distribution during the learning phase can be ~ rmi n.o~l by establishing the current ranges.
In an advantageous device for working the 5 method according to the invention, a microprocessor is provided for working the method, to which microprocessor a measured current value, voltage measured values of the recorded blocking voltage distribution, and the switch-on and switch-off signalE~ are supplied from a pulse lO modulator. This sof tware solution is advisable when the pulse modulator is already using a microprocessor. Then it is even more advantageous for the pulse modulator and the device for working the method according to the invention to constitute a module The device for working the method according to the invention can also be built using discrete regulators . In this connection, a discrete I - regulator is provided for each current range and for each series-connected gate-controlled semiconductor This type of 20 regulator proYides both compensation of parameters that change slowly (temperature for example), as well as the ability to note the correct delay times for the individual semiconductor valves. Each time the valves are switched of f, delay times are available at the output 25 of the regulator, said times consisting of a correction of the times from the previous switching process, with the correction value constituting an amount that is proportional to the incorrect voltage distribution that was present the last time the device was shut off The fact that an independent regulator is associated with each current range provides assurance that delay times will be available during each shutof f process that correspond to the respective shutoff current. This concept, which is also implemented in the software solution, permits any relationship, even a nonlinear one, between the delay times and the shutoff LITERAL 'I'R~I`TC~T.~'T'ION
r ~ 2 185559 current. In addition, it ensures that the correct delay times are immediately available upon shutof f .
The shutof f current is optimally detected by measuring the output current of the rectifier, since when 5 the current direction corresponds, it is identical with the valve current. The advantage of this method lies in the fact that the load current is readily accessible by measuring technology or is usually already available as a potential-free measured value.
The incorrect voltage distribution can be measured f irstly by measuring the anode voltage through a semiconductor valve and then comparing it with a quotient of the total voltage divided by the valves and the number of semiconductors. A second way to measure voltage is to measure only the voltage difference between the individual cathode potentials and a voltage distributor network connected in parallel. These small voltage differences are linked with one another and compensated to zero by the device. A common feature of the methods is that the static blocking voltages are always recorded, in other words no expensive measured-value recorders for dynamic processes must be used.
For further explanation of the invention, reference is now made to the drawing in which a device according to the invention f or working the method is shown schematically, as used for comparison of the voltage distribution of series - connected gate- controlled semiconductor valves.
Figure 1 shows a schematic diagram of an advantageous embodiment of a device according to the invention for the control times of series-connected gate-controlled semiconductors Figure 2 shows a flowchart for learning-capable regulation of the shutoff delay times for series-connected gate- controlled semiconduc'cors in which LITERAL 'I'R~TqT.~'l'ION
OF PCT APPLICA~ION 7 Figure 3 is a schematic diagram of a simple voltage detection device in which Figure 4 shows typical time curves of control signals and control current as well as anode current and anode voltage, plotted against time for two series-connected gate- controlled semiconductors with a shutof f time difference and without compensation, while in Figure 5 the signal graphs are shown, with compensation of the controlled shutoff times plotted as a function of time t.
Figure 1 shows a schematic diagram of a learning-capable regulating system for rendering uniform the voltage division in a series-connected gate-controlled semiconductor 2 with shutof f times of different lengths. Thyristors that can be shut off (GTO-thyristors) are used as gate-controlled semiconductors 2.
These GTO thyristors 2 form one half of a bridge branch of a rectifier circuit, not shown in greater detail.
This rectifier circuit, for example, a 6-pulse inverter, is fed by a DC source of which only one positive intermediate circuit bus is shown. The part of ~he bridge branch that is shown, in addition to the n GTO
thyristors 2, also has a choke 6 for current limitation.
~oad tPrm; n;~l 8 is connected to the midpoint of the bridge branch, said tPrm;n~l having a current converter 10 to detect load current iL. Each semiconductor valve 2 is provided with a device 12 connected electrically in parallel with the valve.
This device 12 ct~nt;linq a known unloading network, for example an RCD circuit, also generally called a~snubber circuit, a resistance of a voltage divider network, and a measured voltage device with which a value of an improper voltage distribution, can be measured. The known RCD clrcuit consists of a series circuit composed of a switching capacitor and a switching LITE-RAL 'I'RbN.qT.~TION
OF PCT ~PPLICATION 8 ~ 2 1 85559 diode connected electrically and in parallel with an ohmic resistance. Voltage distribution in the series circuit of n semiconductor valves 2 is ensured in the steady state by the resistances that are connected in parallel with each semiconductor 2. This steady state, whose voltage distribution is set only slowly by relatively high resistances connected in parallel, is only of real signlf icance when valves 2 are in a prolonged OFF state. On the other hand, the improper voltage dlstribution that occurs immediately after the shutof f process remains almost unchanged during a normal pulse duration, so that this improper distribution is available on a quasi-steady-state basis during the OFF
phase. In addition, each device 12 also has a free-running diode f or the corresponding semiconductor valve ~
2. The output signal, namely the value ~Ul, ~U2,.~ Un 2~ ~U.-l of the improper voltage distribution, is conducted, potential-separated, through one of the n-1 leads to device 14.
The control of the n semiconductor valves 2 ~or turning on and off is accomplished in each case by means of a known driver circuit 16, connected to a control terminal G and a cathode ~ of the gate- controlled semiconductor 2 in question. On the input side, driver circuits 16 are each cr,nnc~rtP~l, potential-separated, with the outputs of device 14.
For potential separation, it i8 r~rt~mmonrll~rl to use voltage-frequency conversion with optocouplers and light pipes or digitization of the measured value to measured potential, with optical transmission of the digital signal . For simpli~ied signal tr;:lncm~ ~sion, it also appears possible to provide only a very coarse measurement of the improper voltage distribution.
Device 14 for rendering the voltage distribution o~ series-rnnnPrt~-l gate-controlled semiconductors 2 uniform is linked on the input side with hITERAL 'T'R~N~T.7~TION
8~
a pulse modulator 18 of the re2c~ifier, 9from which it obtains a control signal E/A (on and off signal) and a start signal StA. From device 14, this modulator 18 obtains a feedback signal RS or R~ regarding the 5 switching state of semiconductor valves 2 and/or the learning phase. Device 14 consists of an asymmetry monitor 20, a control device 22, a computing device 24, an intermediate storage device 26, and an output device 28. Control device 22 is located on the input side in 10 device 14 and receives start signal ST or control signal B/A from pulse modulator 18. In addition, this control device 22 also receives an OFF signal SG and a current measurement signal for the load current iL. The feedback signals RS and R~ for modulator 18 as well as the status 15 signals SI- and SEA for calculating device 24 and a start signal St for output device 28 are generated by control device 22. Calculating device 24 also receives values ~Ul, ....,~Un 1 of the improper voltage distribution and a current measurement signal f or load current iL -The method according to the invention will be described in greater detail with reference to this schematic diagram and the flowchart in Figure 2, and the method according to Claim 1 and then the learning program will be discussed in greater detail.
In calculating device 24, a table with delay times for k current ranges and n semiconductor valves 2 is provided, with these delay times being generated for example by the learning program, which is a 8ub,uLu~Ldll~ of the method according to the invention. During normal operation, control device 22 of device 14 receives a control signal E or A from pulse modulator 18. Then control device 22 activates status signal SEA, resulting in calculating device 24 being placed in the switching mode. Depending on a clock signal, not shown in greater detail, measured values for load current iL are read continuously into calculating device 24, with LITER~L ~R~N~::T~ ION
corresponding delay times being read out for this current measurement range during the next cycle from table n, said times being stored during the next cycle in intermediate storage device 26. '~'hen the control signal 5 of modulator 18 changes from E to A (OFF state), control device 22 generates start signal St, whereupon the n delay times stored in ;nt~ te storage device 26 are taken over into output device 28, so that the n semiconductor valves 2 are each switched of f with their 10 individual delay times. In addition, the level of status signal SEA changes so that the last delay times to be called up are noted.
After the n series-connected gate-controlled semiconductors 2 are shut of f, the delay times noted f or 15 the shutof f current range are updated. This is accomplished as follows: following a period of time to be specified as a function of voltage values for each valve 2, a value ~UI, .... ,~Un l of the improper voltage distribution is formed and fed to asyiTImetry monitor 22 20 and computing device 24. From these values ~U1, ....,i~Un l of the improper voltage distributions, calculating device 24 computes new delay times for this shutoff current range, with an amount being added for the noted delay times that is proportional to a linking of the values 25 ~UI, .... ,~Un l of the improper voltage distribution.
The values ~UI, ...., ~Un 1 of the improper voltage distribution can be linked with one another for example by the f ollowing equation:
UUnsy=.Vi l!'Un l + ~Ui ~ I~Ui l 3 o where n is the nu~nber of valves 2 connected in series and i is the first, second,..., i-th valve 2.
These updated delay times are stored in the table for this shutoff current range, in other words the new delay times overwrite the corresponding stored delay 35 times for this current range. As a result, device 14 continuously adjusts to variable parameters. If a value ~ITERA~ 'I'R~7.`7qT,~TION
OF PCT APP~ICATION 11 f or the improper voltage distribution exceeds a prede~PrminP~ limit, device 14 is shut o~ and notification is provided by an optical signal. Shutoff prevents exce~sive improper voltage distribution during the next switching process from damaging or destroying series - connected gate- controlled valves 2 .
This is the regulating process of device 14 in normal operation, and makes it clear that device 14 has an integrating behavior, as a result of which the control errors, i.e. the unequal voltage distribution, can be compensated to zero . The clock f re~auency or scanning time of device 14 corresponds to the switching time of valves 2.
Instead oi~ the table in calculating device 24, a discrete I-regulator can be used for each table value, since this type of regulator ensures compensation of parameters that change slowly (temperature, for example) as well as the ability to '~note~ the correct delay times for the individual semiconductor valves 2.
Since no delay times are known for semiconductor valves 2 when the rectifier is first switched on, so that a voltage overload can lead to destruction of semiconductor 2 even when it is first switched on, in the method according to the invention the delay times are determined in a so- called learning phase .
The method in the learning phase differs from the method already described in that in the learning phase the cutoff current is specified or limited by a regulating system .
According to the flowchart in ~igure 2, the voltage is equal to the rated voltage, the current value is approximately zero, and the GTO parameters are unknown. Since the parameters of GT0 valves 2 are not known, no shutoff delay times can be stored in device 14.
In the smallest current range k=1, the gate-controlled semiconductors 2 that are connected in series are shut LITERAL TRI~N~T.~TION
2 1 8555q off. The values ~U1, ....,~Un 1 determined for the incorrect voltage distribution are converted by calculating device 24 into delay times. This process can be repeated several times for the lowest current range 5 k=1 80 that the unequal voltage distribution is corrected approximately to zero. This regulating process preferably does not last more than two switching processes. These n delay times flf~ rm;n~l for the first current range are stored in the table of Qlculating lO device 24 and noted as selected delay times for current range k=2. After shutoff has been performed, these noted delay times of current range k=2 are updated by the values ~Ul, .... ,~Un l ~t~rm;n~ for incorrect voltage distribution and stored in the table for the second 15 current range. At the same time, these delay times again constitute the delay times for the next current range k=3. These processes are repeated until the maximum current range k=k is reached.
In each current range k, the shutoffs can be 20 repeated several times so that a very high accuracy is attained in determining the shutof f delay times . During this learning phase of device 14, the current is increased f rom zero to the maximum shutof f current by a regulating device, not shown in greater detail. When n 25 shutoff delay times have been de~ T;n~d for k current ranges, a switch is made to normal operation.
The incorrect voltage distribution can be measured firstly by measuring the anode voltage Uv~, - ,Uvn through a semiconductor valve 2, which is then compared 3 o with the quotients UBOS/n f rom the total voltage U~os divided by valves 2 and the number n of semiconductors 2.
A second possibility for voltage measurement consists in measuring only the voltage difference ~U1,....,~Un1 between the individual cathode potentials Uvl, . . . ,Uvn and a 35 voltage distribution network connected in parallel (Figure 3). A common feature of these two methods is LITE~ L TR7~7~T~T,~'I'ION
OF PCT l~lPPLICATION 13 2~8555q that the blocking voltage that i9 static and is present af ter shutof f is always recorded, in other words, no expensive measuring recorders need to be used for dynamic processes . In both cases, potential - separated 5 transmission of the measured voltages is required, with a resolution approximately four times higher than in the recording of pure voltage difference being required when the full anode voltage is detected. The potential-separated transmission takes place logically through 10 digiti2ation of the measured signal and occurs basically within the fLd~ rh of the driver feedback messages that are available in any event and can be performed at acceptable expense.
Figure 3 shows the schematic diagram for 15 voltage acquisition using a resistance divider network to measure the incorrect voltage distribution at semiconductor valves 2. It is clear that only an additional feedback RSZ of driver 16 is required, indicating whether ~U=,x has been exceeded or ~U=~x has been 20 undershot. This eliminates A/D conversion and potential separation also becomes very simple.
As a result of this method according to the invention, long- term parameter changes, i . e . those that last for several switching processes, such as a change in 25 temperature for example, are compensated by simple corrective regulation, while the influential parameter that changes rapidly, the shutoff current, acts immediately as a control parameter and hence affects the delay times during the current shutof f process . As a 30 result of this combination of corrective regulation and direct control, a highly advantageous solution can be obtained for the problem recited at the outset.
To clarify the effect of the method according to the invention for making the voltage distribution of 35 series-connected gate-controlled semiconductor valves 2 uniform, Figures 2 and 5 contain time curves for the LITERAL TR~l::T.7~'rION
shutof f of two series - connected semiconductor~ 2 that have different shuto~f times, as a function of time t.
In the graphs, the typical time curves of control signal S, control current IGV11 IGVZ as well as the anode current 5 IAV11 IAV~ and anode voltage UV1, Uvz are shown. The difference in shutoff time ~toff is not equal to zero in the figure, while this difference in ~to~f is ~hown corrected to zero in Figure 5 by means of the method according to the invention. By a corresponding delay in 10 the faster semiconductor valve, the voltage curve on valves 2 is rendered uniform.
Another advantage of the method according to the invention is the ability of the system, without costly calibration, to start automatically and thus to 15 ensure 6afe operation of the rectifier. ~y using the method in the so-called learning phase, the problem of unknown delay times for semiconductor valves 2 at initial startup, after replacement of components, or after a long downtime, is solved LITER~AL ~R~ r,~ION
Claims (7)
1. Method for rendering uniform the voltage distribution in a series circuit composed of gate-controlled semiconductors (2) that have shutoff times of different lengths, characterized by the following method steps:
a) During an ON state of series-connected, gate-controlled semiconductors (2), a current (iL) flowing through these semiconductors (2) is measured;
b) depending on this measured current value, a predetermined shutoff delay time is called up for series-connected, gate-controlled semiconductors (2);
c) when a shutoff signal (A) arrives, series-connected, gate-controlled semiconductors (2) are shut off with the shutoff delay times determined;
d) following shutoff of these semiconductors (2), after a period of time to be specified, the blocking voltage distribution over these semiconductors (2) is determined;
e) Depending on this recorded blocking voltage distribution, values are determined for an improper distribution of voltage;
f) the shutoff delay times that have been called up are updated, with an amount being added that is proportional to a linking of the determined values (.DELTA.U1,..., .DELTA.Un-1) of the improper voltage distribution; and g) these updated shutoff delay times are stored.
a) During an ON state of series-connected, gate-controlled semiconductors (2), a current (iL) flowing through these semiconductors (2) is measured;
b) depending on this measured current value, a predetermined shutoff delay time is called up for series-connected, gate-controlled semiconductors (2);
c) when a shutoff signal (A) arrives, series-connected, gate-controlled semiconductors (2) are shut off with the shutoff delay times determined;
d) following shutoff of these semiconductors (2), after a period of time to be specified, the blocking voltage distribution over these semiconductors (2) is determined;
e) Depending on this recorded blocking voltage distribution, values are determined for an improper distribution of voltage;
f) the shutoff delay times that have been called up are updated, with an amount being added that is proportional to a linking of the determined values (.DELTA.U1,..., .DELTA.Un-1) of the improper voltage distribution; and g) these updated shutoff delay times are stored.
2. Method according to Claim 1, with the predetermined shutoff delay times being determined and stored automatically during startup by means of a learning phase.
3. Method according to Claim 2, with the learning phase being characterized by the following method steps:
a) the measurement range of the current (iL) flowing though series-connected, gate-controlled semiconductors (2) is subdivided into k current measuring ranges;
b) for each current range, method steps (a to g) are performed according to Claim 1, with the updated shutoff delay times to be stored serving simultaneously as predetermined shutoff delay items for the next current measurement range; and c) after the updated shutoff delay times have been determined for all k current measurement ranges, a switch is made to normal operation.
a) the measurement range of the current (iL) flowing though series-connected, gate-controlled semiconductors (2) is subdivided into k current measuring ranges;
b) for each current range, method steps (a to g) are performed according to Claim 1, with the updated shutoff delay times to be stored serving simultaneously as predetermined shutoff delay items for the next current measurement range; and c) after the updated shutoff delay times have been determined for all k current measurement ranges, a switch is made to normal operation.
4. Device (14) for working the method according to Claim 1 for a series circuit composed of gate-controlled semiconductors (2) that have shutoff times of various lengths, with a driver circuit (16) being connected to control terminals (G, K) of said semiconductors, said circuit being connected in an electrically conducting fashion with a pulse modulator (18) by a potential-separating device, characterized in that this device (14) comprises a control device (22), a calculating device (24), an intermediate storage device (26), and an output device (28), and is connected between pulse modulator (18) and the potential-separating device, with control device (22) controlling calculating device (24) and output device (28) as a function of signals (StA, E/A) from pulse modulator (18), with a measured value for the load (iL) of control device (22) and calculating device (24) being supplied and with calculating device (24) continuing to receive measured voltage values (UV1,..., Uvn; .DELTA.U1,..., .DELTA.Un-1).
5. Device (14) according to Claim 4, characterized in that device (14) contains an asymmetry monitor (20) which receives measured voltage values (.DELTA.U1,..., .DELTA.Un-1) at its input and is connected on the output side firstly with control device (22) and secondly with intermediate storage device (26).
6. Device (14) according to Claim 4, characterized in that a microprocessor is provided as device (14).
7. Device (14) according to Claim 4, characterized in that device (14) is part of pulse modulator (18).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP94104203 | 1994-03-15 | ||
| EP94104203.8 | 1994-03-15 | ||
| PCT/EP1995/000789 WO1995025383A1 (en) | 1994-03-15 | 1995-03-03 | Process and device for equalising the voltage distribution to gate-controlled, series-connected semiconductors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2185559A1 true CA2185559A1 (en) | 1995-09-21 |
Family
ID=8215782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002185559A Abandoned CA2185559A1 (en) | 1994-03-15 | 1995-03-03 | Process and device for equalising the voltage distribution to gate-controlled, series-connected semiconductors |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP0750808B1 (en) |
| JP (1) | JPH09510334A (en) |
| CN (1) | CN1144024A (en) |
| AT (1) | ATE162347T1 (en) |
| CA (1) | CA2185559A1 (en) |
| DE (1) | DE59501290D1 (en) |
| WO (1) | WO1995025383A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017203039A1 (en) * | 2016-05-27 | 2017-11-30 | General Electric Technology Gmbh | Method of controlling a switching valve |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19755984C2 (en) * | 1997-12-17 | 2002-12-12 | Alcatel Sa | Method and circuit arrangement for reverse voltage compensation regulation in a series connection of gate-controlled semiconductors |
| JPH11235015A (en) * | 1998-02-13 | 1999-08-27 | Toshiba Corp | Voltage-driven power semiconductor device and method of controlling the gate of the same |
| CN101354427B (en) * | 2007-07-24 | 2010-12-15 | 通嘉科技股份有限公司 | Method for testing leading edge shield parameter of power supply management chip |
| CN102880443B (en) * | 2012-08-31 | 2014-11-05 | 深圳市英威腾电气股份有限公司 | Data processing method and related devices for data processing method |
| FR3013467A1 (en) * | 2013-11-21 | 2015-05-22 | St Microelectronics Tours Sas | VOLTAGE BALANCING SYSTEM OF SEMICONDUCTOR ELEMENTS IN SERIES |
| JP6346571B2 (en) * | 2015-01-08 | 2018-06-20 | 株式会社豊田中央研究所 | Power system |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62154815A (en) * | 1985-12-27 | 1987-07-09 | Toshiba Corp | Gate circuit for gate turn off thyristor |
| DE3714173A1 (en) * | 1987-04-24 | 1988-11-10 | Licentia Gmbh | COMPARISON OF THE VOLTAGE DISTRIBUTION WHEN DISCONNECTING A SERIAL CONNECTION OF GATE CONTROLLED SEMICONDUCTORS |
| JPH0470209A (en) * | 1990-07-11 | 1992-03-05 | Hitachi Ltd | Method and device for driving switching element |
| JPH04295269A (en) * | 1991-03-20 | 1992-10-20 | Toshiba Corp | Method of adjusting shared voltage of gtos connected in series |
-
1995
- 1995-03-03 DE DE59501290T patent/DE59501290D1/en not_active Expired - Fee Related
- 1995-03-03 EP EP95911288A patent/EP0750808B1/en not_active Expired - Lifetime
- 1995-03-03 JP JP7523801A patent/JPH09510334A/en active Pending
- 1995-03-03 CN CN95192109.6A patent/CN1144024A/en active Pending
- 1995-03-03 AT AT95911288T patent/ATE162347T1/en not_active IP Right Cessation
- 1995-03-03 CA CA002185559A patent/CA2185559A1/en not_active Abandoned
- 1995-03-03 WO PCT/EP1995/000789 patent/WO1995025383A1/en active IP Right Grant
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017203039A1 (en) * | 2016-05-27 | 2017-11-30 | General Electric Technology Gmbh | Method of controlling a switching valve |
| GB2550892B (en) * | 2016-05-27 | 2019-02-27 | General Electric Technology Gmbh | Method of controlling a switching valve |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1995025383A1 (en) | 1995-09-21 |
| JPH09510334A (en) | 1997-10-14 |
| CN1144024A (en) | 1997-02-26 |
| EP0750808A1 (en) | 1997-01-02 |
| DE59501290D1 (en) | 1998-02-19 |
| ATE162347T1 (en) | 1998-01-15 |
| EP0750808B1 (en) | 1998-01-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |