SU1700541A1 - Reference voltage source - Google Patents

Abstract

The invention relates to electrical engineering and can be used as a source of reference voltage, for example, in analog-digital converters. The aim of the invention is to improve the quality of the output voltage. The purpose is justified by the fact that keys 5–7, capacitors 10 and 11, resistor 9 and diode 8, sec, are inserted into a known source containing a divider 1 of the output voltage t, a reference Zener diode 2, a limiting resistor 3 and a differential DC amplifier DC. relevant links. To eliminate the mixing voltage zero of amplifier A, the signal at the control input of the key management unit 12 switches the amplifier for some time to a mode in which the bias voltage of the amplifier is extracted and stored on the capacitor 10. After this, normal operation is restored. The voltage across the capacitor 10 compensates for the bias zero voltage of the amplifier. Periodic alternation of modes allows eliminating the effect of the bias zero voltage of the amplifier C on the output voltage. The resulting impulse mode of the stabilizer is eliminated by the diode 8 and the capacitor 90 which provide the output voltage at a predetermined level during the correction mode. 2 Il. "Tf C

Description

3

The invention relates to electrical engineering and can be used as a source of reference voltage, for example, as analog-digital converters.

The purpose of the invention is to improve the quality of the output voltage.

FIG. 1 shows a functional diagram of the source of the reference to {y; in fig. 2 shows an embodiment of a key management unit.

The source contains between the output output for connecting the load and the common bus divider 1 of the output voltage and a serial chain of the reference Zener diode 2 and the limiting resistor 3, a differential DC amplifier, three keys in series of a diode 8 and a resistor 9 connected between the output the output for connecting the heating and the output of the amplifier 4, two capacitors (capacitors 10 and 11, and a key control unit 12 with a control output 13, and the input of the first key 5 is connected to the Zener diode junction point and 2 with a resistor 3, the output through the first capacitor 10 to inverting

A control amplifier input 5 is connected to an inverse output of a key management unit 12, the direct output of which is connected to the control inputs of the second 6 and third 7 keys, the second key is connected between the outputs of the first key 5 and divider 1, and the third key is between an inverting input and output of amplifier 4, and a second capacitor is connected between the output terminal for connecting the load and the common bus about

The source works as follows

In the initial state, when there is no signal at input 13 of control, key 5 is closed, keys 6 and 7 are open and the device operates in the voltage stabilizer mode. At the initial time, the capacitor 10 is discharged and the output voltage of the source is determined by the formula

eyk

 (U

from

with.

+ V. 11-

U

6S

st

- the output voltage of the stabilizer;

- voltage stabilization of Zener diode 2;

U w o is the bias voltage of zero amplifier 4; Ko, is the ratio of the shoulders of the voltage divider 1.

To eliminate the bias voltage zero of the amplifier 4, it is necessary to input a correction enable signal at control input 13 (any digital signal can be used as logic levels as a correction enable signal, and a variant of the key management unit is shown in FIG. 2) which block 12 oblacheni keys forms the outputs of the outputs, opening the key 5 and the locking keys 6 and 7.

As a result, the amplifier 4 is disconnected from the Zener diode 2, and the diode 8 at the same time disconnects the output of the amplifier 4 from the output of the device. Key 7 connects the inverting input and output of amplifier 4, and key b connects the capacitor 10 to the non-inverting input of amplifier k. With this switch on, the following voltages are present at the inputs of amplifier 4

in | Ine and Ivk Uvt & (Ueic

+ Ucfo (2) + UCM.O) CK;

where in / I1 in is the voltage at the non-inverting input;

 and the voltage at the inverting input;

cio is the voltage across capacitor 10;

K (j is the gain of the amplifier 4.

From (2) find the voltage on the capacitor 10

 TSnUinv 1 + K ,,

- and,

Ki

CM.S

1 + Ki

If we consider that K0 1, then 1) C (0 - ISA /), c, i. for large values of K c amplifier k on the capacitor 10, the voltage is picked up and stored.

offset zero amplifier.

Upon completion of the correction signal at the control input 13, the key management unit 12 converts the stabilizer to the initial state, and the voltage across the capacitor 10 applied to the input of the silytel k of the projectile-phase bias voltage zero compensates for the latter. Formula (1) in this case takes the form

and.

set (1 + k).

 e, ank

Periodic repetition of the bias zero voltage compensation cycles eliminates its destabilizing effect on the output voltage of the stabilizer and thereby reduces the output voltage drift, while the duration of the correction cycle is determined by the duration of transient processes. 30 ms

To eliminate the pulse mode of the device, which is undesirable from the point of view of the stationary thermal regime of Zener diode 2, which determines the minimum voltage drift of the stabilization voltage, a capacitor 11 is inserted that maintains the voltage at the output terminal at the nominal level during the offset zero correction of the amplifier 4. protects amplifier k from overload during the charging of capacitor 11 after turning on the power of the device.

Since this reference voltage source has maximum output voltage stability in the intervals between amplifier bias voltage correction cycles, it can be proposed, for example, as a reference voltage source in analog-to-digital push-pull converters. In this case, the offset offset zero cycles of the amplifier combine in time with the zero cycles of the amplifier itself.

Thus, the present invention allows to reduce the source voltage output drift by about 10 times.

It should be noted that the maximum positive effect is achieved when the voltage variation on the capacitor 11 due to a discharge in the correction cycle is less than the output voltage drift under the influence of the bias zero of the amplifier, which is ensured by the choice of elements and operating modes of the device.

 five

ten

20

25

Invention The source of the reference voltage, containing an output voltage divider, a series of reference zener diodes and a limiting resistor, connected in parallel to the input pins of the output voltage divider, and a differential DC amplifier, the non-inverting input of which is connected to the output of the output voltage divider, input the terminals of which are connected between the output terminal jc for connecting the load and the common bus, characterized in that, in order to improve the quality of the output on three keys, a capacitor ditch, a key control unit, and a series of diode and resistor connected between the output terminal for connecting the load and the output of the differential DC amplifier, the first key input connected to the junction of the reference Zener diode with the limiting a resistor, and the output through the first capacitor to the inverting input of the differential DC amplifier and to the input of the second switch, the output of which is connected to the output of the differential amplifier DC, the third switch is connected between the outputs of the first switch and the output voltage divider, the control input of the first switch is connected to the inverse, and the control inputs of the second and third switches with the direct outputs of the switch control block, the second capacitor is connected between the terminals for connecting the load and a common bus, and the duration of the pulses generated by the key management unit is determined from the calculation of transients when storing the zero offset voltage of the differential DC amplifier and the magnitude of the permissible error due to the second discharge. the pulse frequency is calculated from the calculation of the value of the permissible error due to the discharge of the second capacitor.

thirty

35

40

45

50

. Element M

&

Key management scheme

FIG. 2

Claims (1)

claims A voltage reference source comprising an output voltage divider, a series circuit of a reference zener diode and a limiting resistor connected in parallel with the input terminals of the output voltage divider, and a differential DC amplifier, the non-inverting input of which is connected to the output of the output voltage divider, the input terminals of which are connected between the output output for connection of the load and common bus, characterized in that, in order to improve the quality of the output voltage In this case, three keys, two capacitors, a key management unit up2θ and a serial chain of a diode and a resistor connected between the output terminal for connecting the load and the output of the differential amplifier of direct current 25 are introduced into it, and the input of the first key is connected to the junction point of the reference zener diode with limiting resistor, and the output through the first capacitor to the inverting input 30 of the differential DC amplifier and to the input of the second key, the bias voltage of the amplifier, it can be proposed, for example, as a reference voltage source in analog-to-digital converters of push-pull integration. In this case, the amplifier’s zero offset correction cycles are combined in time with the amplifier’s zero correction cycles. Thus, the present invention allows to reduce the drift of the output voltage of the source by about 10 times. It should be noted that the maximum positive effect is achieved when the voltage change across the capacitor 11 due to the discharge in the correction cycle is less than the output voltage drift under the influence of the zero bias of the amplifier, which is ensured by the choice of elements and operating modes of the device. the output of which is connected to the output of the differential DC amplifier, the third key is connected between the outputs of the first key and the output voltage divider, the control input of the first key is connected to | inverse, and the control inputs of the second and third keys with direct outputs of the key control unit, the second capacitor is connected between the output; for connecting the load and the common bus, the duration of the pulses generated by the key control unit is determined from the calculation of transients when storing the zero bias voltage of the differential DC amplifier and the value of the permissible error due to discharge. sator, and the pulse repetition rate - based on the calculation of the allowable error due to the discharge of the second capacitor. The element is NOT ” Key management scheme FIG. 2