CA2178456A1 - Systeme multiprocesseur insensible aux defaillances - Google Patents

Systeme multiprocesseur insensible aux defaillances

Info

Publication number
CA2178456A1
CA2178456A1 CA 2178456 CA2178456A CA2178456A1 CA 2178456 A1 CA2178456 A1 CA 2178456A1 CA 2178456 CA2178456 CA 2178456 CA 2178456 A CA2178456 A CA 2178456A CA 2178456 A1 CA2178456 A1 CA 2178456A1
Authority
CA
Canada
Prior art keywords
data
memory
packet
cpu
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2178456
Other languages
English (en)
Inventor
Robert W. Horst
William Edward Baker
William Patterson Bunton
Gary F. Campbell
Richard W. Cutts, Jr.
Daniel L. Fowler
David J. Garcia
Paul N. Hintikka
Geoffrey I. Iswandhi
David Paul Sonnier
William Joel Watson
Frank A. Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/482,618 external-priority patent/US5964835A/en
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of CA2178456A1 publication Critical patent/CA2178456A1/fr
Abandoned legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Storage Device Security (AREA)
CA 2178456 1995-06-07 1996-06-06 Systeme multiprocesseur insensible aux defaillances Abandoned CA2178456A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/482,618 US5964835A (en) 1992-12-17 1995-06-07 Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
US08/482,618 1995-06-07

Publications (1)

Publication Number Publication Date
CA2178456A1 true CA2178456A1 (fr) 1996-12-08

Family

ID=23916759

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2178456 Abandoned CA2178456A1 (fr) 1995-06-07 1996-06-06 Systeme multiprocesseur insensible aux defaillances

Country Status (2)

Country Link
JP (1) JPH09244960A (fr)
CA (1) CA2178456A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103077152B (zh) * 2012-12-25 2015-09-30 北京四方继保自动化股份有限公司 一种用于智能变电站终端设备芯片间的通信加速方法

Also Published As

Publication number Publication date
JPH09244960A (ja) 1997-09-19

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Legal Events

Date Code Title Description
FZDE Dead