CA2178408A1 - Methode et appareil de transmission d'interruption dans un systeme de traitement - Google Patents

Methode et appareil de transmission d'interruption dans un systeme de traitement

Info

Publication number
CA2178408A1
CA2178408A1 CA 2178408 CA2178408A CA2178408A1 CA 2178408 A1 CA2178408 A1 CA 2178408A1 CA 2178408 CA2178408 CA 2178408 CA 2178408 A CA2178408 A CA 2178408A CA 2178408 A1 CA2178408 A1 CA 2178408A1
Authority
CA
Canada
Prior art keywords
packet
data
memory
cpu
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA 2178408
Other languages
English (en)
Inventor
Geoffrey I. Iswandhi
William Edward Baker
William Patterson Bunton
John Deane Coddington
Daniel L. Fowler
David J. Garcia
Paul N. Hintikka
Susan Stone Meredith
Stephen H. Miller
David Paul Sonnier
William Joel Watson
Frank A. Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tandem Computers Inc
Original Assignee
Tandem Computers Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/481,749 external-priority patent/US5675807A/en
Application filed by Tandem Computers Inc filed Critical Tandem Computers Inc
Publication of CA2178408A1 publication Critical patent/CA2178408A1/fr
Abandoned legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
CA 2178408 1995-06-07 1996-06-06 Methode et appareil de transmission d'interruption dans un systeme de traitement Abandoned CA2178408A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/481,749 US5675807A (en) 1992-12-17 1995-06-07 Interrupt message delivery identified by storage location of received interrupt data
US08/481,749 1995-06-07

Publications (1)

Publication Number Publication Date
CA2178408A1 true CA2178408A1 (fr) 1996-12-08

Family

ID=23913236

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2178408 Abandoned CA2178408A1 (fr) 1995-06-07 1996-06-06 Methode et appareil de transmission d'interruption dans un systeme de traitement

Country Status (2)

Country Link
JP (1) JPH09244906A (fr)
CA (1) CA2178408A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110184687A1 (en) * 2010-01-25 2011-07-28 Advantest Corporation Test apparatus and test method

Also Published As

Publication number Publication date
JPH09244906A (ja) 1997-09-19

Similar Documents

Publication Publication Date Title
EP0747833B1 (fr) Système multiprocesseur à tolérance de panne
US6157967A (en) Method of data communication flow control in a data processing system using busy/ready commands
US6151689A (en) Detecting and isolating errors occurring in data communication in a multiple processor system
US5751932A (en) Fail-fast, fail-functional, fault-tolerant multiprocessor system
US5964835A (en) Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source
US5675807A (en) Interrupt message delivery identified by storage location of received interrupt data
US5867501A (en) Encoding for communicating data and commands
CA2190209A1 (fr) Transferts de donnees en masse
EP0747817B1 (fr) Méthode et dispositif de contrôle du flux de données dans un système à multiprocesseur à tolérance de fautes
CA2178440A1 (fr) Systeme multiprocesseur insensible aux defaillances
CA2178408A1 (fr) Methode et appareil de transmission d'interruption dans un systeme de traitement
CA2178455A1 (fr) Systeme multiprocesseur insensible aux defaillances
CA2178456A1 (fr) Systeme multiprocesseur insensible aux defaillances

Legal Events

Date Code Title Description
FZDE Dead