CA2167742C - Modulator-demodulator device capable of detecting an unsynchronized frame state - Google Patents

Abstract

A modulator-demodulator device capable of detecting a frame unsynchronized state of a receiver device connected to a network through which the data to be transmitted are maximum likelihood coded and phase modulated, and the coded and modulated data are transmitted; the receiver device comprises: demodulator means for demodulating the phase modulated data;
compensating means for compensating for signal deterioration in rotation of the demodulated base band signal; proximate signal point deciding means for deciding one signal point in the proximity of the compensated signal from a plurality of received ideal signal points with respect to the compensated signal delivered from the compensating means; maximum likelihood signal point deciding means for decoding the maximum likelihood coded data, deciding the maximum likelihood coded data by using the compensating signal delivered from the compensating means, and outputting the result of the decision; means for comparing the compensated signal and the one signal point delivered by the proximate signal point deciding means and deriving a first error;
means for comparing the compensated signal and the maximum likelihood signal point delivered by the maximum likelihood signal point deciding means and deriving a second error; and means for deriving the difference the first error and the second error. The unsynchronized frame state is detected based on the derived difference.

Description

DESCRIPTION
Modulator-Demodulator Device Capable of Detecting an Unsynchronized Frame State [Technical Field]
This application is a division of co-pending Canadian Application Serial No. 2,034,007 filed June 13, 1990.
The present invention relates to a modulator-demodulator (modem) device for a phase modem system, a quadrature amplitude modem system, and the like. The present invention relates particularly to a device capable of detecting an unsynchronized frame state in synchronization transmission in a modem device.
The device according to the present invention is used, for example, for a modem in terminal devices for data communication.
[Prior Arts}
In a synchronization type data transmission system adopting a phase modem system, a quadrature amplitude modem system, and the like, frame synchronization between the transmitter side and the receiver side is established by introducing a frame synchronization signal in a training signal for the automatic pulling-in of the automatic equalizer of the receiver side prior to the transmission of the data, and during the data transmission, the operation is carried out with synchronized frame phase which is established during the receiving of the training signal. If the frame phase deviates due to a variation in the characteristics of the data transmitting network, and an unsynchronized frame state occurs, normal data transmission is prevented, however, this unsynchronized frame state can be detected only by an abnormal condition of received data. Thus, it would be desirable if a system in which the frame synchronization is detected quickly and reliably could be realized.
In general, for a transmission device which uses an analog line having a transmission rate of 2400 bps to 19200 bps, data transmission speed is normally set to an integer number times 2400 bps. Thus, in a transmission device in which the modulation speed as an interval for synchronizing data and for transmitting a~nd receiving synchronized data is different from 2400 bps, and the bit number of the transmission which is able to be at one time is an integer, it is necessary to carry out transmission processing in a frame synchronized condition between a transmitter and receiver by using frame phase information in order to coincide with the transmission speed of an integer multiple of the standard 2400 bps.
In a prior art system, the frame phase synchronization between a transmitter side and a receiver side is established by introducing a frame synchronization signal in a training signal prior to data transmission in order to make the frame phase of the receiver side coincide with the frame phase of the transmitter side, and during the data transmission, the operation is carried out with synchronized frame phase when the training signal is received.
For example, if one frame is assumed to be constituted by 8 modulations, a modulation synchronization signal is derived by demodulating each instance of modulation, frame phase information is generated by counting the number of these demodulated synchronization signals, and the timing of clearing a counter is preliminarily determined by the frame phase synchronization signal when the training signal is received, and frame phase synchronization between the transmitter side and the receiver side can be established even if the frame synchronization signal is not received during the data transmission.
However, in such a prior art frame synchronization system, if part of the modulation signal within one frame ~s lost due to a variation in the characteristics of the transmitter, such as distortion of the signal 2 ~

waveform caused by noise during the data l~ icn a IllGnlcllt~y los of signal caused by a cut ofthe line, or the like, the frame phase on the receiver side deviates and an ullsyllcl~ol~cd frame state occurs. Once the un;"rll~,hrol~ed frame date occurs, frame syn,l rol ization cannot be recovered, normal data ll~ns...;Q~;on is prevented, and this un~nchrol~cd frame state can only be detected by the abnollllal state ofthe r~ccivcd data, which causes a problem in operation.
[Disclosure of the Invention]
In accolJ~ ce with an embodiment ofthe present invention there is provided a modulator-demodulator device capable of del~L;ng an ~Ir,s~n.,l.lolfi~cd frame state, characterized in that a receiver device, co~ ed to a nctw~lk in which data to be ~ s. . .;1 led is mi Yimllm likelihood coded and phase modllli~ted and the coded and modlllsfed data are ll~n~.. ;lled The device COIIl~liScS. d~nodll~ tor means for demodlll~ting the phase modlll~te~l data; compe~-Q~ g means for co...~ g for signal deterioration in the rotation of the demodlll~ted base band signal;
pluAhndle signal point deci~ing means for de~ ling one signal point in the pro~hll,ly of the co...l c~Y(ed signal from a plurality of received ideal signal points with respect to the col-.p~nc~ed signal delivered from said conl~en~lil~g means; n~;.n.. Iikelihood signal point desi~lin~ means for decoding the m~x1mum likelihood coded data, de~ in~ the ~a";~n.~n~ likelihood coded data by using the c~.n~ ,t;,~ signal delivered from the co-n~.sating means, and delivering the result of the decision; means for COIllpaling the compel-F~ed signal and a hard decision signal point delivered by the pro~ ale signal point deci~1in~ means and deriving a first error; means for comparing the compe~-s~ed signal and the l-.q,~;ln.. n likelihood signal point delivered by the maximum likelihood signal point dcli:~;;led by the ll~nwll likelihood signal point deci~ing means and deriving a second error, and means for deriving the dirrerellce b~t~cel the first error and the second error; the un~nchlol~od frame state B

being detected based on the derived difference.
[Brief Description of the Drawings]
In the drawing, Fig. 1 shows a modulator-demodulator device according to one embodiment;
Fig. 2 shows waveforms of signals for explaining the operation of the device shown in Fig. l;
Fig. 3 shows an arrangement of signal points in Trellis coding modulation;
Fig. 4 shows a modulator-demodulator device according to another embodiment; and Fig. 5 shows waveforms of signals for explaining the operation of the device shown in Fig. 4.
[Best Mode for Carrying out the Invention]
A modulator-demodulator (modem) device according to one embodiment is shown in Fig. 1.
The operation of the modem shown in Fig. 1 is illustrated in Fig. 2 and Fig. 3.
In the modem of Fig. 1, in the transmitter side, the signal to be transmitted is rotated on a complex plane based on the frame phase, and in the receiver side, the received signal point is rotated on a complex plane in the reverse direction of that of the transmitter side to be returned to the original position. The unsynchronized frame state is then decided based on the difference between the distance of hard decision and the distance of soft decision. In a network where the unsynchronized state does not occur frequently, the hard decision signal point and the soft decision signal are usually the same point, and, in such a case, the unsynchronized state is determined and detected by the fact that the difference ~1 67742 between the errors of these two points is zero, and that the difference between the errors of these two points will increase when an unsynchronized state occurs. Therefore, the difference between the hard decision value and the receiving signal, i.e., the first error, and the difference between the soft decision value and the receiving signal, i.e., the second error are calculated, the difference between the first error and the second error is obtained by, for example, subtraction, the obtained value is subject to an integration operation, or the like to determine a mean value, and then the unsynchronized frame state can be decided when the mean value is more than a predetermined value.

In the device of Fig. 1, the transmitter side 1 includes a bit processing circuit 10 for delivering the bit sequence of the transmission data at predetermined intervals, a frame phase generating circuit 12 for generating frame phase information by which the interval of an integer N times the interval of the bit sequence is made one frame, a training signal generating circuit 14 for generating a training signal including a frame synchronization signal prior to the data transmission, a Trellis coding circuit 16 as the error control coding circuit for adding redundancy according to a predetermined procedure to the bit sequence to be transmitted from the bit processing circuit 10 and coding the bit se~uence, a data sequence to coordinate transforming circuit 18 for transforming the bit sequence from the error control coding circuit 16 into the coordinates of a signal point on the complex plane, a coordinate rotating circuit 20 for rotating the transformed coordinates of the signal point transformed by the data sequence to coordinate transforming circuit 18 based on the frame phase information from the frame phase generating circuit 12, and modulation means 24 for phase-modulating or quadrature-modulating the output of the coordinate rotating circuit 20 and delivering the modulated output to the communication network 6.
The receiver side 2 includes a demodulation circuit 26 for demodulating the coordinates of the received signal point on.the complex plane for the signal from the communication network 6, a frame phase detecting circuit 32 for controlling the delay amount r of the variable delay circuit 30 to cause coincidence between the frame phase from the frame phase generating circuit 28 and the received frame phase from the variable delay circuit 30, a coordinate rotating circuit 34 for applying rotation in the reverse direction of that of the coordinate rotation in the transmitter side based on the frame phase information of the frame phase .1._ generating circuit 28, a first decision circuit 36 for deciding the nearest signal point among the signal points on the complex plane having the possibility of transmission with respect to the signal receiving point coordinates delivered from the coordinate rotating circuit 34 as the hard decision, a second decision circuit 38 for deciding the maximum likelihood signal point by utilizing the rédundancy added by the error control coding means 16 of the transmitter side and correcting the coordinate error of the received signal point, and an unsynchronized frame state deciding circuit 5 for deciding the unsynchronized frame state based on the distance between the decision point by the first and/or the second decision circuit 36, 38 and the modulated received signal point on the complex plane.
The unsynchronized frame state decision circuit 5 decides the unsynchronized frame state based on the difference between the distance between a point decided by the first decision circuit 36 and the demodulated receiving point, and the distance between a point decided by the second decision circuit 38 and the demodulated receiving point.
Concretely, the unsynchronized frame state decision circuit 5 calculates the distance between the decision point of the first decision circuit 36 and the demodulated receiving point as a first decision error El as the hard decision error, calculates the distance between the decision point of the second decision circuit 38 and the demodulated receiving point as a second decision error as the soft decision error E2, and decides the unsynchronized frame state when the mean value of the differences between the first decision error E1 and the second decision error E2, "El - E2", becomes more than a predetermined threshold value.
Each of the frame phase generating circuits 12 and 32 generates, as shown in Fig. 2, frame phase information for dividing one frame into the first half 2 ~ 67742 .~,...

frame and the latter half frame. The coordinate rotating circuit 20 of the transmitter side causes a predetermined coordinate rotation of the signal point coordinates included in the first half frame, leaving the signal point coordinates included in the latter half frame not rotated. The coordinate rotating circuit 30 of the receiver side causes a predetermined coordinate rotation of the receiving point coordinates included in the first half frame in the reverse direction of that of the transmitter side, leaving the receiving point coordinate included in the latter half frame not rotated.
The relation between coordinate rotation and non-rotation in the first half frame and the latter half frame is not limited to the above described relation, but conversely, the first half frame can be of non-rotation and the latter half frame can be of rotation.
Further, each of the frame phase generating circuits 12 and 32 respectively provided in the transmitter side and the receiver side generates the same frame phase information independently and asynchronously.
In the device shown in Fig. 1, reference numeral 1 denotes the transmitter side, 2 denotes the receiver side, and the transmitter side 1 and the receiver side 2 are connected to each other via the communication network 6. The device of Fig. 1 carries out data transmission at a transmission speed of 14400 bps.
In the transmitter side 1, the bit processing circuit 10 receives the transmission data from the appropriate terminal. The bit processing circuit io divides the bit sequence of the transmission data into each modulation bit, carries out processing such as scrambling or the like, and delivers the scrambled data.
Since the transmission speed of the device of Fig. 1 is 14400 bps, 14400 bps divided by 2400 bps gives 6 bits.

g That is, the bit processing circuit 10 outputs a bit sequence of 6 bits per modulation "Q6n Q5n Q4n Q3n Q2n Qln".
The bit sequence of 6 bits is supplied from the bit processing circuit 10 to the Trellis coding circuit 16 as the error control coding circuit, and the Trellis coding circuit 16 delivers a bit sequence of 7 bits including one bit of redundancy in accordance with a predetermined rule. In this case, the Trellis coding circuit 16 inputs a lower 2 bits "Q2n Qln" of the bit sequence from the bit sequence processing circuit 10 into the coding circuit including a differential coder and a convolution coder, and generates a subset of 3 bits "Y2n Yln YOn". The 3-bit subset is combined with the upper 4 bits, and the bit sequence of 7 bits "Q6n Q5n Q4n Q3n Y2n Yln YOn~ is generated.
The output of the Trellis coding circuit 16 is supplied to the data sequence to coordinate transforming circuit 18 through the switching circuit 42. The switching circuit 42 switches the outputs of the Trellis coding circuit 16 and the training signal generating circuit 14. Namely, the switching circuit 42 selects the training signal from the training signal generating circuit 14 prior to the data transmission, and causes the pulling-in of the automatic equalizer of the receiver side 2 by the training signal from the training signal generating circuit 14.
In the device of Fig. 1, the frame synchronization signal is included in the training signal generated in the training signal generating circuit 14. This frame synchronization signal is detected from the training signals in the receiver side, and the frame synchronization control is carried out during a training time. Needless to say, the switching circuit 42 seiects the output of the Trellis coding circuit 16 during the data transmission.
The data sequence to coordinate transforming '_ 21 67?42 circuit 18 transforms the bit sequence of 7 bits obtained from the Trellis coding circuit 16 to the coordinates representing the signal point on the complex plane. For example, the data sequence to coordinate transforming circuit 18 delivers the coordinate value of the signal point on the complex plane, indicated by a black point in Fig. 3, having a binary number of the bit sequence of 7 bits arranged according to the arrangement of signal points in Trellis coding modulation shown in Fig. 3, i.e., the coordinate data constituted by the real number axis (Re) amplitude and the imaginary number axis (Im) amplitude. In the signal point arrangement shown in Fig. 3, A, B, C, and D are the signal points for low speed in the first half portion of the training signal.
Following the data sequence to coordinate transforming circuit 18, the coordinate rotating circuit 20 is provided for applying a predetermined rotation to the signal point coordinate on the complex plane from the data sequence to coordinate transforming circuit 18 based on the frame phase information from the frame phase generating circuit 12.
The frame phase generating circuit 12 is actuated when the power supply is turned on and independently operated for dividing, one frame constituting 8 - modulations into the first half frame and the latter half frame, as shown in frame phase information of transmitter side (Fig. 2 (2)).
According to the frame phase information from the frame phase generating circuit 12, the coordinate rotating circuit 20 applies the rotation 0 on the complex plane, for example the rotation of 0 of +9~~, for example the clockwise rotation of 90~ on the complex plane shown in Fig. 3, to the signal point coordinates from the data sequence to coordinate transforming circuit 18 included in the first half frame A, leaving the lower signal coordinate included in the latter half .,_ frame not rotated, and repeats the same operation for each frame.
The output of the coordinate rotating circuit 20 is supplied to the modulation circuit 24, modulated by phase-modulation, quadrature modulation, or the like, and the modulated output is delivered to the communication network. In other words, in the modulation circuit 24, the real number axis (Re) amplitude of the signal point coordinates delivered ~rom the coordinate rotating circuit 20 is modulated by sin~t, the imaginary number axis (Im) amplitude of the signal point coordinate is modulated by 90~ advanced sin~t, and after both components are composed together, the composed data is delivered to the communication network 6.
In the receiver side, reference number 26 indicates a demodulation circuit for demodulating the receiving point coordinates, i.e., the signal point coordinates from the signal received from the communication network 6. In other words, the real number axis (Re) amplitude is decided by detecting the synchronization of the received signal by coswt, and the imaginary number axis (Im) amplitude is decided by detecting the synchronization by sin~t. The demodulation circuit 26 includes, of course, a circuit for eliminating the network deterioration factor, such as an automatic equalizer and the like.
Following the modulation circuit 26, the frame phase generating circuit 28, the variable delay circuit 30 and the frame phase detecting circuit 32 are provided for carrying out synchronization control of the frame phase.
The frame phase detecting circuit 32 detects the frame synchronization signal included in the training signal from the transmitter side 1, and adjusts the delay amount r of the variable delay circuit 30 so that the frame phase information from the frame phase , ,_ generating circuit 28 of the receiver side 2 is coincident with the phase of the frame phase information of the transmitter side of the frame phase generating circuit 12 in the transmitter side.
Both the frame phase generating circuit 12 of the transmitter side and the frame phase generating circuit 28 of the receiver side an independently actuated when the device is powered up for generating the frame phase information of the frame divided into the first half frame and the latter half frame, however, the coincidence between the frame phases of the transmitter side and the receiver side is not established. In the frame phase detecting circuit 32, the frame phase of the transmitter side is decided by the frame synchronization signal detected from the training signals, the error of the frame phase of the receiver side in relation to the frame phase of the transmitter side, i.e., the delay amount r, is obtained, and the delay amount of the variable delay circuit 30 is adjusted accordingly.
According to the signal delay by the variable delay circuit 30, the frame phases of the frame phase generating circuits 12 and 28 of the transmitter side and the receiver side may made coincident with each other.
The coordinate rotating circuit 34 applies rotation in the reverse direction of that of the transmitter side on the complex plane to the receiving point coordinate obtained through the variable delay circuit 30 based on the frame phase information from the frame phase generating circuit 28.
In the device of Fig. l, in the transmitter side, the coordinate rotating circuit 20 of the transmitter side applies the rotation of, for example, o of, for example, +90~ for the first half frame, leaving the latter half frame not being rotated, thus the coordinate rotating circuit 34 applies the rotation 0, i.e., -90~
as 0, in the reverse direction of that of the transmitter side, to the receiving point coordinates included in the first half frame based on the frame phase information from the frame phase generating circuit 28, leaving the latter half frame not rotated.
Therefore, the signal point coordinates rotated by the coordinate rotatinq circuit 34 in the transmitter side returns to the initial signal point coordinates before being rotated in the receiver side, provided that the frame synchronization is properly established.
The receiving point coordinates from the coordinate rotating circuit 34 are delivered to each of the first decision circuit 36 as the hard decision means and the second decision circuit 38 as the soft decision means.
The first decision circuit 36 decides the nearest signal point among the signal points on the complex plane having the possibility of transmission, and delivers the coordinate point closest to the received signal point as the decision point.
The second decision circuit 38 decides the maximum likelihood signal point on the complex plane preliminarily determined by utilizing the redundancy bit according to the Trellis coding performed by the Trellis coding circuit 16 of the transmitter side, and corrects the error of the received signal point. For example, the second decision circuit 38 sets the evaluation value for each of the transition sequence of a plurality of the received signals based on the transition rule in accordance with the Trellis coding in the transmitter side, updates the evaluation value for each receipt of the signals, and selects the transition sequence of the maximum likelihood received signal based on the updated evaluation numeral to correct the error in the demodulated signal point. This operation is referred to as a Viterbi decoding decision. For an explanation of Viterbi decoding decision, refer to, for example, "The Viterbi Algorithm", Proceedings of the IEEE, Vol. 61, No. 3, Pages 268-278, published by I.E.E.E., U.S.A., ..

March 1973.
The si~nal point decided by the second decision circuit 38 is delivered to the coordinate to data sequence transforming circuit 44, and the coordinate to data sequence transforminq circuit 44 is provided with the mapping circuit having binary numbers of the 6-bit data for each of signal point arrangements. The decision coordinate point is transformed into 6-bit data, and the transformed data is delivered to a bit processing circuit 46. The bit processing circuit 46 carries out descrambling and the like, combines the 6-bit data, and delivers the received data to the terminal.
Further, in the device of Fig. 1, the unsynchronized frame state decision circuit 5 is provided. For the unsynchronized frame state decision circuit 5, the demodulated receiving point from the coordinate rotating circuit 34, the hard decision point from the first decision circuit 36, and the soft decision point from the second decision circuit 38 are delivered.
The unsynchronized frame state decision circuit 5 is constituted by error calculating circuits 50 and 52, difference calculating circuit 54, mean value determining circuit 56, and decision circuit 58.
The error calculating circuit 50 calculates the distance on the complex plane between the demodulated receiving point and the decision point of the first decision circuit 36 to derive a hard decision error El.
The error calculating circuit 52 calculates the distance on the complex plane between the demodulated receiving point and the soft decision point of the second decision circuit 36 to derive a soft decision error E2.
The hard decision error E1 calculated by the error calculating circuit 50 and the soft decision error E2 calculated by the error calculating circuit 52 are _ delivered to the difference calculating circuit 54, and the difference between the decision errors 'E2 - E1" is calculated in the difference calculating circuit 54.
The output of the difference calculating circuit 54 is supplied to the mean value determining circuit 56. The mean value determining circuit 56 determines the mean difference value between, for example, several frames.
Finally, the decision circuit 58 compares the determined mean value with a predetermined threshold value, and generates an output decision of an unsynchronized frame state when the mean value becomes more than the predetermined threshold value.
Next, the operation of the device of Fig. 1 will be described referring to the signal waveforms shown in Fig. 2.
When the power is switched on in the transmitter side 1 and the receiver side 2, the frame phase generating circuit 12 of the transmitter side 1 and the frame phase detecting circuit 32 of the receiver side 2 are independently actuated, and generate frame phase information indicating the first half frame and the latter half frame independently (Figs. 2 (2) and (6)).
The switch circuit 42 is switched to the training signal 14 side, and the training signal including the frame synchronization signal is transmitted from the training signal generating circuit 14 to the receiver side 2. The receiver side 2, upon the receipt of the training signal from the transmitter side 1, carries out the network compensation processing including the pulling-in of the automatic equalizer provided in the demodulation circuit 26 and the like, detects the frame synchronization signal included in the training signal by the frame phase detecting circuit 32, and detects the timing of the frame phase of the frame phase generating circuit 12 of the transmitter side 1. Thus, in the frame phase detecting circuit 32, the phase error between the frame phase information of the transmitter .. 21 67742 side and the frame phase information of the receiver side, i.e., the delay amount r ~ is detected, and the frame phase detecting circuit 32 adjusts the delay amount of the variable delay circuit 30 ~o the detected delay amount r. Accordingly, even if the coincidence between the frame phases of the transmitter side and the receive side is not established, the frame of the received signal obtained through the signal delay of the variable delay circuit 30 becomes coincident with the frame phase information of the frame phase generating circuit 28 by setting the delay amount r of the variable delay circuit 30 based on the frame synchronization signal .
Upon the completion of transmission of the training signal, the transmitter side 1 starts the transmission of data from the terminal.
In the bit processing circuit 10, the bit sequence of 6 bits per modulation is derived from the transmission data synchronously with the modulation synchronization signal, a single redundancy 1 bit is added to the 6 bit sequence by coding the lower 2 bits in the Trellis coding circuit 16 to transform the 6 bit sequence to a 7 bit sequence, and the transformed bit sequence is delivered to the data sequence to coordinate : transforming circuit 18 through the switch circuit 42.
An example of the signal point arrangement in the Trellis coding modulation is shown in Fig. 4. The data sequence to coordinate transforming circuit 18 transforms the 7 bit sequence to the signal point coordinates by a mapping circuit having a signal point arrangement corresponding to the binary numbers of the 7 bit sequence delivered from the Trellis coding circuit, and delivers the transformed data to the coordinate rotating circuit 20.
Frame phase information is supplied from the frame phase generating circuit 12 to the coordinate rotating circuit 20, and the coordinate rotating circuit 20 _ 2167742 causes a predetermined coordinate rotation o of, for example, +90~ as 0 on the complex plane, of 4 signal point coordinates included in the first half frame of the frame phase information, leaving the 4 signal - coordinates included in the latter half frame not rotated, and delivers the signal point coordinates to the modulation circuit 24. Thus, the signal point coordinates successively delivered through the coordinate rotating circuit 20 are modulated in the modulation circuit 24, and the modulated signal point coordinates are delivered to the communication network 6. In this case, the real number axis (Re) coordinate value is modulated by coswt, while, the imaginary number axis (Im) coordinate value is modulated by 90~ advanced sinwt, and the synthetic signal of both components is delivered to the communication network.
In the receiver side 2, the signal point coordinates are demodulated from the received siqnal from the communication network 6 by the demodulation circuit 26, the variable delay circuit 30 applies the signal delay of delay amount r, which is set while receiving the training signal, to the demodulated signal point coordinates so that the signal point coordinates as synchronized with the frame phase and delivered to the coordinate rotating circuit 34. Based on the phase information from the frame phase generating circuit 28, i.e., the frame phase information (Fig. 2 (6)), the coordinate rotating circuit 34 causes the coordinate rotation 0, for example 0 = -90~, in the reverse direction of that of the transmitter side for the receiving point coordinates of the first half frame of one frame, leaving the latter half frame thereof not rotated. Thus, the receiving point delivered from the coordinate rotating circuit 34 returns to the original signal point before being rotated in the transmitter side.
The receiving point coordinates rotated by the ~ - 18 -coordinate rotating circuit 34 are delivered to the second decision circuit 38. The second decision circuit 38 corrects the error of the demodulated receiving point by deciding the maximum likelihood signal point on the complex plane according to the Viterbi decoding processing, the coordinate to data sequence transforming circuit 44 transforms the error-corrected received signal point to 6 bit data using the mapping circuit, the bit processing circuit 46 carries out processing such as de-scrambling and the like on the 6 bit data, then after that, combines the 6 bit data of each successive modulation, and transmits the combined data to the appropriate terminal side.
In the unsynchronized frame state decision circuit 5, the error calculating circuits 50 and 52 calculate the hard decision error El and the soft decision error E2 by using the decision point obtained from the first decision circuit 36 and the second decision circuit 38 at each of the received modulation signal of one modulation, the difference operation circuit 54 finds the difference between the errors, the mean value determining circuit 56 determines the mean value with respect to a predetermined number of frames, and compares the result with predetermined threshold value ~ which is set in the second decision circuit 58.
One or more modulation signals may be missing due to an instantaneous interruption caused by switching a connection or the like on the communication network 6 during data transmission between the transmitter side 1 and the receiver side 2. In this case, the number of the modulation synchronization signal (Fig. 2 (8)) becomes 7 or less in one frame interval, and the frame phase of the receiver side is deviated. When the frame phase of the receiver side is deviated, the modulation signal included in the rotated frame of the transmitter side does not correspond to the timing of the frame of reverse rotation in the receiver side but corresponds to 2t 67742 '_ the non-rotated frame, o~ in the transmitter side, the modulation signal included in the non-rotated frame corresponds to the frame of reverse rotation in the receiver side. Accordingly, even if the coordinate rotating circuit 34 of the receiver side 2 applies the reverse rotation to the transmitter side, the signal point does not return to its initial position. Thus, when the frame phase is deviated, the continuity of the demodulated receiving point is destroyed and a significant soft decision error E2 is caused with respect to the decision point of the second decision circuit 38. Since lost frame synchronization cannot be recovered, the mean value of the mean value determining circuit 56 becomes more than the threshold value of the second decision circuit 58. Thus, the output of decision of an unsynchronized frame state can be obtained.
If the decision output of the unsynchronized frame state decision circuit 5 is obtained, the system is in a state in which data transmission is impossible. In that case, the normal data transmission can be restored by restarting both the transmitter side and the receiver side, and commencing again the transmission of the training signal.
Further, in the unsynchronized frame state decision circuit 5, the unsynchronized frame state is decided based on the mean value of the hard decision error El and the soft decision error E2, and accordingly the unsynchronized frame state can be exactly decided by eliminating the error caused by the characteristics of the communication network. In other words, both the hard decision error E1 and the soft decision error E2 significantly change according to the characteristics of the network, and if the network characteristics are stable, the unsynchronized frame state can be decided only by detecting an increase in the soft decision errors due to the unsynchronized frame state.

In the device of Fig. 1, the rotation and reverse rotation are carried out only for the first half frame of the frame phase information of the transmitter side. Another way, i.e., non-rotation of the first half frame and rotation and reverse rotation of the latter half frame, may be used to obtain the same effect.
Also, in the device of Fig. 1, the frame phase information is divided into the first half frame and the latter half frame, but other frame phase information with frames divided into 3 divisions, 4 divisions, or another appropriately selected division of frame phase information may be used.
Further, the device of Fig. 1 is an example in which the rotation of the signal point coordinates by 90~ is carried out on the complex plane, but other rotation angles may be used provided that the rotation angle is appropriately selected so that an adequate soft decision error can be obtained according to the unsynchronized frame state.
The device according to another embodiment is shown in Fig. 4. The operation of the device of Fig. 4 is illustrated in Fig. 5.
The device shown in Fig. 4 is technically closely related to the device of Fig. 1, and it is preferable to use the technology of the device of Fig. 1 together with the technology of the device of Fig. 4.
In the device of Fig. 4, the transmitter side 1 and the receiver side 2 are connected through the communication network 6 such as a telephone network and the like, user data to be transmitted by the transmitter side 1 is coded for error control, and is then modulated by phase-modulation or quadrature modulation and delivered to the communication network 6. In the receiver side 2, the received signal from the communication network 6 is demodulated, errors are corrected by the maximum likelihood signal point decoding, and the transmission data (user data) is ._ reproduced.
First, the transmitter side 1 will be described.
In the transmitter side 1, a bit processing circuit 300 is provided. The transmission data is supplied from the user transmission terminal to the bit processing circuit 300, the transmission data is processed by bit processing such as scrambling or the like, and the transmission data is divided into the number of bits to be transmitted for each modulation, and is then delivered. For example, the bit processing circuit 300 outputs a bit sequence of 6 bits per modulation "Q6n Q5n Q4n Q3n Q2n Qln", where n is an integer indicating the modulation number.
Reference numeral 180 denotes a selector switch as a second delivery signal selector means. The selector switch 180 switches the output of the bit processing circuit 300 and the output of a high speed signal generating circuit 280 to an error control coding circuit (Trellis code circuit) 110. That is, the selector switch 180 delivers the high speed signal from the high speed signal generating circuit 280 for a predetermined time period from the start of coding and decoding at the start stage prior to the transmission of the transmission data, after that, switches to the output of the transmission data from the bit processing circuit 300.
The Trellis coding circuit 110 as the error control coding means carries out coding for controlling errors according to a transition rule which restricts the transition on the complex plane of the signal point for transmitting in accordance with a predetermined procedure, with respect to the transmission signal.
To the Trellis code circuit 110, the bit sequence of 6 bits per modulation "Q6n Q5n Q4n Q3n Q2n Qln" is supplied from the bit processing circuit 300 via, for example, the selector switch circuit 180. The subset "Y2n Yln Yn" to which the redundancy l bit is added by coding the lower 2 bits "Q2n Qln" of the above mentioned bit sequence by using the differential coder and the convolution coder, is produced. The 7 bit sequence including this subset and the upper 4 bits "Q6n Q5n Q4n Q3n", i.e., the bit sequence constituted by 6 bits and l added redundancy bit is coded as ~Q6n Q5n Q4n Q3n Y2n Yln YOn", and this coded signal is delivered.
The output of the Trellis code circuit 110 is supplied to the bit sequence to coordinate transforming circuit 340, and this bit sequence to coordinate transforming circuit 340 outputs the signal point coordinate on the phase plane as the complex plane corresponding to the transmission bit sequence.
The signal point coordinate on the complex plane with respect to the input 7 bit sequence from the Trellis code circuit 110 transformed by the bit sequence to coordinate transforming circuit 340 is, for example, as shown in Fig. 3.
The output of the bit sequence to coordinate transforming circuit 340 is supplied to the modulation circuit 140 through the selector switch circuit 160 which is the first delivery signal selector means. The selector switch circuit 160 switches the output of the bit sequence to coordinate transforming circuit 340 and the output of the low speed signal generating circuit 260 which comprise the non-coded signal generating circuit to the modulation circuit 140, and at the actuation stage prior to the transmission of the transmission data, the selector switch circuit 160 selects the output of the low speed signal generating circuit 260, delivers the low speed signal to the communication network 6 through the modulation circuit 140 for a predetermined time period, and selects the output of the bit sequence to coordinate transforming : circuit 340, i.e., the signal output coded by the Trellis code circuit llO upon the completion of the delivery of the low speed signal.

The modulation circuit 140 generates the modulation signal corresponding to the coordinate input of the transmission signal point on the complex plane, or more concretely, modulates the rear number axi-s (Re) amplitude in the signal point input coordinate on the complex plane by amplitude modulation by coswt, further modulates the imaginary number axis (Im) amplitude by amplitude modulation by sinwt having a 90~ leading phase, combines these components, and delivers these combined data to the communication network 6.
In the receiver side 2, reference numeral 200 indicates a demodulation circuit which demodulates the modulation signal received from the communication network 6, and outputs the coordinates of the received -- signal point on the complex plane. In other words, the real number axis (Re) amplitude component and the imaginary number axis (Im) amplitude component are reproduced by detecting synchronization of the received modulation signal by respective coswt and sinwt, and the coordinate data of the received signal point is detected.
The demodulated output from the demodulation circuit 200 i.e., the coordinate data of the received signal point, is supplied to the error control signal decoding circuit 220 as the error control decoding means, which corrects the error of the received signal point from the demodulation circuit 200 by selecting the transition sequence of the maximum likelihood received signal utilizing the transition rule of the signal point restricted in the transmitter side, and by delivering the maximum likelihood signal point coordinate on the complex plane according to the selected transition sequence.
The error control signal demodulation circuit 220, having the evaluation value for each of a plurality of the receiving sequences defined by the transition rule of the signal point restricted by the transmitter side, updates the evaluation value at every receipt of the signal, and corrects the error of the received signal point by selecting the signal sequence of the maximum likelihood received signal based on the updated evaluation value.
The coordinate data of the receiving point the error of which is corrected by the maximum likelihood decoding circuit 220 is supplied to the coordinate to bit sequence transforming circuit 360. The coordinate to bit sequence transforming circuit 360 delivers the bit sequence corresponding to the input receiving point coordinates on the complex plane. The device of Fig. 4 is an example of the case in which the bit sequence of 6 bits per modulation is transmitted, thus, the bit sequence "Q6n Q5n Q4n Q3n Q2n Qln" is delivered from the coordinate to bit sequence transforming circuit 360.
The bit sequence delivered from the coordinate to bit sequence transforming circuit 360 is supplied to the bit processing circuit 380 which joins the bit sequences divided per 1 modulation, carries out the bit processing such as the scrambling and the like on each of bit sequences, and delivers the receiving data to the terminal of the receiver side.
Further, in the device of Fig. 4, the evaluation value setting circuit 240 is provided against the error control signal decoding circuit 220 provided in the receiver side. The evaluation value setting circuit 240 designates to the error control signal decoding circuit 220 the evaluation value which is updated by the first received high speed signal when the transmission signal from the transmission side 1 is switched from a non-coded low speed signal to the coded high speed signal. For the evaluation value to be designated by the evaluation value setting means 240, the evaluation value which represents the transition sequence o~ the received signal available for the error control signal decoding circuit 220 when the number of received coded ' ".., high speed signals delivered from the transmitter side 1 is more than a predetermined number.
The operation of the device of Fig. 4 will be described with reference to Fig. 5.
When the transmitter side 1 receives the transmission request from the terminal side at the time tl, the selector switch circuit 160 switches to the low speed signal generating circuit 260 side, the low speed signal is supplied from the low speed signal generating circuit 260 to the modulation circuit 140 through the selector switch circuit 160, and the low speed signal modulated by the modulation circuit 140 is delivered to the communication network 6. The receiving signal from the communication network is demodulated by the demodulation circuit 200, the low speed signal is reproduced, and the actuation of the error control signal decoding circuit 220 provided in the receiver side 2, the coordinate to bit sequence transforming circuit 360, the bit processing circuit 380, and other necessary circuit portions, is carried out. When the actuation operation is carried out upon the reception of a low speed signal, the decoding operation by the error control signal decoding circuit 220 is not carried out.
When a predetermined time period from the time tl has elapsed, i.e., when the transmission of the low speed signal of a predetermined number covering successive data is completed, the selector switch circuit 160 cuts off the output of the low speed signal generating circuit 260 and connects the output of the bit sequence to coordinate transforming circuit 340 to the modulation circuit 140. At the same time, the selector switch circuit 180 selects the output of the simultaneously actuated high speed signal generating circuit 280 at a timing of completion of the low speed signal generating circuit 260, and supplies the high speed signal having the bit pattern predetermined for this transmission system.

~ 21 67742 ~ - 26 -The high speed signal generating circuit 280outputs the bit sequence of 6 bits having a predetermined fixed bit pattern, and the bit pattern is either the repetition of the same pattern or the repetitive output of a plurality bit patterns which change in accordance with a predetermined procedure.
The first coded high speed signal is demodulated by the demodulation circuit 200 in the receiver side 2, and the signal point coordinate data is supplied to the error control signal decoding circuit 220, then the time period of the low speed signal is measured by a timer (not shown) in the receiver side, and when a predetermined time period is elapsed, the timing of supply of the signal point coordinate data is identified. The error control signal decoding circuit 220 updates the evaluation value which is predetermined by the evaluation value setting means 240 based on the received and demodulated signal point coordinate at this timing, and, based on the updated evaluation value, the error of the demodulated signal point coordinates is corrected so that the signal point coordinate in accordance with the transition sequence of the receiving signal is realized.
When the first coded high speed signal is received, the high speed signal previously coded is not demodulated in the error control signal decoding circuit 220, therefore, an evaluation value to be updated does not exist in that circuit 220. However, in the device of Fig. 4, in appearance, the same state as the state in which more than a predetermined number of the high speed signals has been received and the error control signals have been demodulated is established by the evaluation value setting means 240. Therefore, in the device of Fig. 4, the evaluation value of the receiver side is a ~ numeral having continuity from the viewpoint of the transition rule of the transmission signal, and reliable correction of the error can be carried out in the error ~ 2167742 control signal decoding circuit 220 even immediately - after the switching transmission of the decoded high speed signals.
The receiving signal point coordina~tes the error of which is corrected by the error control signal decoding circuit 220, are transformed into the bit sequence of 6 bits by the coordinate to bit sequence transforming circuit 360, and after that, are transformed to the receiving data in which the bit sequence divided at each modulation by the bit processing circuit 380, and these bit sequences are connected in sequence.
When the transmission of the high speed signals is completed at the time t3 after a predetermined time period from the time t2 has elapsed, the selector switch circuit 180 of the transmitter side 1 cuts off the output of the high speed signal generating circuit 280, connects the output of the bit processing circuit 300 to the error control coding circuit 110, carries out the bit processing such as the scrambling and the like on the transmission data, divides the data into 6 bit sequences at each 1 modulation and delivers them to the error control coding circuit 110, and in the same way as the high speed signal, causes coding for controlling errors, and delivers the data to the receiver side 2 so the correct data can always be received in the receiver side 2 due to the error correction by the error control signal decoding circuit 220.
Although the device of Fig. 4 is an example of the device in which the data divided into the bit sequence of 6 bits per modulation is transmitted, the device according to the present invention is not restricted to this example, and the number of bits per 1 modulat~ion may be appropriately selected based on the transmission speed.

~7a C/~ 2 1 6 7 7 4 2 . .

[CORRESPONDENCE BETWEEN REFERENCE NUMERALS AND MATTERS]
1 ... transmitter side ... bit processing circuit 14 ... training signal generating circuit 16 ... error control coding circuit 42 ... switch 18 ... data sequence to coordinate transforming circuit 12 ... frame phase generating circuit ... coordinate rotating circuit 24 ... modulation circuit 6 ... communication network 2 ... receiver side 26 ... demodulation circuit 28 ... frame phase generating circuit ... variable delay circuit 34 ... coordinate rotating circuit 36 ... first decision circuit 38 ... second decision circuit 44 ... coordinate to data sequence transforming circuit 46 ... bit processing circuit ... unsynchronized frame state decision circuit ... error calculating circuit 52 ... error calculating circuit 54 ... difference calculating circuit 56 ... mean value calculating circuit 58 ... decision circuit ~'~s,~ rl~h~

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS;

1. A modulator-demodulator device capable of detecting a frame unsynchronized state of a receiver device connected to a network through which a data to be transmitted are maximum likelihood coded and phase modulated, and the coded and modulated data are transmitted, in which said receiver device comprises:
demodulator means for demodulating the phase modulated data;
compensating means for compensating for signal deterioration in rotation of the demodulated base band signal;
proximate signal point deciding means for deciding one signal point in the proximity of the compensated signal from a plurality of received idea signal points with respect to the compensated signal delivered from said compensating means;
maximum likelihood signal point deciding means for decoding the maximum likelihood coded data, deciding the maximum likelihood coded data by using the compensating signal delivered from said compensating means, and outputting the result of the decision;
means for comparing the compensated signal and the one signal point and the maximum likelihood signal point delivered by said proximate signal point deciding means and deriving a first error;
means for comparing the compensated signal and the maximum likelihood signal point delivered by said maximum likelihood signal point deciding means and deriving a second error; and means for deriving a difference between the first error and the second error;
the unsynchronized frame state being detected based on said derived difference.