CA2111680A1 - Power savings with ms-dos idle loop - Google Patents
Power savings with ms-dos idle loopInfo
- Publication number
- CA2111680A1 CA2111680A1 CA 2111680 CA2111680A CA2111680A1 CA 2111680 A1 CA2111680 A1 CA 2111680A1 CA 2111680 CA2111680 CA 2111680 CA 2111680 A CA2111680 A CA 2111680A CA 2111680 A1 CA2111680 A1 CA 2111680A1
- Authority
- CA
- Canada
- Prior art keywords
- processor
- idle
- interrupt
- sleeper
- data processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
Abstract
2111680 9306545 PCTABS00021 In a portable computer, a device driver program causes the system to conserve power whenever the processor is idle. The program detects the idle processor via a unique interrupt generated by the operating system's idle loop. After detecting the idle state, the program conserves power usage by slowing the system clock speed and halting the processor. The system returns to its normal operating state when the processor detects an external interrupt.
Although an operator action generates an external interrupt, the 55 ms periodic timer typically awakens the processor. In addition, the program blocks the power saving measures in cases where the operator would notice performance degradation.
Although an operator action generates an external interrupt, the 55 ms periodic timer typically awakens the processor. In addition, the program blocks the power saving measures in cases where the operator would notice performance degradation.
Description
WO 93/06545 PC~/US92/0440~
2 ~ 0 POWER SAVINGS WITH MS-DOS IDLE LOOP ~ ;
Back~round of the Invention ~ ;
Portable computers allow users to take computing power wherever they go. As portable computers become smaller and li~hter, their mobility increases. In addition, a portable computer's usefulness increases as ~ -~
processing power and battery life are increased.
All portables, however, are powered by batteries. The demand for smaller and lighter portables place restrictions on battery si~e. Presently, the battery pack in a six pound portable computer usually weighs approximately one pound. Thus, a portable computer's size and weight is significantly influenced by the battery. Manufacturars, therafore, are driven to produce portable computers with even smaller batteries. ~;
At the sarne time, manufacturers are driven to produce more powerful portables. Manufacturers have increased processing speeds and available memory. As a result, portable computers are approaching the capabilities of stationary personal computers. These perforrnance increases, howaver, place a greater drain on battery power.
A typical battery pack will power a notebook size computer for approximately two hours of continuous use. A portable computer's usefulness, as a result, is limited. By carrying a spare battery pack, a user can extend the portable computers usefulnass another two hours. However, , the additional battery pack reduces the compute~s portability. ; ~;
Sumrnary of the Invention ~ ~;
It is desirable to rQduce the drain of battery power without adversely affecting the user. In accordance with the present invention, battery power is conserved without any effort from the user or any noticeable affect on the computer's performance.
The present invention extends battery life by decreasing the power drain while the portable computer is idle~ Whenever the operating system waits for an event, it enters an idle sequence. The present invention takes -advantage o~ the idle sequence.
WO 93t06545 PCI'/US92J04405 ~ . ~
~9 2 . . ~
The invention comprises an idle state dstector, which detects an idle sequence, and a sleeper, which provides an instruction to halt the processor when the idle state detector detects the idle sequence. In the prefarred -embodiment, the idle sequence generates a unique interrupt. The uniqué
interrupt, in tum, triggers a specific interrupt handler. By thus de~ecting the unique interrupt, the specific interrupt handler detects the idie state. The sleeper is implemented as the specific interrupt handler program. Whenever the sleeper program executes, the processor is in the idle state.
In particuiar, the preferred slseper interrupt handler reduces the system clock speed, tums down hardware devices having a power saving mode, and hal~s the processor. The processor remains halted until an external interrupt occurs. After the processor services the external interrupt, -~
processing continues until the processor returns to the idle sequence. - -In the preferred embodiment, there are identified situations where -executing the sleeper program leads to noticeable performance degradation.
In response, the Applicant's invention includes a limiter, which detects the identified situations and prevents the sleeper from executing. In particular, the limiter sets a flag in shared data while an identified system service function is executing and maintains a cleared flag otherwise. In the prefarred smbodiment, both the sleeper and the limiter are interrupt handler programs installed ~s device drivers. Application program calls to MS-DOS
system services trigger execution of the limiter program. Any program call to the MD-DOS idle sequence causes the sleeper program to execute.
Bn_Description of Drawinqs Fig. 1 shows the logical system overview of a normal computer sy~tem operating under Microsoft DOS.
Fig. 2 shows the logical system overview of a computer systern cperating under Microsoft DOS and enhanced by the present invention.
Fig. 3 is a flowchart of the sleeper.
Fig. 4 is a flowchart of the limiter.
Description of the Preferred Embodiment ~ E
In the preferred embodiment, the portable computer is notebook :-~^ ' r .: . . . .
WO 93/06545 2 ~ 8 0 PCI/US92/04405 ~:
Back~round of the Invention ~ ;
Portable computers allow users to take computing power wherever they go. As portable computers become smaller and li~hter, their mobility increases. In addition, a portable computer's usefulness increases as ~ -~
processing power and battery life are increased.
All portables, however, are powered by batteries. The demand for smaller and lighter portables place restrictions on battery si~e. Presently, the battery pack in a six pound portable computer usually weighs approximately one pound. Thus, a portable computer's size and weight is significantly influenced by the battery. Manufacturars, therafore, are driven to produce portable computers with even smaller batteries. ~;
At the sarne time, manufacturers are driven to produce more powerful portables. Manufacturers have increased processing speeds and available memory. As a result, portable computers are approaching the capabilities of stationary personal computers. These perforrnance increases, howaver, place a greater drain on battery power.
A typical battery pack will power a notebook size computer for approximately two hours of continuous use. A portable computer's usefulness, as a result, is limited. By carrying a spare battery pack, a user can extend the portable computers usefulnass another two hours. However, , the additional battery pack reduces the compute~s portability. ; ~;
Sumrnary of the Invention ~ ~;
It is desirable to rQduce the drain of battery power without adversely affecting the user. In accordance with the present invention, battery power is conserved without any effort from the user or any noticeable affect on the computer's performance.
The present invention extends battery life by decreasing the power drain while the portable computer is idle~ Whenever the operating system waits for an event, it enters an idle sequence. The present invention takes -advantage o~ the idle sequence.
WO 93t06545 PCI'/US92J04405 ~ . ~
~9 2 . . ~
The invention comprises an idle state dstector, which detects an idle sequence, and a sleeper, which provides an instruction to halt the processor when the idle state detector detects the idle sequence. In the prefarred -embodiment, the idle sequence generates a unique interrupt. The uniqué
interrupt, in tum, triggers a specific interrupt handler. By thus de~ecting the unique interrupt, the specific interrupt handler detects the idie state. The sleeper is implemented as the specific interrupt handler program. Whenever the sleeper program executes, the processor is in the idle state.
In particuiar, the preferred slseper interrupt handler reduces the system clock speed, tums down hardware devices having a power saving mode, and hal~s the processor. The processor remains halted until an external interrupt occurs. After the processor services the external interrupt, -~
processing continues until the processor returns to the idle sequence. - -In the preferred embodiment, there are identified situations where -executing the sleeper program leads to noticeable performance degradation.
In response, the Applicant's invention includes a limiter, which detects the identified situations and prevents the sleeper from executing. In particular, the limiter sets a flag in shared data while an identified system service function is executing and maintains a cleared flag otherwise. In the prefarred smbodiment, both the sleeper and the limiter are interrupt handler programs installed ~s device drivers. Application program calls to MS-DOS
system services trigger execution of the limiter program. Any program call to the MD-DOS idle sequence causes the sleeper program to execute.
Bn_Description of Drawinqs Fig. 1 shows the logical system overview of a normal computer sy~tem operating under Microsoft DOS.
Fig. 2 shows the logical system overview of a computer systern cperating under Microsoft DOS and enhanced by the present invention.
Fig. 3 is a flowchart of the sleeper.
Fig. 4 is a flowchart of the limiter.
Description of the Preferred Embodiment ~ E
In the preferred embodiment, the portable computer is notebook :-~^ ' r .: . . . .
WO 93/06545 2 ~ 8 0 PCI/US92/04405 ~:
3 :
sizecl. The central procassing unit (CPU) is an Intel model 80386SX
rnicroprocessor, normally operating at 16 MHz. The system is operated under Microsoft DOS (MS-DOS).
Fig. 1 dopicts the normal operation of MS-DOS. The Intel farnily of processors support up to 256 interrupts, number3d 0 ~hrough 255. During initialization, the boot strap program ~reates a table 20 indexed by interrupt number for containing each interrupt's vector transfer address. The boot ;~
strap program, MS-DOS 30 and application programs 10 load th~ vectors for ~;
defined interrupts 22,24 into the table 20. The processor services interrupts - -~
by transferring control to the interrupt's vector address 22,24 which the processor looks up in the table 20. At the vector address is a program called an interrupt handler. Users, however, can causa a new interrupt handler to execute when the processor services a particular interrupt.
Although there are several methods for irnplementing interrupt handlers, MS-DOS provides standardized mechanisms. See e.~., R. Duncan, Advanced MS-DOS, pps. 207-257 (Microsoft Press 1986).
Application programs 10 communicate with MS-DOS 30 usiny software interrupts. When an application 10 requests a system service, it issues the system service interrupt 15. The processor reads the vector address 22 for the system service interrupt 15 from the vector table 20 and transfers control to the MS-DOS System Service 35. In the preferred embodiment, the system service interrupt 15 is interrupt number 33 (21 hex).
A code in the AH register identifies the particular system se~ice function 37 requested by the application program 10.
The system service function 37 may need to wait for an event. If that is the case, the ~unction 37 enters an idle loop 40. The processor continuously executes the instructions in the idle loop 40 until the awaited -event occurs. When the event occurs, control returns to the function 37, which then returns control to the application 10. One instruction in the idle loop 40 is an instruction to issue an idle loop interrupt 45. In the preferred embodiment, the idle loop interrupt 45 is interrupt number 40 (28 hox).
Upon receiving the idle loop interrupt instruction 45, the processor ' ~ . ;~-,,;
wog3/n6s4s ~ 6~ ` Pcr/us9~/o44os transfers control to the idle loop interrupt handler ~û based on the vector address 24. The idle loop interrupt handler 50 sxecutes its software instructions and returns control to the idle loop 40.
As depicted in Fig. 2, the present invention installs an MS-DOS
Device Driver 90 to modify the interrupt interface for the MS-DOS Systern Service calls 15 and the idle loop interrupt 45. R. Duncan, supra., discussas the details of implementing device drivers. In par~icular, the device driver's "
initialization routine checks the BIOS version, stores the original vector ' addresses for ths system service interrupt 22 and idle loop interrupt 24 in ~' shared data 80, and modifies the vector addresses 22,24 to point to the limiter 60 and sleeper 70 prograrns. By using the device driver approach, the present invention realizes a reduced memory requirement because MS- ' DOS reclaims the rnemory used for the first-time initialization instructions.
The present invention is installed as a character device driver, with the initialization routine coded at the end of the driver. The initialization routine relays its start address to MS~DOS as the first usable memory address.
Therefore, MS-DOS is free to reuse the memory occupied by the 'initialization routine.
An application program 10 calls MS-DOS System Services 35 using the system sorvice interrupt 15. The present invention modifies the interrupt interface 20 to include a limiter interrupt handler program 60. Likewise, the instant invention supplies a sleeper interrupt handler program 70 for the idle loop interrupt 45. The limiter program 60 communicates with the sleeper program 70 via shared data 80.
Fig. 3 shows the flowchart of the sleeper program 70J which contains; -the a~ctual power saving instructions. Upon entry, the sleeper program 70 ' ~ ~ :
CheCkS 71 the flag in shared memory 80. If the flag is set then the limiter program 60 is restricting the functioning of the sleeper program 70 and tha sleeper program 70 does not implement the power saving features. Instead, the sleeper program exits 78 by transferring control to the original idle loop ' interrupt handler 50 based on the original vector address. On the other hand, d the flag in shared memory ~0 is not set then the limiter program 60 ~- :
sizecl. The central procassing unit (CPU) is an Intel model 80386SX
rnicroprocessor, normally operating at 16 MHz. The system is operated under Microsoft DOS (MS-DOS).
Fig. 1 dopicts the normal operation of MS-DOS. The Intel farnily of processors support up to 256 interrupts, number3d 0 ~hrough 255. During initialization, the boot strap program ~reates a table 20 indexed by interrupt number for containing each interrupt's vector transfer address. The boot ;~
strap program, MS-DOS 30 and application programs 10 load th~ vectors for ~;
defined interrupts 22,24 into the table 20. The processor services interrupts - -~
by transferring control to the interrupt's vector address 22,24 which the processor looks up in the table 20. At the vector address is a program called an interrupt handler. Users, however, can causa a new interrupt handler to execute when the processor services a particular interrupt.
Although there are several methods for irnplementing interrupt handlers, MS-DOS provides standardized mechanisms. See e.~., R. Duncan, Advanced MS-DOS, pps. 207-257 (Microsoft Press 1986).
Application programs 10 communicate with MS-DOS 30 usiny software interrupts. When an application 10 requests a system service, it issues the system service interrupt 15. The processor reads the vector address 22 for the system service interrupt 15 from the vector table 20 and transfers control to the MS-DOS System Service 35. In the preferred embodiment, the system service interrupt 15 is interrupt number 33 (21 hex).
A code in the AH register identifies the particular system se~ice function 37 requested by the application program 10.
The system service function 37 may need to wait for an event. If that is the case, the ~unction 37 enters an idle loop 40. The processor continuously executes the instructions in the idle loop 40 until the awaited -event occurs. When the event occurs, control returns to the function 37, which then returns control to the application 10. One instruction in the idle loop 40 is an instruction to issue an idle loop interrupt 45. In the preferred embodiment, the idle loop interrupt 45 is interrupt number 40 (28 hox).
Upon receiving the idle loop interrupt instruction 45, the processor ' ~ . ;~-,,;
wog3/n6s4s ~ 6~ ` Pcr/us9~/o44os transfers control to the idle loop interrupt handler ~û based on the vector address 24. The idle loop interrupt handler 50 sxecutes its software instructions and returns control to the idle loop 40.
As depicted in Fig. 2, the present invention installs an MS-DOS
Device Driver 90 to modify the interrupt interface for the MS-DOS Systern Service calls 15 and the idle loop interrupt 45. R. Duncan, supra., discussas the details of implementing device drivers. In par~icular, the device driver's "
initialization routine checks the BIOS version, stores the original vector ' addresses for ths system service interrupt 22 and idle loop interrupt 24 in ~' shared data 80, and modifies the vector addresses 22,24 to point to the limiter 60 and sleeper 70 prograrns. By using the device driver approach, the present invention realizes a reduced memory requirement because MS- ' DOS reclaims the rnemory used for the first-time initialization instructions.
The present invention is installed as a character device driver, with the initialization routine coded at the end of the driver. The initialization routine relays its start address to MS~DOS as the first usable memory address.
Therefore, MS-DOS is free to reuse the memory occupied by the 'initialization routine.
An application program 10 calls MS-DOS System Services 35 using the system sorvice interrupt 15. The present invention modifies the interrupt interface 20 to include a limiter interrupt handler program 60. Likewise, the instant invention supplies a sleeper interrupt handler program 70 for the idle loop interrupt 45. The limiter program 60 communicates with the sleeper program 70 via shared data 80.
Fig. 3 shows the flowchart of the sleeper program 70J which contains; -the a~ctual power saving instructions. Upon entry, the sleeper program 70 ' ~ ~ :
CheCkS 71 the flag in shared memory 80. If the flag is set then the limiter program 60 is restricting the functioning of the sleeper program 70 and tha sleeper program 70 does not implement the power saving features. Instead, the sleeper program exits 78 by transferring control to the original idle loop ' interrupt handler 50 based on the original vector address. On the other hand, d the flag in shared memory ~0 is not set then the limiter program 60 ~- :
4~ PCl~/US92/04405 21116~
is not restricting the functioning of the sleeper program 70 and the sleeper program 70 implements the power saving f~atures.
In the preferred embodiment, the system clock frequency is ~-~- ; f decreased to its min3mum value. Barrett et al., in U.S. Patent Serial Number 611,990, herein incorporated by raference, discloses the method for -reducing the clock frequency. In addition, the preferred embodiment requires there be no floppy disk accesses in progress. Reducing the systern clock speed while a floppy disk access is in progress results in a Direct Memory Access (DMA) failure. To prevent a DMA failure, the sleeper program 70 checks 72 a flag maintained by the ROM Basic InpuVOutput System (BIC)S) to see if a floppy disk access is in progress and, if notj the sleeper proç~ram 70 reduces 73 the clock speed. Otherwise, th~ sleeper program 70 does not reduce the clock speed. In either case, however, the next step is to enable interrupts 74 so the suspended processor detects extemai interrupts. The sleeper program 70 next issues a halt instruction 75, which suspends processor activity. The processor stays suspended until the processor detects an extemal interrupt.
Halting the processor results in two power saving benefits. First, the halt reduces the amount of transistor switching within the procesæor itself.
Therefore, the processor requires less power to operate. Second, system bus activity stops. I~ the preferred embodiment, the portable computer uses ~ ~ i pseudo-static memory. Pseudo-static memory chips enter a low-power, self-refresh mode while not acc~ssed, and, once accessed, return to full-power mode. Hereth et al., in U.S. Patent Number 4,710,903, her~in incorporatsd ~ -by reference, discuss the operation of pseudo-static memories in detail. ;
Because there is no bus activity, there are no memory accesses occurring.
Because there are no memory accesses occurring, the pseudo-static ~ -memory automatically goes into the low-power, self-refresh mode. ~ -Therefore, memory decreases its power demands as a direct result of the halt instruction 75. These power saving fea~ures continue until an external interrupt occurs. ;
The external interrupt results from a user keyslroke, cursor movement . ~
WO g3/0654~; PCI'/USg2/04405 6~ 6 provid~d by a mouse, electromagnetic stylus or light pen device, or another hardware event. Th~ most common hardware event ~o occur and, thus, wake the processor is the pariodic system timar, which triggers an sxternal -interrupt every ~5 milliseconds. Thus, the computer does not remain in the -suspended state indefinitsly.
A hardware mechanism services 76 the external interrupt. The resulting memory accesses cause the pseudo-static memory to power up.
In the preferred embodiment, a hardware mechanism automatically increases the system clock frequency during processing of the ex~amal interrupt. After servicing the intarrupt, control retums to the sleeper program 70 at the instruction after the halt instruction. The sleeper program 70 corrects registers 77 reflecting the system speed. The sleeper program 70 then exits 78 by transferring control to the original idle loop interrupt handler ~0 based on the original vector address.
Fig. 4 shows the flowchart of the limiter program 60. Upon entry, the Atl register ~ontains the system service function code identifying the particular system service function 37 called by the application 10. Halting the processor during the idle loop 40 degrades several identified system -service functions. To reduce visible degradation, the limiter program 60 compares 61 the code in the AH register with the codes corresponding to the identilied functions. The identified functions arethe CharacterOutput (code 2), Auxiliary Output (code 4), Printer C)utput (code 5), Direct Console InpuVOutput tcode 6), Output Character String (code 9), and Get Input Status (code 11 ) functions. If the code in the AH register does not correspond to any identHied function, then the limiter program exits by !
transfernng control 62 to the system service interrupt handler 35 based on the original vector address. As a result of the exit, the system servise 35 -returns directly to the application 10 upon completing the requested function.
On the other hand, if the AH register contains an identified function code then the limiter program 60 signals the sleeper program 70 by setting 63 a flag located in shared memory 80. Next, the limiter program 60 calls 64 the original system service 3~ using the original interrupt vector. As a
is not restricting the functioning of the sleeper program 70 and the sleeper program 70 implements the power saving f~atures.
In the preferred embodiment, the system clock frequency is ~-~- ; f decreased to its min3mum value. Barrett et al., in U.S. Patent Serial Number 611,990, herein incorporated by raference, discloses the method for -reducing the clock frequency. In addition, the preferred embodiment requires there be no floppy disk accesses in progress. Reducing the systern clock speed while a floppy disk access is in progress results in a Direct Memory Access (DMA) failure. To prevent a DMA failure, the sleeper program 70 checks 72 a flag maintained by the ROM Basic InpuVOutput System (BIC)S) to see if a floppy disk access is in progress and, if notj the sleeper proç~ram 70 reduces 73 the clock speed. Otherwise, th~ sleeper program 70 does not reduce the clock speed. In either case, however, the next step is to enable interrupts 74 so the suspended processor detects extemai interrupts. The sleeper program 70 next issues a halt instruction 75, which suspends processor activity. The processor stays suspended until the processor detects an extemal interrupt.
Halting the processor results in two power saving benefits. First, the halt reduces the amount of transistor switching within the procesæor itself.
Therefore, the processor requires less power to operate. Second, system bus activity stops. I~ the preferred embodiment, the portable computer uses ~ ~ i pseudo-static memory. Pseudo-static memory chips enter a low-power, self-refresh mode while not acc~ssed, and, once accessed, return to full-power mode. Hereth et al., in U.S. Patent Number 4,710,903, her~in incorporatsd ~ -by reference, discuss the operation of pseudo-static memories in detail. ;
Because there is no bus activity, there are no memory accesses occurring.
Because there are no memory accesses occurring, the pseudo-static ~ -memory automatically goes into the low-power, self-refresh mode. ~ -Therefore, memory decreases its power demands as a direct result of the halt instruction 75. These power saving fea~ures continue until an external interrupt occurs. ;
The external interrupt results from a user keyslroke, cursor movement . ~
WO g3/0654~; PCI'/USg2/04405 6~ 6 provid~d by a mouse, electromagnetic stylus or light pen device, or another hardware event. Th~ most common hardware event ~o occur and, thus, wake the processor is the pariodic system timar, which triggers an sxternal -interrupt every ~5 milliseconds. Thus, the computer does not remain in the -suspended state indefinitsly.
A hardware mechanism services 76 the external interrupt. The resulting memory accesses cause the pseudo-static memory to power up.
In the preferred embodiment, a hardware mechanism automatically increases the system clock frequency during processing of the ex~amal interrupt. After servicing the intarrupt, control retums to the sleeper program 70 at the instruction after the halt instruction. The sleeper program 70 corrects registers 77 reflecting the system speed. The sleeper program 70 then exits 78 by transferring control to the original idle loop interrupt handler ~0 based on the original vector address.
Fig. 4 shows the flowchart of the limiter program 60. Upon entry, the Atl register ~ontains the system service function code identifying the particular system service function 37 called by the application 10. Halting the processor during the idle loop 40 degrades several identified system -service functions. To reduce visible degradation, the limiter program 60 compares 61 the code in the AH register with the codes corresponding to the identilied functions. The identified functions arethe CharacterOutput (code 2), Auxiliary Output (code 4), Printer C)utput (code 5), Direct Console InpuVOutput tcode 6), Output Character String (code 9), and Get Input Status (code 11 ) functions. If the code in the AH register does not correspond to any identHied function, then the limiter program exits by !
transfernng control 62 to the system service interrupt handler 35 based on the original vector address. As a result of the exit, the system servise 35 -returns directly to the application 10 upon completing the requested function.
On the other hand, if the AH register contains an identified function code then the limiter program 60 signals the sleeper program 70 by setting 63 a flag located in shared memory 80. Next, the limiter program 60 calls 64 the original system service 3~ using the original interrupt vector. As a
5 ^ 2111 68 o ~ P~/US92/04405 7 :
result of the call 64, the system service 35 returns control to the limiter program 60 upon completion of the requested function. After control retums to the limitsr program 60, it pushes 65 the results retumed from ths system service call onto the system stack. The limiter program 60 clears 66 the flag in shared memory 80 and e~tits by returning 67 to the application program 10.
Although this invention has bean particularly shown and described with reference to a preferr~d embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
For example, the applicants implemented the limiter program and sleeper program as device driver interrupt handiars. The applicants recognize the interrupt handlers could also be implemented as MS-DOS
Terminate-and-Stay-Resident programs. In addition, the operating system code could ~e modified to include the limiter and sleeper program instructions in-line. Some functions of ths limiter and sleeper programs also ~ -could bs implemented through hardware devices, instead of entirely through software instructions.
Although the preferred embodiment relies on a particular hardware arrangement, the invsntion could be used on any MS-DOS computer with only rninor modifications. For exarnp!e, another computer's DMA
implementation rnight not be affected by a reduction in clock speed. In that ~;
case, there wouid be no need for the sleeper pr~gram to check for floppy . .~ .:
disk accesses. Another computer may have additional devices with a ; ~-s~ftware selectable power-saving mode. Software instructions to place -these devices into low-power mode could be added to the sleeper program.
Furthermore, the invention ix not limited to computers using pseudo-static memory. Any computer memory with a low-power mode will benefit from the ~ -lack of memory accesses. In any case, any portable computers will ~enefit from halting the processor while it is idle. ~ ~
- ~ '. ":
result of the call 64, the system service 35 returns control to the limiter program 60 upon completion of the requested function. After control retums to the limitsr program 60, it pushes 65 the results retumed from ths system service call onto the system stack. The limiter program 60 clears 66 the flag in shared memory 80 and e~tits by returning 67 to the application program 10.
Although this invention has bean particularly shown and described with reference to a preferr~d embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
For example, the applicants implemented the limiter program and sleeper program as device driver interrupt handiars. The applicants recognize the interrupt handlers could also be implemented as MS-DOS
Terminate-and-Stay-Resident programs. In addition, the operating system code could ~e modified to include the limiter and sleeper program instructions in-line. Some functions of ths limiter and sleeper programs also ~ -could bs implemented through hardware devices, instead of entirely through software instructions.
Although the preferred embodiment relies on a particular hardware arrangement, the invsntion could be used on any MS-DOS computer with only rninor modifications. For exarnp!e, another computer's DMA
implementation rnight not be affected by a reduction in clock speed. In that ~;
case, there wouid be no need for the sleeper pr~gram to check for floppy . .~ .:
disk accesses. Another computer may have additional devices with a ; ~-s~ftware selectable power-saving mode. Software instructions to place -these devices into low-power mode could be added to the sleeper program.
Furthermore, the invention ix not limited to computers using pseudo-static memory. Any computer memory with a low-power mode will benefit from the ~ -lack of memory accesses. In any case, any portable computers will ~enefit from halting the processor while it is idle. ~ ~
- ~ '. ":
Claims (16)
1. A data processing system including a processor and having software instructions stored in memory for processing by the processor at a clock frequency, the software instructions including at least one application program, a plurality of system service functions, and an idle sequence, the processor and software instructions further comprising:
a limiter coupled between the programs and the system service functions to identify processing of predetermined system service functions by the processor, the predetermined system service function being subject to a substantial degradation upon halting the processor;
an idle state detector to automatically detect processing of the idle sequence; and a sleeper coupled to the limiter and the idle state detector to halt the processor upon the detection of the idle sequence by the idle state detector when the limiter has not identified processing of a predetermined system service function.
a limiter coupled between the programs and the system service functions to identify processing of predetermined system service functions by the processor, the predetermined system service function being subject to a substantial degradation upon halting the processor;
an idle state detector to automatically detect processing of the idle sequence; and a sleeper coupled to the limiter and the idle state detector to halt the processor upon the detection of the idle sequence by the idle state detector when the limiter has not identified processing of a predetermined system service function.
2. The data processing system of Claim 1 further comprising a shared memory area coupled between the limiter and the sleeper, wherein the limiter sets data in the shared memory area to indicate that a predetermined system service is being processed by the processor and the sleeper reads data from the shared memory area.
3. The data processing system of Claim 2 wherein the idle state detector is an interrupt vector adapted to instructor processing by the sleeper in response to the predetermined idle loop interrupt.
4. The data processing system of Claim 3 wherein the sleeper is an interrupt handler.
?. The data processing system of Claim 1 wherein the sleeper further comprises software instructions to decrease the clock frequency.
6. The data processing system of Claim 1 wherein the memory has a power-saving mode entered when no memory accesses are occurring.
7. The data processing system of Claim 6 wherein the memory is pseudo-static memory.
8. The data processing system of Claim 1 wherein the limiter is an interrupt handler responsive to calls to system service functions.
9. The data processing system of Claim 1 wherein the processor continues normal operation upon receipt of any interrupt subsequent to the halting of the processor.
10. The data processing system of Claim 9 wherein the sleeper returns control to the idle sequence upon continuing normal operation.
11. The data processing system of Claim 1 wherein the idle sequence generates a predetermined idle loop interrupt.
12. A method of conserving power usage on a data processing system including a processor and having software instructions stored in memory for processing by the processor at a clock frequency, the software instructions including at least one application program, a plurality of system service functions, and an idle sequence, the method comprising the steps of:
identifying processing of predetermined system service functions that are subject to a substantial degradation upon halting the processor;
automatically detecting processing of the idle sequence; and halting the processor upon detection of the idle sequence except when a predetermined system service function has been identified.
identifying processing of predetermined system service functions that are subject to a substantial degradation upon halting the processor;
automatically detecting processing of the idle sequence; and halting the processor upon detection of the idle sequence except when a predetermined system service function has been identified.
13. The method of Claim 12 wherein the step of detecting is the response to a predetermined idle loop interrupt generated by the idle sequence.
14. The method of Claim 13 wherein the step of halting is in response to the predetermined idle loop interrupt.
15. The method of Claim 12 wherein the step of identifying is in response to calls to system service functions.
16. The method of Claim 12 further comprising the step of decreasing the clock frequency.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US75902491A | 1991-09-13 | 1991-09-13 | |
| US759,024 | 1991-09-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2111680A1 true CA2111680A1 (en) | 1993-04-01 |
Family
ID=25054097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2111680 Abandoned CA2111680A1 (en) | 1991-09-13 | 1992-05-26 | Power savings with ms-dos idle loop |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0603185A1 (en) |
| JP (1) | JPH06510616A (en) |
| AU (1) | AU665354B2 (en) |
| CA (1) | CA2111680A1 (en) |
| WO (1) | WO1993006545A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0654726B1 (en) * | 1993-11-23 | 1998-12-16 | Advanced Micro Devices, Inc. | Computer power management systems |
| DE69516199T2 (en) * | 1994-02-23 | 2000-09-21 | Sun Microsystems Inc | Method and arrangement for power saving in a computer system using a power control pseudo device driver |
| JPH08241145A (en) * | 1995-03-02 | 1996-09-17 | Nec Corp | Power consumption reduction system of data processor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE479887T1 (en) * | 1989-06-30 | 1992-12-17 | Poqet Computer Corp., Santa Clara, Calif., Us | POWER SUPPLY MANAGEMENT SYSTEM FOR COMPUTERS. |
| US5218704A (en) * | 1989-10-30 | 1993-06-08 | Texas Instruments | Real-time power conservation for portable computers |
-
1992
- 1992-05-26 EP EP92912580A patent/EP0603185A1/en not_active Withdrawn
- 1992-05-26 CA CA 2111680 patent/CA2111680A1/en not_active Abandoned
- 1992-05-26 AU AU21455/92A patent/AU665354B2/en not_active Ceased
- 1992-05-26 WO PCT/US1992/004405 patent/WO1993006545A1/en not_active Application Discontinuation
- 1992-05-26 JP JP5505544A patent/JPH06510616A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| AU665354B2 (en) | 1996-01-04 |
| EP0603185A1 (en) | 1994-06-29 |
| WO1993006545A1 (en) | 1993-04-01 |
| JPH06510616A (en) | 1994-11-24 |
| AU2145592A (en) | 1993-04-27 |
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