CA2110632A1

CA2110632A1 - Overvoltage protection circuit

Info

Publication number: CA2110632A1
Application number: CA002110632A
Authority: CA
Inventors: Robert Pezzani; Angelo Ugge
Original assignee: Individual
Current assignee: STMicroelectronics SA; STMicroelectronics lnc USA
Priority date: 1992-12-04
Filing date: 1993-12-03
Publication date: 1994-06-05
Also published as: FR2699015A1; US6252256B1; DE69325241T2; EP0600810A1; JPH0738063A; EP0600810B1; FR2699015B1; DE69325241D1

Abstract

ABSTRACT OF THE DISCLOSURE

A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment.
Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.

Description

~ 2110632 2 1. Field of the Invontion:

3 The present invention relates generally to protective 4 circuits for electronic devices, and more specifically to S overvoltage protection circuits suitable for use in 6 protecting devices attached to telephone lines.

7 2. De~¢ription of the Prior Art:

8 In order to prevent damage from electrical 9 overvoltages, devices attached to electrical lines such as telephone lines are protected by overvoltage protection 11 circuitry designed to accomplish this task. Such 12 overvoltages can be caused by, for example, lightning 13 strikes somewhere in the system, or power surges caused by 14 accidental cross connection with power lines. The overvoltage protection circuitry should protect the primary 16 devices, and reset to allow normal operation after the 17 overvoltage condition has passed.

18 In the past, numerous different circuit designs have 19 been used to provide protection. Typically, such designs utilize 2 or three discrete semiconductor devices packaged 21 into a single component package. These devices can provide 22 good protection, but the use of more than one semiconductor 23 die in a package results in a relatively expensive 24 protection circuit.

Overvoltage protection circuitry intended for use with 26 telephone equipment must take into account the particular 27 hazards which are encountered when devices are connected to 28 the telephone system. Two incoming signal lines, called 29 "tip~ and "ring" for hi~torical reasons, carry the normal telephone ~ignal. Overvoltage~ can occur between these two 31 line~. More commonly, overvoltages can occur between one 32 or both of the~e lines and ground. In normal operation, ~m~DK~ ~.~ Page 2 :-`` 2110632 1 the voltage on the tip and ring lines float with respect to 2 ground, although one line is typically at approximately -2 3 volts, and the other at approximately -50 volts. A 48 volt 4 differential between the two lines is expected in normal operation.

6 In order to provide the most complete protection, 7 overvoltage potentials must be protected against between 8 the tip and ring lines as well as between these lines and 9 ground. Thus, in most applications a three-way balanced protective circuit is preferred, although two-way balanced 11 circuits are useful and common as known in the art.
12 Examples of devices which have been utilized in the past to 13 provide the required protection can be found in US Patent 14 Number 4,282,555, titled OVE~VOLTAGE PROTECTION MEANS FOR
PROTECTING LOW POWER SEMICONDUCTOR COMPONENTS, and US
16 Patent Number 4,905,119, titled SOLID STATE OVERVOLTAGE
17 PROTECTION CIRCUIT.

18 Although the circuits described in these patents can 19 provide adequate protection for devices attached to telephone lines, they are difficult to produce 21 inexpensively in a monolithic integrated circuit. The 22 circuit in Patent Number 4,905,119 utilizes more than one 23 chip, which increases cost of the overall circuit. The 24 device de~cribed in the 4,282,555 patent can be implemented on a single chip, but P-type diffusions through the depth 26 of the device must be used for isolation. This process 27 add~ greatly to the cost of the device.

28 An ob~ect of the invention i5 to provide a design for 29 an overvoltage protection circuit which can be easily and inexpen~ively integrated into a single monolithic device.

31 Another ob~ect o~ the invention i5 to provide such a 32 circuit that i8 suitably turned off after an overvoltage in 33 use of a connection with a telephone line.

~ DK~ ~ ~ Page 3 ~` 2110~32 1 Another object of the invention is to provide such a 2 circuit that is triggered not only further to an 3 overvoltage, but also further to an overcurrent.

4 Another object of the invention is to provide such a S design which i8 flexible enough to be easily changed to 6 provide several different protection techniques.
7 Another object of the invention is to provide such a 8 design to incorporating packaging designs which are 9 flexible and easily adapted to a number of different mounting and thermal dissipation requirements.

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-~` 211()632 2 Therefore, in accordance with the present invention, 3 a design for an overvoltage protection circuit can be used 4 to fabricate several different circuits incorporating different protection techniques. The design is suitable 6 for use in a single device, which can be easily and 7 inexpensively packaged and protected from the environment.
8 Three terminal protection circuits can have three terminals 9 on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular 11 design. Additional circuitry can be included to sense for 12 high current conditions which are caused by overvoltages 13 too low to trigger the normal overvoltage protection 14 circuits.

~m~Dx~t~ ~ Page 5 , ;~,, . .. . . ".; .; ~, ~` 2110~32 BRIEF D~8C~IPTION OF TNB D~AWING8 2 The novel features believed characteristic of the 3 invention are set forth in the appended claims. The 4 invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best 6 be understood by reference to the following detailed 7 description of an illustrative embodiment when read in 8 conjunction with the accompanying drawings, wherein:

g Figures lA, lB, and lC contain several schematic diagrams of overvoltage protection circuits;

11 Figures 2A, 2B contain top and bottom plan views of a 12 devise constructed in accordance with the present 13 invention;

14 Figure 3 contains section views of the device of Figure 2A;

16 Figure 4 is an upper plan view of an alternative :
17 device constructed in accordance with the present :~
18 invention;

19 Figure 5 is a section of the device of Figure 4; ~
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Figure 6 contains two schematic diagrams of additional 21 preferred embodiments of the present invention;

22 Figures 7A and 7B are upper and lower plan views of a ~:
23 device according to figures 2 and 3 incorporating the 24 features of figures 6A and 6B;

Figure 8 is a section view of the device of Figure 7;

~bmqDx~ ~.~i~ Page 6 211~32 1 Figure 9 is an upper plan view of a device constructed 2 in accordance with Figures 4 and 5 incorporating the 3 features of Figures 6A and 6B

4 Figure 10 is a section view of the device of Figure 9;

Figures 11 and 12 illustrate packaging techniques for 6 overvoltage protection devices in accordance with the 7 present invention; and 8 Figure 13 illustrates two alternative embodiments of 9 packaging techniques in accordance with the present invention.

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21106~2 1 DE8CRIPTION OF THE PREFERRED ~M~ODIMENT

2 The structures described below do not include a 3 process flow for manufacturing integrated circuits. The 4 present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in 6 the art. The figures representing cross-sections of 7 portions of an integrated circuit during fabrication are 8 not drawn to scale, but instead are drawn so as to 9 illustrate the important features of the invention.

The devices described below are directed to 11 overvoltage protection circuitry suitable for use with 12 equipment which interfaces to a standard telephone line.
13 However, it will be appreciated by those skilled in the art 14 that the devices and techniques described herein may be utilized, with modification in some cases, to interface 16 electronic equipment with other types of electrical lines.

17 Referring to Figure 1, three alternative circuits are 18 shown for protecting electronic equipment from overvoltages 19 on a telephone line. Referring to Figure lA, an overvoltage protection circuit 10 is connected to the 21 incoming tip (T) and ring (R) lines 12, 14, respectively.
22 Two surge protectors 16, 18 are connected to the tip and 23 ring lines, respectively, and to a common node 20. A third 24 surge protector 22 is connected between the common node 20 and ground.
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26 As known in the art, the series combination of 27 protectors 16, 18 turn on to short the tip and ring lines 28 12, 14 when a large voltage differential appears between 29 these lines. If a large voltage potential occurs between the tip and ring lines and ground, all three surge 31 protectors 16, 18, 22 begin conducting and channel current 32 to ground. Additionally, each of the devices 16, 18, 22 33 has to cease conducting when the overvoltage ceases.

~om~ Dx~ No. ~ Page 8 x . .,,. . , . . ~ -, , ~ 211~632 1 Each of the surge protectors 16, 18, 22 triggers at a 2 voltage which is 1/2 the desired protection voltage. For 3 example, if it is desired to trigger the protective 4 circuitry for a surge of 500 volts or more, each of the surge protectors 16, 18, 22 will trigger at 250 volts.
6 Thus, if a 500 volt differential appears between the tip 7 and ring lines, surge protectors 16 and 18 will begin 8 conduction. If a 500 or greater potential appears between 9 either the tip or ring line and ground, the appropriate surge protector 16, 18 will be triggered, as well as surge 11 protector 22.

12 As known in the art, one of the most common causes of 13 high voltage spikes is lightening strikes. Such surges 14 typically cause a large voltage differential between both the tip and ring lines and ground. In such instances, all 16 three of the surge protectors 16, 18, 22 will conduct 17 ~imultaneously. Since the voltage differential between the 18 tip and ring lines is low compared to the overvoltage 19 contained in the spike, the current conducted by the surge protectors 16, 18 is approximately equal. This requires 21 surge protector 22 to conduct twice the current to ground 22 which must be handled by ~urge protectors 16, 18. In 23 Figure lA, this is indicated by the larger block used for 24 surge protector 22.

Figure lB illustrates an alternative overvoltage 26 protection circuit 24 used with the same tip and ring line 27 12, 14. This circuit 24 is arranged in a delta connection, 28 as opposed to the star connection of Figure lA.
29 Overvoltage protection circuit 24 contains three surge protectors 26, 28, 30. In the delta configuration, each of 31 the surge protectors 26-30 is designed to trigger at the 32 de~lred protection voltage, as opposed to 1/2 the desired 33 voltage as described in connection with Figure lA. Each 34 leg o~ the delta arrangement is capable of aonducting the same current, although, as described above, the most common ~bn~d~ ~ ~ Page g --` 2110632 1 high current situations are a high overvoltage on both the 2 tip and ring lines compared to ground. In such a case, 3 both of the surge protectors 28, 30 will conduct 4 approximately the same current to ground.

Figure lC illustrates a third overvoltage protection 6 eircuit 32, which is unbalanced compared with the two 7 eireuits previously described. Surge protectors 34, 36 are 8 both eonneeted directly to ground. This eircuit provides 9 adequate protection against common mode overvoltages, such as those eaused by lightening strikes, but requires an 11 overvoltage twice as large to trigger conduction between 12 the tip and ring lines 12, 14. However, the circuit of 13 Figure lC has many uses where the primary mode of 14 protection is expected to be overvoltages to ground, as opposed to those between the tip and ring lines.

16 Figures 2A and 2B illustrate, respectively, top and 17 bottom views of a monolithie semieonduetor deviee suitable 18 for use as an overvoltage proteetion circuit. The 19 embodiment shown in Figure 2 implements the overvoltage proteetion eireuit 24 illustrated in Figure lB. Each surge 21 proteetor shown in Figure lB is a bilateral PNPN switeh.
22 Re~erring to Figure 2A, the proteetion deviee includes two 23 P-well regions 38, 40. P-well regions 38, 40 are 24 fabrieated on the upper ~ide of a substrate. The upper ~urfaee of the substrate is eovered by an oxide region 42 26 over the periphery of the P-wells and between the P-wells.
27 Within eaeh P-well region 38, 40 is a highly doped N+
28 region 44, 46. A metal eontaet 48 overlies P-well region 29 40 and N+ region 46. A similar metal eontaet is formed over P-well region 38 and N+ region 44, but is removed from 31 Figure 2A for purposes of illustration.

32 The N+ regions 44, 46 are patterned so that they are 33 not eontinuous. Cireular regions 50 of the underlying P-34 well 38 show through the N+ region 44 as shown. These ar¢
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~m~Do~ ~.~ Page 10 -' 2110632 1 regions which are blocked from implant of the N+ dopant 2 using masking techniques as known in the art.

3 Referring to Figure 2B, a P-well region 52 occupies 4 substantially the entire undersurface of the device, and its peripheral upper surface is covered by an oxide region 6 54. An N+ region 56 is formed covering approximately 1/2 7 of the P-well 52, and contains circular regions 58 which 8 show through to the underlying P-well region 52. The 9 projection of the N+ region 56 is substantially complementary with respect to the N+ regions 44 and 46 of 11 upper surface of the device. A metal contact 60 covers 12 substantially the entire P-well region 52, and is shown 13 broken away in order to expose the silicon surface for the 14 left-hand side of the device.

Figure 3A is a section of the device of Figure 2A
16 taken along the section line A-A. The P-well and N+
17 regions are numbered according to Figure 2A. It can be 18 seen that the P-wells 40, 52 are formed in an N-substrate 19 62. The peripheral upper surfaces of the P-well regions are passivated at the upper or lower surface of the device 21 by the oxide regions 42, 54.

22 A bidirectional PNPN switch is apparent from the 23 section view of F$gure 3A. It comprises a first and a 24 second PNPN switch. The first PNPN switch includes the P-well 40, N-substrate 62, P-well 52, and N+ region 56. The 26 second, parallel, PNPN switch is formed by the P-well 52, 27 N-substrate 62, P-well 40, and N+ region 46.

28 Figure 3B is a section of the device of Figure 2A
29 taken along the line B-B. Figure 3B includes metal contact 64 which wa~ removed from Figure 2A for ease of 31 illustration.

~bm~Cx~ ~ ~ Page 11 2:~10632 1 In addition to the bilateral vertical PNPN switches 2 described in connection with 3A, a bilateral horizontal 3 PNPN switch is formed between contact 64 and contact 48.
4 This bidirectional horizontal switch comprises a first switch consisting of P-well 38, N-substrate 62, P-well 40, 6 and N+ region 46 and a second switch consisting of P-well 7 40, N-substrate 62, P-well 38, and N+ region 44.

8 Thus, when a sufficient voltage differential occurs ~-9 between the tip and ring lines, current flows between contact 64 and contact 48. When an overvoltage occurs 11 between both the tip and ring lines and ground, current 12 flows vertically through the device from contacts 64 and 48 13 to contact 60, which is connected to ground. The large 14 area of the ground contact 60 ensures that overheating due to current flow will not occur when such large currents 16 flow to ground. Since the currents between tip and ring 17 overvoltages tend to be significantly less, the lesser 18 current handling capacity of the device between contacts 64 19 and 48 i~ sufficient.
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According to an aspect of the invention, the bilateral 21 PNPN switches which flow vertically through the device to 22 the ground contact 60 are not symmetrical. This is because 23 a larger number of regions 50 show through the N+ regions 24 44 and 46 to the underlying P-wells 36, 38. A lesser number of P-well show through regions 58 are formed on the 26 back side of the device. The larger number of openings 50 27 for the top side contacts increases the holding current 28 required to maintain these devices on in the forward 29 direction. The smaller number of openings on the back side, ground, contact defines a smaller holding current, 31 but provides higher surge capacity. In a preferred 32 embodiment, the ratio of number of opening~ is greater than 33 approximately three-to-one. The ratios can be selected as 34 de~ired to obtaln appropriate ratios for holding current in the two directions.
-~on~Dx~ ~ ~ Page 12 2~0~32 1 As is known to those skilled in the art, the2 protective switches triggered by a positive surge on the 3 tip and/or ring lines (current flowing from line to ground) 4 will switch off by reverse polarity after the disturbance ceases. This reverse polarity is applied by the negative 6 steady bias of the tip and ring lines with respect to 7 ground. However, in the reverse direction, with current 8 flowing from ground towards the tip and ring lines, a 9 larger value for holding current is required. This larger value is required to ensure that the protective device 11 switches off despite the reverse bias of each line with 12 respect to ground. This is to insure that the protective 13 devices switch off to allow normal operation of the line 14 after a voltage surge. Thus, with the asymmetrical switches shown in Figures 2 and 3, the device recovers 16 properly regardless of the direction of the surge.

17 Figure 4 illustrates a protective device which 18 implements the star circuit of Figure lA. In this device, 19 all three contacts are made on the upper surface o~ a device. An oxide region 66 surrounds the device and 21 divide~ it into three regions. Each of these regions 22 contains a P-well 68, 70, 72. P-well 68 contains an N+
23 region 74, P-well region 70 contains an N+ region 76, and 24 P-well region 72 contains an N+ region 78. The various P-wells show through their respective N+ regions through 26 circular regions 80. Metal contacts 82 and 84 27 ~ubstantially cover their respective P-well regions. As 28 was the case with Figure 2A, the metal contact over P-well 29 region 68 has been removed, and metal contact 84 has been broken for clarity of illustration.

31 It will be appreciated that the various regions of the 32 device of Figure 4 are virtually identical to their 33 counterpart regions shown in Figure 2A and 2B. In fact, by 34 rearranging the masks used to form the device, the same ~b~Dxk~ ~ Page 13 `` 2~10632 1 device structures can be formed in the device of Figure 4 2 as were used in the device of Figure 2A.

3 Figure S is a section view of the device of Figure 4 4 taken along section line A-A. The device is formed in an S N-substrate 86. P-regions 88 and N+ regions 90 are formed 6 on the back side of the substrate 86, and connected by a 7 back side conductive region 92 on the back surface of the 8 substrate 86. Conductive region 92 may be formed as a 9 metallic contact on the back side of the device, but represents the common node 20 of the star configuration of 11 Figure lA. Thus, the conductive region 92 is not normally 12 bonded to a contact external of the device package. The 13 conductive region 92 can be mounted on a heat sink to 14 dissipate heat generated by the device.

The device shown in Figures 4 and 5 operates in a 16 manner very similar to that shown in Figures 2 and 3. The 17 difference is that current flowing between the tip and ring 18 connections and the ground connection flow vertically to 19 the back side of the device, across the conductive contact region, 92 and vertically up to the other contact. Some 21 lateral current flow will also naturally occur. The 22 primary mode of conduction is through the vertical PNPN
23 ~witches.

24 The layout of Figure 4 provides for a ground contact which ha~ twice the surface area of the tip and ring 26 contact~. This provides for twice the current carrying 27 capacity to the ground contact, which is often required as 28 described above. The placement of the tip and ring 29 contacts adjacent to each other allows for good conductive properties between these two terminals. The tip and ring 31 contact~ are symmetrical with respect to the ground 32 contact, 80 that the properties of both of the bilateral 33 PNPN switches are the same.

~bn~Dx~ ~ ~ Page 14 -` 21~0~32 ¦ i The circuits described above provide protection 2 against short, high voltage/high current surges such as 3 lightening strikes. Another type of surge which can occur 4 generates a lower voltage and current, but typically lasts for a longer period of time. This type of problem can be 6 exemplified by a surge which occurs when a sixty cycle 7 power line connects with either the tip or ring line.
8 Although the voltage and current which are generated are 9 lower, such a continuous connection can actually transfer more power than a lightening strike into the equipment 11 connected to the line.

12 The voltage impressed on the line by such a fault may 13 not be high enough to trigger the PNPN switches of the 14 previously described devices. In order to protect against this lower voltage problem, additional circuitry can be 16 added to the devices previously described.

17 Figures 6A and 6B illustrate two alternative circuits 18 which can be connected to the tip and ring lines in 19 addition to the previously described protective circuits.

Figure 6A illustrates a first embodiment of a surge 21 protect circuit 94. Tip line 12 is connected to Tl line 96 22 through resistors 98, 100. Similarly, ring line 14 is 23 connected to line Rl 102 through resistors 104, 106. The 24 Tl and Rl terminals 96, 102 are connected to the tip and ring inputs of the equipment being protected.

26 A common node 108 between resistors 98 and 100 is 27 connected to the control gate of thyristor devices 110, 28 112. The anodes of thyristors 110, 112 are connected to a 29 co~mon node 114, which ie grounded. In a similar manner, a common node 116 between resi~tor~ 104, 106 is connected 31 to the control gates of thyristor devices 118, 120.

~bn~Dx~ ~.~ Page 15 211~32 1 In operation, a voltage drop across the appropriate 2 resistor 98, 100, 104, 106 triggers the associated 3 thyristor. Such a voltage drop is caused by current 4 flowing between the tip or ring lines and the Tl and R1 terminals. For example, current flowing to the left along 6 the tip line causes a voltage drop through resistor 100 7 which triggers thyristor 112. Current flowing to the right 8 on the tip line causes a voltage drop across resistor 98 9 which triggers thyristor 110. Current flow in either direction along the ring line similarly triggers thyristor 11 devices 118 or 120.

12 When a thyristor device is triggered by current flow 13 through its controlling resistor, current is shunted to 14 ground. This prevents current from flowing into, or out of, the protected equipment. Once current flow has ceased, 16 or fallen low enough that the voltage drop across the 17 a6sociated resistor no longer generates a sufficient 18 voltage to trigger the thyristor, the thyristor turns off 19 and the protection circuit returns to its normal state.
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Referring to Figure 6B, surge protect circuit 122 21 operates in a manner similar to that described in 22 connection with Figure 6A. Instead of being connected to 23 ground, the anodes of thyristor~ 110, 112 are connected to 24 common node 124, which is in turn connected to the ring line 14. In a similar manner, the anodes of thyristors 26 118, 120 are connected to common node 126, which in turn is 27 connected to tip line 12.
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28 Figure 7A and 7B correspond to the device of Figures 29 2A and 2B, with the inclusion of the circuits of Figures 6A
and 6B. Figure 7A shows a top plan view of the device, and 31 i5 similar to the structure shown in Figure 2A. Additional 32 structures have been ~ormed within the P-wells 38, 40.
33 The~e structuree are N+ regions 128, 130 in P-well 38, and 34 N+ regions 132, 134 in P-well 40.

~yDx~ ~ ~ Page 16 `` 2~10~2 1 As shown in Figure 7A, metal contact 48 is modified so 2 as to contact N+ region 134, and not contact N+ region 132.
3 A separate metal contact 136 makes contact with N+ region 4 132. Metal contact 48 is used to make a connection to the tip or ring line in the phone system, while metal contact 6 136 is used to make contact with the tip or ring line which 7 connects to the equipment being protected. As was the case 8 in Figure 2A, the metal contacts over the P-well 38 have 9 been removed for clarity of description.

Figure 7B illustrates the back side of the device. As 11 shown, the N+ region 56 is narrowed underneath the 12 thyristor devices.

13 Figure 8 is a section view of the device taken through 14 section line A-A of Figure 7A. Figure 8 is similar to Figure 3A with the addition of the thyristor elements 132, 16 134, 136. The thyristor 110 of Figure 6A is located 17 between the metalizations 48 and 60. This thyristor is 18 formed from regions 134, 40, 62, and 52. The thyristor 112 19 of Figure 6A is located between metalizations 136 and 60.
It i8 formed from the regions 132, 40, 62, and 52. These 21 two thyristors have a common gate defined by the layer 40.
22 The resistors shown in Figures 6A and 6B are the current 23 path between metal contact 48, through the P-well 40 24 underneath N+ regions 132, 134, to the metal contact 136.
The P-well region 40 acts as the control gates for the 26 thyristors.

27 By symmetry, the regions 130, 38, 62, and 52 form the 28 thyristor 118 of Figure 6A, and the regions 128, 38, 62, 29 and 52 form the thyristor 120 of Figure 6A. The thyristor 110 shown in Figure 6B is illustrated in Figure 7A between 31 the main two top metalizations, of which only metallization 32 48 is shown. This thyristor is formed by regions 130, 38, 33 62, and 40, which i8 a lateral transistor. Thyristor 112 34 of Figure 6B is ~ormed by the regions 128, 38, 62, and 40.

~omey Do~ No. ~ Page 17 - 2~la~32 1 By symmetry, it is possible to recognize in Figure 7A the 2 thyristors 118 and 120 of Figure 6B. Thyristor 118 is 3 formed from regions 136, 40, 62, and 38, and thyristor 120 4 is formed from regions 138, 40, 62, and 38.

Figure 9 depicts the star protection circuit of Figure 6 4, with the addition of thyristor protection circuits. Due 7 to the different configuration of this device, these 8 thyristors implement the tip to ring connection shown in 9 Figures 6A and 6B. The orientation of the various cells has been changed from that shown in Figure 4, but the 11 bilateral PNPN switches operate as previously described.

12 N+ regions 138, 140 are formed as shown in P-well 13 region 68. N+ regions 142, 144 are formed as shown in 14 P-well 70. As in the immediately preceding embodiment, metal contact 82 is modified to contact N+ region 144.
16 Metal contact 146 contacts N+ region 142, and is used to 17 connect to the eqjuipment being protected. Figure 10 is a 18 section view of the device of Figure 9, taken through 19 section line A-A. It is similar to the device shown in Figure 5, with the inclu~ion of the thyristor structures.
21 The resistors shown in Figures 6A and 6B are formed by the 22 current path through P-well 70 between metal contact 82 and 23 metal contact 146. As before, the P-well 70 acts as the 24 control gate for the thyristor devices. The P-well 88 underlying the P-well 70 has been enlarged to extend under 26 the thyristor devices as well as under the N+ region 76.
27 In those portions of the P-well not extending under the 28 thyristor~, P-well region 88 will extend only under the N+
29 region 76.

In Figure 10 the thyristor 110 of Figure 6A is located 31 between the metalizations 82 and 92. This thyristor is 32 ~ormed by the regions 144, 70, 86, and 88. Thyristor 112 33 of Flgure 6A i8 located between metalizations 146 and 92, 34 and is formed by the regions 142, 70, 86, and 88. These ~or~ Da*d ~. ~ Page 18 ~ 2 i 1~632 1 two thyristors have a common control gate defined by the 2 layer 70. The resistors shown in Figure 6B are the current 3 path between metal contact 82 through the p-well 70, 4 underneath N+ regions 142, 144, to the metal contact 146.

In Figure 9, by symmetry, the thyristor 118 shown in 6 Figure 6A is formed from regions 140, 68, 86, and 88.
7 Thyristor 120 in Figure 6A is formed from regions 138, 68, 8 86, and 88. The contact 92 (Figure 10) is connected to the 9 ground contact 84 by a diode formed by regions so, 86, and 72. The thyristors 110, 112, 118, and 120 shown in Figure 11 6B are built in Figure 9 exactly the same way as in Figure 12 7A.

13 The chip designs described above provide numerous 14 advantages related to packaging of the completed devices.
They are symmetrical, and several package designs can be 16 used to accommodate the chips containing the protective 17 circuitry.

18 Figure 11 shows one preferred bonding technique for 19 the star chip design described in Figure 4. A semi-conductor die 148 is formed according to the structure of 21 Figure 4. The die 148 is bonded to a heat sink 150, which 22 can be used to carry heat out of the package. Metal 23 contacts 152, 154 are used to connect to the tip and ring 24 lines, and metal contact 156 is connected to ground.

The contacts are bonded to leads 158, 160, 162 using 26 techniques well known in the art. Because all of the 27 necessary circuitry is contained on a monolithic device, 28 only three leads are required.

29 If the die 148 is a 5-terminal device, as described in connection with Figure 9, two additional leads can be 31 provided in the lead frame, and bonded to the appropriate 32 locations on the die. Again, this package is simple to .~:
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~`~` 2lla632 1 construct, and the fact that all required circuitry is 2 contained on a single chip simplifies packaging and insures 1 3 that a good hermetic seal can be made.

4 Referring to Figure llB, a similar bonding arrangement is illustrated for the device of Figure 2. Because the 6 ground contact is on the back side of the chip, the surface 7 area of the die 164 is less than that of die 148. In this 8 example, die 164 is bonded to a conductive heat sink 166, 9 which serves to conduct heat away from the device and acts ~ -as the ground contact. In a package of this type, the 11 device would be normally attached to a grounded external 12 heat sink. Metal contacts 168, 170 are connected to leads 13 172, 174, which are in turn connected to the tip and ring 14 lines.

As shown in Figure llB, the design having the ground 16 connection on the back side of the device is much smaller, 17 and may have some packaging advantages. However, such 18 design requires that a lead or other conductive connection 19 be made to the back side of the device, and requires that, if a heat sink is connected to the device, that the heat 21 sink be grounded. As an alternative to the technique shown 22 in Figure llB, a ground contact can be connected to the 23 back side of the device, and extend to the right as do 24 leads 172, 174.

; 25 Figure 12 illustrates one technique for placing ; 26 devices of the type described into a hermetically sealed 27 package. The semiconductor die 176 is attached to a heat 28 sink 178. If the delta configuration is being packaged, 29 the heat sink 178 will be suitable for connection to a grounded structure.

31 A package 180 made of injection molded plastic, or 32 other suitable material, surrounds the die 176 and heat 33 sink 178. Leads 182, 184 may be attached so as to project U~m~ ~d ~. ~ Page 20 ~
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211~632 1 out both sides of the package 180, or may project from only 2 a single side as shown in Figure llB. From the point at 3 which they project from the package 180, the leads may 4 remain horizontal (not shown), or may curve down to make S contact at a location which is coplaner with the bottom of 6 the heat sink 178. Alternatively, as shown in phantom 186, 7 188, the leads may be curved to form a J-lead package as 8 shown.

9 One advantage to the star structure illustrated in Figure 4 is that it may be easily reconfigured to operate 11 as an unbalanced protection circuit as shown in Figure lC.
12 This may be done as a packaging option, without changing 13 the actual layout of the chip. This is done by modifying 14 the lead arrangement of Figure llA to have a single wide lS lead projecting to the left, in an identical manner to lead 16 162 which pro~ects to the right. The combined lead 158, 17 160, and the lead 162 can then be connected to the tip and 18 ring lines of the circuit. The common terminal on the back 19 side o~ the device is bonded to a conductive heat sink 178 as shown in Figure 12. This conductive heat sink is, in 21 turn, connected to a grounded heat sink, or otherwise 22 connected to ground potential. Thus, the star 23 configuration device can be converted to an unbalanced 24 configuration device using the same die.

Figure 13A and 13B illustrate another layout technique 26 for the device which enables different protective designs 27 to be realized using bonding options. In Figure 13A, a 28 semiconductor die 190 is bonded to a heat sink 192. The 29 semiconductor die 190 contains four regions 194, 196, 198, 200 which may be identical. Each of the regions 194-200 31 can be laid out the same as one of the P-well regions 32 contained on the upper side of the chip design of Figure 2.
33 Theee ~our regions are separated by oxide regions, and each 34 ha~ a metal contact on the top.

~ DK~ ~ ~ Page 21 ~-~ 2110632 1 In order to form a star arrangement, three leads 202, 2 204, 206 can be bonded to the die 190 as shown. Lead 202 ;
3 is bonded to region 194, and lead 206 is bonded to region 4 200. Lead 204 is bonded to both regions 196, 198, and is preferably a wider lead in much the manner of the lead 6 shown in Figure llA. Lead 204 is then suitable for 7 connection to ground, while leads 202 and 206 are connected - --8 to the tip and ring lines.

9 Figure 138 illustrates a bonding arrangement for the 10 same die 190 which gives a delta configuration. In this -11 bonding technique, leads 208 and 210 are each connected to 12 two of the regions 194-200. The heat sink 190 is 13 conductive, and lead 212 is connected to this heat sink.
14 This results in the unbalanced arrangement shown in Figure 15 lC. ~-16 As will be appreciated by those skilled in the art, 17 tho chip designs and packaging arrangements set forth above 18 provide a single, monolithic device which is capable of 19 performing overvoltage protection for devices such as those attached to telephone lines. Since these designs utilize 21 a single semiconductor device, they may be inexpensively 22 packaged and still be adequately protected against harsh 23 environmental condition~. A number of different package 24 designs can be used with a single integrated circuit design.

26 While the invention has been particularly shown and 27 described with reference to a preferred embodiment, it will 28 be understood by those skilled in the art that various 29 changes in form and detail may be made therein without deptrting from the spirit and scope of the invention.
, ' " "' ', ~m~Do~t~.n~ Page 22

Claims

1. An overvoltage protection circuit, comprising:
first and second regions, formed within a substrate having a first conductivity type, said first and second regions having a second conductivity type and having the same area;
third and fourth regions, having the first conductivity type, formed within said first and second regions, respectively, wherein said third and fourth regions are not continuous, having sub-areas contained within them through which portions of said first and second regions, respectively, are exposed,;
a fifth region, formed within the substrate, having the second conductivity type and having an area approximately twice that of said first region;
a sixth region, having the first conductivity type, formed within said fifth region, wherein said sixth region is also not continuous, also having sub-areas contained within it through which portions of said fifth region is exposed, and wherein the hole density of the sub-areas in said sixth region is at least two-thirds less than the respective hole density of the sub-regions within the third and fourth regions; and first, second and third conductive contacts connected to said first, second, and fifth regions, respectively, said first contact also contacting said third region, said second contact also contacting said fourth region, and said third contact also contacting said sixth region;
wherein bilateral switches are formed between each pair of said conductive contacts.

2. The overvoltage protection circuit of Claim 1, wherein said fifth region is formed on a surface of the substrate opposite that of said first and second regions, whereby the bilateral switches form a delta configuration.

3. The overvoltage protection circuit of Claim 1, wherein said first, second, and fifth regions are formed on a single surface of the substrate, whereby the bilateral switches form a star configuration.

4. The overvoltage protection circuit of Claim 3, further comprising a conductive common node formed on a second surface of the substrate opposite the single surface.

5. The overvoltage protection circuit of Claim 4, wherein said conductive common node comprises a metal layer formed on the second substrate surface.

6. The overvoltage protection circuit of Claim 1, wherein the first conductivity type comprises N-type, and the second conductivity type comprises P-type.

7. The overvoltage protection circuit of Claim 1, further comprising:
first and second sensors electrically connected to said first and second contacts for sensing current flow through signal lines connected to said first and second contacts; and first and second circuits, connected to said sensors, for electrically connecting the first and second contacts together when the sensed current flow surpasses a selected level.

8. The overvoltage protection circuit of Claim 7, said first and second sensors comprise resistors.

9. The overvoltage protection circuit of Claim 8, wherein said first and second circuits comprise thyristors.

10. The overvoltage protection circuit of Claim 7, wherein said sensors and circuits operate for current flowing in a first direction, and further comprising:

third and fourth sensors electrically connected to said first and second contacts for sensing current flow through the signal lines in a second direction; and third and fourth circuits, connected to said third and fourth sensors, for electrically connecting the first and second contacts together when the sensed current flow in the second direction surpasses the selected level.

11. The overvoltage protection circuit of Claim 7 or Claim 10, wherein said sensors and said circuits are formed within said first and second regions, thereby forming a monolithic integrated circuit.

12. The overvoltage protection circuit of Claim 1, further comprising leads connected to said first, second, and third contacts.

13. The overvoltage protection circuit of Claim 12, wherein said leads extend externally of an insulating package containing the substrate.

14. The overvoltage protection circuit of Claim 1, further comprising leads connected to said first and second contacts, and further comprising a conductive heat sink connected to said third contact.

15. The overvoltage protection circuit of Claim 4, wherein the conductive common node is connected to a heat sink external of a package containing the substrate.

16. The overvoltage protection circuit of Claim 1, wherein the sub-areas in said third, fourth, and sixth regions are circular.