CA2089014A1 - Hysteresis comparator circuit - Google Patents
Hysteresis comparator circuitInfo
- Publication number
- CA2089014A1 CA2089014A1 CA 2089014 CA2089014A CA2089014A1 CA 2089014 A1 CA2089014 A1 CA 2089014A1 CA 2089014 CA2089014 CA 2089014 CA 2089014 A CA2089014 A CA 2089014A CA 2089014 A1 CA2089014 A1 CA 2089014A1
- Authority
- CA
- Canada
- Prior art keywords
- comparator
- circuit
- impedance element
- hysteresis
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
- H03K3/02337—Bistables with hysteresis, e.g. Schmitt trigger
Landscapes
- Manipulation Of Pulses (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A hysteresis comparator circuit is provided wherein an input impedance element is connected to a non-inverted input terminal of a comparator, and a feedback impedance element is connected between an output terminal of the comparator and the non-inverted input terminal. The feedback impedance element and input impedance element are connected with each other to cooperatively constitute a differentiation circuit when seen from the output terminal side of the comparator. With this arrangement, it becomes possible to eliminate an undesirable extension of the pulse width resulting from a hysteresis and at the same time, to Prevent chattering. Further, this hysteresis comparator circuit requires no additional special circuit there by reducing the substrate accommodating space and manufacturing cost.
A hysteresis comparator circuit is provided wherein an input impedance element is connected to a non-inverted input terminal of a comparator, and a feedback impedance element is connected between an output terminal of the comparator and the non-inverted input terminal. The feedback impedance element and input impedance element are connected with each other to cooperatively constitute a differentiation circuit when seen from the output terminal side of the comparator. With this arrangement, it becomes possible to eliminate an undesirable extension of the pulse width resulting from a hysteresis and at the same time, to Prevent chattering. Further, this hysteresis comparator circuit requires no additional special circuit there by reducing the substrate accommodating space and manufacturing cost.
Description
2 ~
SPECIFICATION
[Title of the Invention]
HYSTERESIS COMPARATOR CIRCUIT
~Backsround of the Invention]
_ [Field of the Invention]
The Present invention relates to a hysteresis comparator circuit which is capable of detecting. for, e,x,a,m,ple,,th*,,~ulse , width of an analo8ue Pu!se signa! supplied from a Particle - measurement apparatus. without givin~ rise to an adyerse .. . _ . . .., _ . , .
effect such as the generation of noises.
[Description of the Prior Art]
In order to detect the Pulse width and the like of an analosue pulse signal. it is general to utilize a hYsteresis conparator circuit havin~ a hYsteresis characteristic as included in its input-outPUt characteristics.
Conventionally, this kind of hysteresis comparator circuit has been constituted such that as shown in Fig. 9, a signal V~ to be detected (or a target signal) is supplied from an inPut terminal TMI to an inverted inPut terminal T, of a comparator CP as a voltage V_.
Further, a reference signal VR is supplied from an input terminal TM2 via an input resistor RI1 to a non-inverted input ~8~01~
terminal T12 of the comparator CP as a volta8e V+.
In addition, an output terminal T13 of the comPa.rator CP
is connected via a feedback resistance R~ to the non-inverted terminal T~2.
Then, an outPut voltage VO generated from the outPut terminal Tlg of the comparator CP is taken out from an output teruinal TM3.
Thus, with such a circuit arrangement that the input resistor Rl, is connected to the non-inverted inPut terminal Tl2 of the comParator CP and the feedback resistor RFI ;S
interposed between the output ter~inal Tl3 and the non-inverted inPut terminal Tl2 of the comParator CP, the comparator CP can possess a hYsteresis characteristic as included in its inPut-outPut characteristics by the aPplication of a positive feedback on the comParator CP, therebY Preventing chatterin8s due to noises and etc.
Fig. 10 is a wave form diagram illustrating an operation of the hYsteresis comparator circuit of Fig. 9. In Fig.
lO(a) there are shown the target signal V~, the voltage V_ (=
V~) applied to the inverted input terminal Tll of the comParator CP, and the voltage V+ applied to the non-inverted inPut terminal Tl2 of the comparator CP. Further, in Fig.
lO(b) there is shown the outpùt voltage VO appearing at the outPUt terminal Tl3 of the comparator CP.
As described above, the hYsteresis comparator circuit .
shown in Fig. 9 is caused to have a hYsteresis characteristic by the application of a Positive feedback throu8h the Input resistor RI1 and the feedback resistor RF1 SO that there arises a voltage difference V with respect to the volta8e V+
betqeen the risetime and falltime of the signal Vs to be detected. That is, there aPPears a hYsteresis width of the voltage V. Consequently, the Pulse width TB nf the output voltage VO appearing at the outPut terminal T19 oi the comparator CP becomes larger by T than the pulse width TA Of the output voltage when the comparator CP has no hYsteresis characteristic. That is, no accurate pulse width can be obtained. This also means that the judgment of termination of the pulse si8nal is delayed by that amount T.
In order to reduce the above-mentioned pulse width extension of T, the hYsteresis width V maY be made small but in that case, chatterings tend to take place due to noises.
To satisfy these contradictory requirements, the hYsteresis component (voltage V) of the voltage V+ maY be eliminated midway between the risetime and falItime of the signal Vs so that the voltage V+ can be returned to the level of the referenoe signal VR. Thus, as a Prior art technique for eliminatlng such a hYsteresis component of the voltage V+, there is disclosed in the JaPanese Unexamined Patent APPI ication No.
SH0 63-298029 a means for varying the reference voltage of a :
~ ~ r~
comparator bY using an analog switch.
However, the above-mentioned circuit configurati.on for varYing the comparator reference voltage has been disadvantageous in view of the substrate receiving space and nanuiacturing cost since a special circuit for varying the reference voltage must be added to a conventional hYsteresis comparator circuit.
[SuGmarY of the Invention]
Accordingly, an obiect of Present invention is to provide a hYsteresis comparator circuit which is caPable of eliminating an undesired pulse wldth extension occurring due to a hYsteresis and with which chatterings hardlY take Place.
Another object of the Present invention is to provide a hYsteresis comparator circuit which does not require an additional special circuit therebY saving the substrate accommodating space and manufacturing cost.
According to a first aspect of the Present invention, there is Provided a hYsteresis comParator circuit comPrising an inPut imPedance element connected to a non-inverted inPut terminal of a comParator, and a feedback imPedance element connected between an output terminal of the comparator and the non-inverted inPut terminal. The input imPedancè element and feedback impedance element are so set as to constitute a differentiation circuit when seen from the outPut terminal side of the comParator.
~ ith the above arrangement, when a si~nal to be detected is inputted to an inverted inPut terminal of the compara,tor and a reference signal is inPutted via the inPut i-Pedance ele-ent to the non-inverted input terminal of the comParator, if the voltage at the inverted inPut terminal of the comparator exceeds the reference signal; i.e. the voltage at the non-inverted input terminal of the comparator, at the risetime of the voltage at the inverted inPut terminal of the comParator, the outPUt voltase of the comparator turns from a HlGH-level to a LOW-level.
Then, this LOW-level voltage is aPPlied to the non-inverted input terminal of the comparator via the feedback impedance element.
In this instance. as the feedback impedance element and the inPut impedance element constitute a differentiation circuit whe seen from the outPut terminal side of the comparator, the voltage at the non-inverted inPut terminal of the comparator immediately droPs below the voltage level of the reference signal to cause a hysteresis, and no chattering Phenomenon due to noises takes place. Thereafter, the voltage of the non-inverted inPut terminal of the comParator continuouslY
increases with a gradient determined by the characteristics of this differentiation circuit; i.e. the time constant determined bY the feedback impedance element and the inPUt impedance element, until it reaches the voltage level oi the reference sisnal, so that the hYsteresis is finallY eliminated.
Furthermore, at its falltime, iS the volta8e of the target signal decreases down below the volta8e of the reference signal, the output voltage of the comParator turns from a LOW-level to a HlGH-level. Then. this HlGH-level voltage is suPPlied via the feedback impedance element to the non-inverted inPut terminal of the comParator.
_ In this case, the voltage at the non~-inverted input terminal of the comParator immediatelY increases above the voltage level of the reference signal to cause a hYsteresis and no chattering phenomenon due to noises takes Place. After that, ~ the voltage of the non-inverted input terminal of the comparator continuously decreases with a gradient determined by the characteristics of this differentiation circuit; i.e. the time constant determined by the feedback imPedance element and the in put imPedance element, until it reaches the voltage level of the reference signal, so that the hYsteresis is finally eliminated.
As is exPlained in the ioregoing descriPtion. in accordance with the hYsteresis comparator circuit of the present invention.
the voltage of the non-inverted inPut terminal of the comparator largelY varies immediatelY after the output voltage of the comparator has changed from a HlGH-level to a LOW-level and also immediately after the output voltage of the comparator has subsequently changed irom a L~W-level to a HlGH-level so that the comParator circuit may possess an appropriate hYsteresis effective for suppressing the chattering Phenomenon.
~ o ~
Furtheroore, the volta~e level before the output voltsse of the ComParatOr changes from a HlGH-level to a LO~-level can be equalized to the voltage level before the output voltage of the comparator subsequentlY changes from a LO~-level to a HlGH-level, so that it becomes possible to eliminate an undesirable extension of thepulse width resulting from the hYsteresis.
_ Moreover, all that is required ior arran8ing this circuit is only the connection of the ieedback impedance element and the inPut ImPedance element so as to constitute the differentiation circuit when seen from the output terminal side of the comParator. AccordinglY, it is not necessarY to Provide a particular circuit seParatelY which results in saving the substrate accomEodating space and ~anuiacturing cost.
According to a second aspect of the Present invention there is Provided a hYsteresis comParator circuit which comprises a ieedback imPedance ele~ent and an inPut impedance elèment wherein at least either one of these two elements is constituted bY a Parallel circuit composed oi iirst and second series circuits of which the first series circuit includes a first imPedance element and a iirst unilateral conductive element that allows current to flow in one direction only, and the second serial circuit includes a second imPedance element and a second unilateral conductive element.that allows current to flow in the other direction onlY.
. In this case, the impedance value of unilateral current ~'~8~f-~
path passing through the first series circuit including the first unilateral conductive element and the first impedance element is made different from the illPedance value of the other current path Passing through the second series circuit including the second unilateral conductive element and the second impedance element, in at least either of the feedback impedance element or the inPut impedance -element.
With this arrangement, it becomes Possible to intentionallY
varY the width of a hYsteresis and the hYsteresis attenuation characteristics of the circuit between the risetime and the fall tiee of the target signal.
Nameiy, the hYsteresis width and hYsteresis attenuation characteristics obtained when the output voltage of the comparator turns from a HlGH-level to a LOW-level at the risetime of the target siYnal can be made different from those obtained when the output voltage of the comParator subsequently turns from a LOW-level to a HlGH-level at the falltime of the target signal.
Accordingly, the hysteresis comparator circuit in accordance with the second asPect of the Present invention, a wide varietY of use can be exPected. For example, where a pluralitY of target signals to be detected are continuouslY
inPutted, all the remaining signals that follow the first target signal can be intentionallY ignored. That is, a masking is effectivelY carried out in this hYsteresis comparator circuit x ~
embodying the Present invention.
[Brief DescriPtion of the Drawin8s]
Fig. 1 is a circuit diagram showing a concrete configuration of a hYsteresis comparator circuit according to a first embodiment of the Present invention;
Fig. 2 is a circuit dia8ram showing a concrete example of the hYsteresis comParator circuit shown in Fig. 1;
Fi8. 3 is a waveform diagram showinB an operation of the hYsteresis comparator circuit shown in Fig. 2;
Fig. 4 is a circuit diagram showing another examPle oS the hYsteresis comParator circuit shown in Fig. l;
Fig. 5 is a circuit diagram showing a hYsteresis comParator circuit configuration according to a second e~bodi-ent of the present invention;
Fig. 6 is a waveiorm diagram showing an oPeration of the hYsteresis comParator circuit shown in Fig. 5;
Fig. 7 is a waveform diagram also showing an operation of the hYsteresis comParator circuit shown in Fig. 5;
Fig. 8 is a circuit diagram showing a hYsteresis comparator circuit configuration according to a third embodiment of the present invention;
Fig. 9 is a circuit diagram showing an examPle of a conventional hYsteresis comparator circuit configuration; and Fig. 10 is a waveform diagram showing an oPeration of the hysteresis comparator circuit shown in Fig. 9.
Fig. Il is a circuit diagram showing a hYsteresi.s comparator circuit configuration according to a fourth embodiment of the Present invention; and Fig. 12 is a waveiorm diagram showing an oPeration of the hYsteresis comparator circuit shown in Fig. 11.
~Detailed DescriPtion of Preferred Embodiments]
The first embodiment of the present invention will now be described by referring to Figs. 1 through 4. As shown in Fig. 1, an inPut impedance element Z~ is connected to a non-inverted inPut terminal T12 of a comParator CP and a feedback imPedance element Z2 is interposed between an oUtPUt terminal T13 and the non-inverted input terminal T12 of the comParatOr CP, therebY
Sorming a hYsteresis comparator circuit.
The feedback impedance element Z2 and the input imPedance element Z1 are connected with each other to cooPerativelY
constitute a difierential circuit DF when seen irom the outPut terminal T~3 side of the comParator CP.
In this hYsteresis comparator circuit. a signal V8 to be detected is supplied from an inPut terminal TM~ to an inverted input terminal T~1 of the comparator CP as a voltage V_. This signal V8 is represented by, for examPle. a Particle detecting signal obtained from a particle measurement apparatus such as a flow cYtometer or the like.
Further, a reference signal VR to be compared to the signal V8 is supPlied from an input terminal TM2 via an input impedance element Z, to a non-inverted inPUt terminal T12 as a voltage V+
In addition, an output voltage VO at an outPut terminal T~3 of the comparator CP is fed back to the non-inverted input terminal T12 throu8h a feedback imPedance element Z2 _ Then, the outPut voltage VO apPearing at the outPut terminal T~ of the comParator CP is taken out from an output terminal TM3 In the case of the above hYsteresis comparator circuit, ~ when the target signal V~ is inPutted to the inverte~d input terminal T11 of the comParatOr CP and the reference signal VR jS
inPutted to the non-inverted input terminal T12 of the coaparator CP through the inPut imPedance element Z" and if the signal V~; i e the voltage V_ of the inverted inPUt terminal T~, of the comparator CP, exceeds the reference signal VR; i e the voltage V+ of the non-inverted input terminal Tl2 of the comparator CP at its risetime, the output voltage VO of the comparator CP turns from a HlGH-level to a LOW-level Then, this LOW-level voltage is suPPlied via the feedback impedance element Z2 to the non-inverted inPut terminal T12 of the comparator CP
In this case, as the feedback impedance element Z2 and the inPut impedance element Z~ constitute a differentiation circuit DF when seen from the output terminal T~3 side of the comparator CP,the voltage Y+ of the non-inverted input terminal T,2 of the ~08~
comparator CP immediatelY droPs belo~l the voltage level of the reference signal VR to generate a hYsteresis so that no chattering takes Place. After that, the voltase V+ of the non-inverted inPut terminal T12 of the comParator CP
continuously increases with a 8radient determined bY the characteristics of this differentiation circuit DF; i.e. a time constant determined by the feedback impedance ele-ent Z2 and the inPut imPedance element Z~, until it reaches the voltage level oi the reference sisnal VR. Thereiore, the hYsteresis is iinally eliminated.
Furthermore, at the falItime of the tarset sisnal Vs, if the volta8e of the detected sisnal Vs decreases down below the voltage of the reference signal VR~ an outPut voltase VO of the comParator CP turns from a LOW-level to a HlGH-level. Then, this HlGH-level voltage is suPPlied vin the feedback impedance element Z2 to the-non-inverted inPUt terminal T12 of the comparator CP.
In this case, the voltase V~ of the non-inverted inPut terminal T12 of the comparator CP immediatelY increases above the voltage level of the reference signal YR to cause a hYsteresis. Thus, the chattering Phenomenon due to noises is surely suPpressed.
Thereafter, the voltage ~ oi the non-inverted input terminal T12 of the comParator CP continuouslY decreases with a sradient determined by the characteristics of this difierentiation circuit DF; i.e. the time constant determined bY
the feedback impedance element Z2 and the inPUt impedance eleuent Z1, until it reaches the voltage level of the reSerence sisnal VR. Therefore, the hYsteresis is finally eliminated.
As has been explained in the foregoing description, in accordance ~ith this hYsteresis comParator circuit of the present invention, the voltage V+ of the~non-inverted input ter~inal T12 of the comparator CP is largelY varied immediatelY
aiter the output voltage VO of the comparator CP has chan8ed irom a HlGH-level to a LOW-level and also immediatelY after the output voltage VO of the comparator CP has subsequently chansed from a LOW-level to a HlGH-level. Hence, it becomes Possible for the comparator CP to Possess an aPpropriate hYsteresis characteristic effective for suppressing the chattering phenomenon.
Furthersore, the voltage level of the target signal Vs before the outPut voltage VO of the comParator CP changes from a HlGH-level to a LOW-level is equalized with the voltage level of the target signal Vs before the output voltage VO of the comparator CP subsequently changes from a LOW-level to a HIGH-level. Therefore, it becomes possible to eliminate an undesirable extension of the pulse width that is inevitably derived from the hYsteresis. s Moreover, all that required for arranging this circuit is only to connect the feedback impedance element Z2 and the input ~ag~oll~
imPedance element Zl with each other to cooPerativelY constitute the differential circuit DF when seen from the same sid-e as the outPut terminal T~3 of the co~parator CP. AccordinglY, there is no requirement for additionally providing a sPecial circuit, which results in the advantage of reducing the substrate accommodating sPace and the manuiacturing cost.
_ Next, Fig. 2 shows a specific circui~t examPle wherein a resistor is used as the input i~Pedance element Z1 and a caPacitor is used as the feedback impedance element Z2.
In Fig. 2. an inPut resiætor Rl1 IS one that is used as the input imPedance element Z1 and a feedback capacitor CF~ is one that is used as the ieedbàck loPedance element Z2. These inPut resistance RI1 and the ieedback capacitor CF1 are connected with each other to cooPerativelY constitute a difierentiation circuit when seen from the outPut terninal T13 side of the conparator CP.
Other co-Ponents of this circuit are the same as those of the above-described circuit shown in Fig. l.
Fig. 3 is a waveform diagram showing an operation of the hYsteresis comparator circuit shown in Fig. 2. Fig. 3(a) shows the target signal Vs to be detected , the voltage V_ (= Vs) aPPlied to the inverted inPut terminal T1~ of the comparator CP, and the voltage V+ apPlied to the non-inverted input terminal T12 of the comParator CP. (In the initial condition, the volta~e V+ aPPlied to the non-inverted inPUt terminal T~2 of the comParator CP is equal to the reference signal V~).
9~
Further, in Fis. 3(b) there is shown the outPut voltage YO
appearing at the output teroinal T13 of the comparator-CP.
Though the operation of thi 8 circuit has been previouslY
described with reference to Fig. 1, the same operation will be described again Dith reference to Fig. 3.
In the hYsteresis comParator circuit shown in Fig. 2, when the target signal V8 is s-aller than the reference si~nal VR.
the outPut signal VO of the comparator CP is at HlGH-level.
HoDever, if the signal V8 exceeds the reference signal VR at its rlsetioe, the output signal VO of the cooparator CP turns from a HlGH-level to a LOW-level.
Accordin81Y, the volta8e V+ of the non-inverted inPut teroinal T12 of the comparator CP imoediatelY changes (drops) bY
the amount of variation of the outPut voltage VO. In other words, the voltage V+ of the non-inverted inPut terminal T~2 f the comparator CP changes by an amount corresponding to the difference between the output voltage VO at a HlGH-level and the output voltage VO at a LOW-level. However, the voltage V+ once dropped continuouslY increases with a time constant of CF1 Rl1 until it returns to the voltage level of the reference signal VR.
Furthermore, at the falItime of the target signal Vs, the output voltage VO of the comparator CP turns from a LOW-level to a HlGH-level when the signal ~s becomes smaller than the reference signal VR.
AccordinglY, the voltage V+ of the non-inverted input _ 15 _ ~9~901~
ter~inal T12 of the comparator CP immediatelY changes (increases) by an amount corresponding to the amount of variation of the outPUt voltage VO. In other words, the voltage V+ of the non-inverted input terminal T~2 of the comparator CP changes bY an a~ount corresPonding to the difference between the output voltage VO at a HlGH-level and the outPut voltage VO at a LO~-level. However, the voltage V~ once incr-eased continuouslY
decreases with the time constant of C~ RI1 until it returns to the voltage level of the reference signal VR.
Consequently, the coDparator CP can compare the target signal V~ with the same reference signal VR at both the risetime and falltime of the signal Y~. In other words, it becomes possible for the comparator CP to temporarilY possess the hYsteresis necessary for suppressing the chatterin~ phenomenon only for a limited period of time, immediatelY after the output voltage VO of the comparator CP has turned from a HlGH-level to a LOW-level or vice versa.
Accordingly, an undesirable extension of the pulse width experienced in a conventional hYsteresis ComParator circuit no longer takes Place. Thus it becomes possible to accuratelY
detect a Pulse width, and the chattering phenomenon can of course be effectivelY supPressed.
Furthermore, the circuit'-of the present invention uses a capacitor instead of a resistor as serving a conventional feedback impedance element so that it is not neCessarY to ~ a ~
provide a particular circuit seParatelY therebY savin8 the substrate accommodating space and manufacturing cost..
Moreover, it is Possible to varY the time required for allowing the voltage V+ at the non-inverted input terninal T12 of the comParator C~ to return to the voltage level of the reference voltage VR by varying the time constant.
_ Next, Fig. 4 shows a concrete circuit exa-Ple wherein a resistor is used as the inPut ImPedance element Z~ and a series circuit of a capacitor and a resistor is used as the feedback i-pedance element Z2 .
~ In Fig. 4, the inPut resistor Rl1 is one that is used as the input impedance element Z1 and a series circuit of a feedback capacitor CF1 and a feedback resistor RF2 is one that is used asthe feedback imPedance element Z2. The feedback cspacitor CF1, feedback resistor RF2. and inPut resistor Rl1 are connected withone another so as to constitute a differential circuit when seenfrom the output terminal T1g side of the comParator CP. Other ComPOnents of this circuit are the same as those shown in Fi~. 2.
BY using such a serial circuit of the feedback capacitor CF1 and the feedback resistor RF2 as the feedback impedance element Z2. it becomes Possible to vary the width of the hYsteresis generating immediatelY after the output voltage VO of the comparator CP has changed from a HlGH-level to a LOW-level or vice versa. The width of this hYsteresis can be properlY
~08901~
deternined dependin~ on the kind of signal to be handled Moreover, the width of the hYsteresis can also ~e chan~ed in the saue uanner when the non-inverted inPut teruinal T12 of the cosparator CP is grounded throu8h a resistor Other ~eatures are the saoe as those of the hYsteresis couparator circuit shown in Fi~ 2 _ A second eubodioent of the Present invention will be explained in detail with reference to Figs 5 throuRh 7 As shown In Fig 5, this hYsteresis coeParator circuit }s couPosed of the inPut resistor R~l servin8 as the input iapedance ele-ent Zl of Fi8. 1, a feedback capacitor C~l, feedback resistor RF5.
RF4 and diodes D~, D2 serving as the feedback inpedance eleuent Z2. with the re-ainin8 Portion belns the saoe as that in Fi8. 1.
That is, the feedback iuPedance eleuent is constituted such that a series circuit ot the feedback resistor RF3 (an i-pedance elenent) and the diode D, (a first unilateral conductive elesent) is connected Parallel to a series circuit of the feedback resistor RF4 (a second iuPedance elenent) and the diode D2 (a second unilateral current conductive ele~ent) and the feedback capacitor C~l is connected in series with the parallel circuit In this case, the values for the feedback resistors are set differentlY
With this arrangeoent, w~en the outPut voltage VO of the couparator CP chanses frou a HlGH-level to a LOW-level at the risetiue of the target si~nal V~, the diode D, is turned on and .
the diode D2 is turned off so that the width of hYsteresis becomes RIl/(RIl ~ RF3)- Vo and the time constant of hY-steresis attenuation beco-es Cpl/(RIl + Rp~-Furthermore when the outPUt volta8e YO of the comparatorCP turns from a LOW-level to a HlGH-level at the falltiue of the target si8nal VB~ the diode D1 is turned off and the other diode D2 is turned on so that the width of hYst~eresis becomes R~l/(RII ~ Rp4) Vo and the time constant of hYsteresis attenuation becomes Cpl/(RI~ ~ Rp4).
With this arrangement, it becomes Possible to intentionallY varY the hYsteresis characteristics at the risetime and the iallti-e of the target signal V8 Namely, the hYsteresis width and hYsteresls attenuation characteristics at the time when the outPUt voltage VO of the comparator CP turns from a HlGH-level to a LOW-level in the risetime of the target si8nal V8 can be differentiated from those when the outPut voltage VO of the comparator CP
subsequently turns from a LOW-level to a HlGH-level at the falltime of the target si8nal V8.
For example, when more than two target signals V5 to be detected are inPutted in sequence, it is Possible to ignore (mask) those following the first signal by intentionally increasing the time constant ~
Figs 6 and 7 are waveform diagrams showin8 an oPeration of the hYsteresis comparator circuit of Fig 5 wherein Figs 6(a) ~ ' ' ' ' " :' ' ~:
and 7(a) corresPond to Fig. 3(a), ancl 3(b) resPectivelY.
Fis. 6 shows a waveform when the time elapsed from the generation of a hYsteresis to the termination thereof at the risetime of a target signal VB jS matle sufficiently shorter than the Pulse width oi an analog Pulse signal as the target signal VB and the time elaPsed from the generation of a hYsteresis to the termination thereof at the falltime o~f the signal V~ is made longer than that at the risetime of the signal.
BY setting such a characteristic, even if an analog Pulse signal inPutted as the target signal V8 has irregulaties at the trailing-edge thereof, it becomes possible to accurately detect onlY the width of the first wave of the signal bY ignoring its succeeding waves.
Fig. 7 shows a wavefor- when the time elapsed from the generation of a hYsteresis to the termination thereof at the risetlme of the target signal VB is sufficientlY longer than the pulse width of analog pulse signal as the target signal V~ and the tlue elaPsed from the generation of a hysteresis to the termination thereof at the falltime of the signal is made shorter than that at the risetime thereof.
BY setting such a characteristic, even if analog pulse signals are inPutted in sequence as the signal V~, it becomes possible to ignore all the Pulse signals following the first one.
Therefore, it becomes easY to Perform a Pulse number counting operation bY excluding the ignored pulse signals.
, ' -~8~
The renaining portion is the saoe as that of the hysteresis comparator circuit of Fig. 2.
BY the waY, a similar oPeration can be Performed even if the inPut resistor R11 and the Parallel circuit consisting of the feedback resistors RF3~ RF4 and diodes D1, D2 are exchangd with each other in the circuit disclosed in Fig. 5.
_ A third embodiment of the present in~vention will be explained with reference to Fi8. 8.
As shown in Fig. 8, the hYsteresis comparator circuit according to this embodiment uses a Parallel circuit consisting of a first series circuit including an input resist-`or RI2 and a diode D3 and a second series circuit including an inPut resistor Rlg and a diode D4, instead of the input resistor Rl1 of Fig. 5.
The resaining Portion is the same as those oi Fig. 5.
In this case, the resistance values of the inPut resistors RI2. RI~ and the feedback resistor RF3. RF4 are so set as to satisfY a relationshiP of RI2 : RI9 ~ Rl9 : RI4.
In the case of the circuit configuration of Fig. 5, the hYsteresis width and time constant change together, but in the Fig. 8 embodiment, it becomes Possible to varY onlY the tine constant with the hYsteresis width kept unchanged.
BY the waY, it is possible to set the ratio between the values oi the inPut resistor Rl2. RI3 and the values of the feedback resistors RF3 and RF4 SO as to satisfy the equation of RI2 + RF3 = RI3 + RF4. In that case, it is Possible to vary ~9~14 onlY the hYsteresis width while keePing the time constant unchanged Now, a hYsteresis comparator circuit as a fourth embodiment of the Present invention will be exPlained by referring to Fig 11 and 12 In the circuit shown In Fig Il, the output voltage VO of the comParator CP is at a High-level when the signal V, to be detected (target signal) is smaller than the reference voltage level V+1 However, as shown in Fig 12, when the tar8et signal V~ exceeds the reference voltage level V+, at the rise time of the signal, the outPut voltage VO of the comParator CP changes from a Hi~h-level to a Low-level AccordinglY, the voltage Y+ at the non-inverted input terminal T12 of the comParator CP imaediatelY changes (decreases) from the voltage level V+l by an amount equivalent to the amount of variation of the output voltage VO That is, the voltage V+
at the non-inverted inPut ter'minal T12 of the comparator CP
changes bY an amount corresponding to the difference between the High-level outPut volta~e VO and Low-level output voltage VO
However, the voltage V+ thus decreased once increases with a time constant CF1.(R11/RF1) to finally reach the reference voltage level V+2 On the other hand, at the fall time of the target signal V~, when the target signal V~ is smaller than the reference voltage level V+2, the outPut voltage VO of the comParator CP changes from a Low-level to a High-level ~89~1~
Consequently, the voltage V+ at the non-inverted input terminal T1 2 also changes (increases) immediatelY from the voltage level V+2 by the amount oi variation of the outPut voltage. That is, the voltage V+ changes by an amount corresponding to the difference between the high-level voltage VO and the low-level voltage Vo. However, the voltage V, thus increased once decreases with the time constant CF1.(RI~/RFl) to finallY resch the reference voltage level V+,.
Accordingly, it is possible for the circuit to have a large hYsteresis onlY for a Poriod requlred to Prevent chatterings immediatelY after the inversion of the outPut voltage VO of the co~lParator CP.
As a result, the generation of chatterings due to noises can be controlled.
In addition, since the circuit of this embodiment does not require the provision oi any'separate particular circuit excePt the oere addition of a caPacitor to be connected to the resistor so as to serve as a conventional ieedback imPedance eleoent, there is no increase In the substrate receiving space or in the cost of manufacturing the circuit.
Moreover, by changing the tice constant, it is possible to varY the tlme required for the voltage V+ at the non-inverted inPut terminal Tl2 of the co~arator CP to reach the reference voltage levels V+~ and V+2.
SPECIFICATION
[Title of the Invention]
HYSTERESIS COMPARATOR CIRCUIT
~Backsround of the Invention]
_ [Field of the Invention]
The Present invention relates to a hysteresis comparator circuit which is capable of detecting. for, e,x,a,m,ple,,th*,,~ulse , width of an analo8ue Pu!se signa! supplied from a Particle - measurement apparatus. without givin~ rise to an adyerse .. . _ . . .., _ . , .
effect such as the generation of noises.
[Description of the Prior Art]
In order to detect the Pulse width and the like of an analosue pulse signal. it is general to utilize a hYsteresis conparator circuit havin~ a hYsteresis characteristic as included in its input-outPUt characteristics.
Conventionally, this kind of hysteresis comparator circuit has been constituted such that as shown in Fig. 9, a signal V~ to be detected (or a target signal) is supplied from an inPut terminal TMI to an inverted inPut terminal T, of a comparator CP as a voltage V_.
Further, a reference signal VR is supplied from an input terminal TM2 via an input resistor RI1 to a non-inverted input ~8~01~
terminal T12 of the comparator CP as a volta8e V+.
In addition, an output terminal T13 of the comPa.rator CP
is connected via a feedback resistance R~ to the non-inverted terminal T~2.
Then, an outPut voltage VO generated from the outPut terminal Tlg of the comparator CP is taken out from an output teruinal TM3.
Thus, with such a circuit arrangement that the input resistor Rl, is connected to the non-inverted inPut terminal Tl2 of the comParator CP and the feedback resistor RFI ;S
interposed between the output ter~inal Tl3 and the non-inverted inPut terminal Tl2 of the comParator CP, the comparator CP can possess a hYsteresis characteristic as included in its inPut-outPut characteristics by the aPplication of a positive feedback on the comParator CP, therebY Preventing chatterin8s due to noises and etc.
Fig. 10 is a wave form diagram illustrating an operation of the hYsteresis comparator circuit of Fig. 9. In Fig.
lO(a) there are shown the target signal V~, the voltage V_ (=
V~) applied to the inverted input terminal Tll of the comParator CP, and the voltage V+ applied to the non-inverted inPut terminal Tl2 of the comparator CP. Further, in Fig.
lO(b) there is shown the outpùt voltage VO appearing at the outPUt terminal Tl3 of the comparator CP.
As described above, the hYsteresis comparator circuit .
shown in Fig. 9 is caused to have a hYsteresis characteristic by the application of a Positive feedback throu8h the Input resistor RI1 and the feedback resistor RF1 SO that there arises a voltage difference V with respect to the volta8e V+
betqeen the risetime and falltime of the signal Vs to be detected. That is, there aPPears a hYsteresis width of the voltage V. Consequently, the Pulse width TB nf the output voltage VO appearing at the outPut terminal T19 oi the comparator CP becomes larger by T than the pulse width TA Of the output voltage when the comparator CP has no hYsteresis characteristic. That is, no accurate pulse width can be obtained. This also means that the judgment of termination of the pulse si8nal is delayed by that amount T.
In order to reduce the above-mentioned pulse width extension of T, the hYsteresis width V maY be made small but in that case, chatterings tend to take place due to noises.
To satisfy these contradictory requirements, the hYsteresis component (voltage V) of the voltage V+ maY be eliminated midway between the risetime and falItime of the signal Vs so that the voltage V+ can be returned to the level of the referenoe signal VR. Thus, as a Prior art technique for eliminatlng such a hYsteresis component of the voltage V+, there is disclosed in the JaPanese Unexamined Patent APPI ication No.
SH0 63-298029 a means for varying the reference voltage of a :
~ ~ r~
comparator bY using an analog switch.
However, the above-mentioned circuit configurati.on for varYing the comparator reference voltage has been disadvantageous in view of the substrate receiving space and nanuiacturing cost since a special circuit for varying the reference voltage must be added to a conventional hYsteresis comparator circuit.
[SuGmarY of the Invention]
Accordingly, an obiect of Present invention is to provide a hYsteresis comparator circuit which is caPable of eliminating an undesired pulse wldth extension occurring due to a hYsteresis and with which chatterings hardlY take Place.
Another object of the Present invention is to provide a hYsteresis comparator circuit which does not require an additional special circuit therebY saving the substrate accommodating space and manufacturing cost.
According to a first aspect of the Present invention, there is Provided a hYsteresis comParator circuit comPrising an inPut imPedance element connected to a non-inverted inPut terminal of a comParator, and a feedback imPedance element connected between an output terminal of the comparator and the non-inverted inPut terminal. The input imPedancè element and feedback impedance element are so set as to constitute a differentiation circuit when seen from the outPut terminal side of the comParator.
~ ith the above arrangement, when a si~nal to be detected is inputted to an inverted inPut terminal of the compara,tor and a reference signal is inPutted via the inPut i-Pedance ele-ent to the non-inverted input terminal of the comParator, if the voltage at the inverted inPut terminal of the comparator exceeds the reference signal; i.e. the voltage at the non-inverted input terminal of the comparator, at the risetime of the voltage at the inverted inPut terminal of the comParator, the outPUt voltase of the comparator turns from a HlGH-level to a LOW-level.
Then, this LOW-level voltage is aPPlied to the non-inverted input terminal of the comparator via the feedback impedance element.
In this instance. as the feedback impedance element and the inPut impedance element constitute a differentiation circuit whe seen from the outPut terminal side of the comparator, the voltage at the non-inverted inPut terminal of the comparator immediately droPs below the voltage level of the reference signal to cause a hysteresis, and no chattering Phenomenon due to noises takes place. Thereafter, the voltage of the non-inverted inPut terminal of the comParator continuouslY
increases with a gradient determined by the characteristics of this differentiation circuit; i.e. the time constant determined bY the feedback impedance element and the inPUt impedance element, until it reaches the voltage level oi the reference sisnal, so that the hYsteresis is finallY eliminated.
Furthermore, at its falltime, iS the volta8e of the target signal decreases down below the volta8e of the reference signal, the output voltage of the comParator turns from a LOW-level to a HlGH-level. Then. this HlGH-level voltage is suPPlied via the feedback impedance element to the non-inverted inPut terminal of the comParator.
_ In this case, the voltage at the non~-inverted input terminal of the comParator immediatelY increases above the voltage level of the reference signal to cause a hYsteresis and no chattering phenomenon due to noises takes Place. After that, ~ the voltage of the non-inverted input terminal of the comparator continuously decreases with a gradient determined by the characteristics of this differentiation circuit; i.e. the time constant determined by the feedback imPedance element and the in put imPedance element, until it reaches the voltage level of the reference signal, so that the hYsteresis is finally eliminated.
As is exPlained in the ioregoing descriPtion. in accordance with the hYsteresis comparator circuit of the present invention.
the voltage of the non-inverted inPut terminal of the comparator largelY varies immediatelY after the output voltage of the comparator has changed from a HlGH-level to a LOW-level and also immediately after the output voltage of the comparator has subsequently changed irom a L~W-level to a HlGH-level so that the comParator circuit may possess an appropriate hYsteresis effective for suppressing the chattering Phenomenon.
~ o ~
Furtheroore, the volta~e level before the output voltsse of the ComParatOr changes from a HlGH-level to a LO~-level can be equalized to the voltage level before the output voltage of the comparator subsequentlY changes from a LO~-level to a HlGH-level, so that it becomes possible to eliminate an undesirable extension of thepulse width resulting from the hYsteresis.
_ Moreover, all that is required ior arran8ing this circuit is only the connection of the ieedback impedance element and the inPut ImPedance element so as to constitute the differentiation circuit when seen from the output terminal side of the comParator. AccordinglY, it is not necessarY to Provide a particular circuit seParatelY which results in saving the substrate accomEodating space and ~anuiacturing cost.
According to a second aspect of the Present invention there is Provided a hYsteresis comParator circuit which comprises a ieedback imPedance ele~ent and an inPut impedance elèment wherein at least either one of these two elements is constituted bY a Parallel circuit composed oi iirst and second series circuits of which the first series circuit includes a first imPedance element and a iirst unilateral conductive element that allows current to flow in one direction only, and the second serial circuit includes a second imPedance element and a second unilateral conductive element.that allows current to flow in the other direction onlY.
. In this case, the impedance value of unilateral current ~'~8~f-~
path passing through the first series circuit including the first unilateral conductive element and the first impedance element is made different from the illPedance value of the other current path Passing through the second series circuit including the second unilateral conductive element and the second impedance element, in at least either of the feedback impedance element or the inPut impedance -element.
With this arrangement, it becomes Possible to intentionallY
varY the width of a hYsteresis and the hYsteresis attenuation characteristics of the circuit between the risetime and the fall tiee of the target signal.
Nameiy, the hYsteresis width and hYsteresis attenuation characteristics obtained when the output voltage of the comparator turns from a HlGH-level to a LOW-level at the risetime of the target siYnal can be made different from those obtained when the output voltage of the comParator subsequently turns from a LOW-level to a HlGH-level at the falltime of the target signal.
Accordingly, the hysteresis comparator circuit in accordance with the second asPect of the Present invention, a wide varietY of use can be exPected. For example, where a pluralitY of target signals to be detected are continuouslY
inPutted, all the remaining signals that follow the first target signal can be intentionallY ignored. That is, a masking is effectivelY carried out in this hYsteresis comparator circuit x ~
embodying the Present invention.
[Brief DescriPtion of the Drawin8s]
Fig. 1 is a circuit diagram showing a concrete configuration of a hYsteresis comparator circuit according to a first embodiment of the Present invention;
Fig. 2 is a circuit dia8ram showing a concrete example of the hYsteresis comParator circuit shown in Fig. 1;
Fi8. 3 is a waveform diagram showinB an operation of the hYsteresis comparator circuit shown in Fig. 2;
Fig. 4 is a circuit diagram showing another examPle oS the hYsteresis comParator circuit shown in Fig. l;
Fig. 5 is a circuit diagram showing a hYsteresis comParator circuit configuration according to a second e~bodi-ent of the present invention;
Fig. 6 is a waveiorm diagram showing an oPeration of the hYsteresis comParator circuit shown in Fig. 5;
Fig. 7 is a waveform diagram also showing an operation of the hYsteresis comParator circuit shown in Fig. 5;
Fig. 8 is a circuit diagram showing a hYsteresis comparator circuit configuration according to a third embodiment of the present invention;
Fig. 9 is a circuit diagram showing an examPle of a conventional hYsteresis comparator circuit configuration; and Fig. 10 is a waveform diagram showing an oPeration of the hysteresis comparator circuit shown in Fig. 9.
Fig. Il is a circuit diagram showing a hYsteresi.s comparator circuit configuration according to a fourth embodiment of the Present invention; and Fig. 12 is a waveiorm diagram showing an oPeration of the hYsteresis comparator circuit shown in Fig. 11.
~Detailed DescriPtion of Preferred Embodiments]
The first embodiment of the present invention will now be described by referring to Figs. 1 through 4. As shown in Fig. 1, an inPut impedance element Z~ is connected to a non-inverted inPut terminal T12 of a comParator CP and a feedback imPedance element Z2 is interposed between an oUtPUt terminal T13 and the non-inverted input terminal T12 of the comParatOr CP, therebY
Sorming a hYsteresis comparator circuit.
The feedback impedance element Z2 and the input imPedance element Z1 are connected with each other to cooPerativelY
constitute a difierential circuit DF when seen irom the outPut terminal T~3 side of the comParator CP.
In this hYsteresis comparator circuit. a signal V8 to be detected is supplied from an inPut terminal TM~ to an inverted input terminal T~1 of the comparator CP as a voltage V_. This signal V8 is represented by, for examPle. a Particle detecting signal obtained from a particle measurement apparatus such as a flow cYtometer or the like.
Further, a reference signal VR to be compared to the signal V8 is supPlied from an input terminal TM2 via an input impedance element Z, to a non-inverted inPUt terminal T12 as a voltage V+
In addition, an output voltage VO at an outPut terminal T~3 of the comparator CP is fed back to the non-inverted input terminal T12 throu8h a feedback imPedance element Z2 _ Then, the outPut voltage VO apPearing at the outPut terminal T~ of the comParator CP is taken out from an output terminal TM3 In the case of the above hYsteresis comparator circuit, ~ when the target signal V~ is inPutted to the inverte~d input terminal T11 of the comParatOr CP and the reference signal VR jS
inPutted to the non-inverted input terminal T12 of the coaparator CP through the inPut imPedance element Z" and if the signal V~; i e the voltage V_ of the inverted inPUt terminal T~, of the comparator CP, exceeds the reference signal VR; i e the voltage V+ of the non-inverted input terminal Tl2 of the comparator CP at its risetime, the output voltage VO of the comparator CP turns from a HlGH-level to a LOW-level Then, this LOW-level voltage is suPPlied via the feedback impedance element Z2 to the non-inverted inPut terminal T12 of the comparator CP
In this case, as the feedback impedance element Z2 and the inPut impedance element Z~ constitute a differentiation circuit DF when seen from the output terminal T~3 side of the comparator CP,the voltage Y+ of the non-inverted input terminal T,2 of the ~08~
comparator CP immediatelY droPs belo~l the voltage level of the reference signal VR to generate a hYsteresis so that no chattering takes Place. After that, the voltase V+ of the non-inverted inPut terminal T12 of the comParator CP
continuously increases with a 8radient determined bY the characteristics of this differentiation circuit DF; i.e. a time constant determined by the feedback impedance ele-ent Z2 and the inPut imPedance element Z~, until it reaches the voltage level oi the reference sisnal VR. Thereiore, the hYsteresis is iinally eliminated.
Furthermore, at the falItime of the tarset sisnal Vs, if the volta8e of the detected sisnal Vs decreases down below the voltage of the reference signal VR~ an outPut voltase VO of the comParator CP turns from a LOW-level to a HlGH-level. Then, this HlGH-level voltage is suPPlied vin the feedback impedance element Z2 to the-non-inverted inPUt terminal T12 of the comparator CP.
In this case, the voltase V~ of the non-inverted inPut terminal T12 of the comparator CP immediatelY increases above the voltage level of the reference signal YR to cause a hYsteresis. Thus, the chattering Phenomenon due to noises is surely suPpressed.
Thereafter, the voltage ~ oi the non-inverted input terminal T12 of the comParator CP continuouslY decreases with a sradient determined by the characteristics of this difierentiation circuit DF; i.e. the time constant determined bY
the feedback impedance element Z2 and the inPUt impedance eleuent Z1, until it reaches the voltage level of the reSerence sisnal VR. Therefore, the hYsteresis is finally eliminated.
As has been explained in the foregoing description, in accordance ~ith this hYsteresis comParator circuit of the present invention, the voltage V+ of the~non-inverted input ter~inal T12 of the comparator CP is largelY varied immediatelY
aiter the output voltage VO of the comparator CP has chan8ed irom a HlGH-level to a LOW-level and also immediatelY after the output voltage VO of the comparator CP has subsequently chansed from a LOW-level to a HlGH-level. Hence, it becomes Possible for the comparator CP to Possess an aPpropriate hYsteresis characteristic effective for suppressing the chattering phenomenon.
Furthersore, the voltage level of the target signal Vs before the outPut voltage VO of the comParator CP changes from a HlGH-level to a LOW-level is equalized with the voltage level of the target signal Vs before the output voltage VO of the comparator CP subsequently changes from a LOW-level to a HIGH-level. Therefore, it becomes possible to eliminate an undesirable extension of the pulse width that is inevitably derived from the hYsteresis. s Moreover, all that required for arranging this circuit is only to connect the feedback impedance element Z2 and the input ~ag~oll~
imPedance element Zl with each other to cooPerativelY constitute the differential circuit DF when seen from the same sid-e as the outPut terminal T~3 of the co~parator CP. AccordinglY, there is no requirement for additionally providing a sPecial circuit, which results in the advantage of reducing the substrate accommodating sPace and the manuiacturing cost.
_ Next, Fig. 2 shows a specific circui~t examPle wherein a resistor is used as the input i~Pedance element Z1 and a caPacitor is used as the feedback impedance element Z2.
In Fig. 2. an inPut resiætor Rl1 IS one that is used as the input imPedance element Z1 and a feedback capacitor CF~ is one that is used as the ieedbàck loPedance element Z2. These inPut resistance RI1 and the ieedback capacitor CF1 are connected with each other to cooPerativelY constitute a difierentiation circuit when seen from the outPut terninal T13 side of the conparator CP.
Other co-Ponents of this circuit are the same as those of the above-described circuit shown in Fig. l.
Fig. 3 is a waveform diagram showing an operation of the hYsteresis comparator circuit shown in Fig. 2. Fig. 3(a) shows the target signal Vs to be detected , the voltage V_ (= Vs) aPPlied to the inverted inPut terminal T1~ of the comparator CP, and the voltage V+ apPlied to the non-inverted input terminal T12 of the comParator CP. (In the initial condition, the volta~e V+ aPPlied to the non-inverted inPUt terminal T~2 of the comParator CP is equal to the reference signal V~).
9~
Further, in Fis. 3(b) there is shown the outPut voltage YO
appearing at the output teroinal T13 of the comparator-CP.
Though the operation of thi 8 circuit has been previouslY
described with reference to Fig. 1, the same operation will be described again Dith reference to Fig. 3.
In the hYsteresis comParator circuit shown in Fig. 2, when the target signal V8 is s-aller than the reference si~nal VR.
the outPut signal VO of the comparator CP is at HlGH-level.
HoDever, if the signal V8 exceeds the reference signal VR at its rlsetioe, the output signal VO of the cooparator CP turns from a HlGH-level to a LOW-level.
Accordin81Y, the volta8e V+ of the non-inverted inPut teroinal T12 of the comparator CP imoediatelY changes (drops) bY
the amount of variation of the outPut voltage VO. In other words, the voltage V+ of the non-inverted inPut terminal T~2 f the comparator CP changes by an amount corresponding to the difference between the output voltage VO at a HlGH-level and the output voltage VO at a LOW-level. However, the voltage V+ once dropped continuouslY increases with a time constant of CF1 Rl1 until it returns to the voltage level of the reference signal VR.
Furthermore, at the falItime of the target signal Vs, the output voltage VO of the comparator CP turns from a LOW-level to a HlGH-level when the signal ~s becomes smaller than the reference signal VR.
AccordinglY, the voltage V+ of the non-inverted input _ 15 _ ~9~901~
ter~inal T12 of the comparator CP immediatelY changes (increases) by an amount corresponding to the amount of variation of the outPUt voltage VO. In other words, the voltage V+ of the non-inverted input terminal T~2 of the comparator CP changes bY an a~ount corresPonding to the difference between the output voltage VO at a HlGH-level and the outPut voltage VO at a LO~-level. However, the voltage V~ once incr-eased continuouslY
decreases with the time constant of C~ RI1 until it returns to the voltage level of the reference signal VR.
Consequently, the coDparator CP can compare the target signal V~ with the same reference signal VR at both the risetime and falltime of the signal Y~. In other words, it becomes possible for the comparator CP to temporarilY possess the hYsteresis necessary for suppressing the chatterin~ phenomenon only for a limited period of time, immediatelY after the output voltage VO of the comparator CP has turned from a HlGH-level to a LOW-level or vice versa.
Accordingly, an undesirable extension of the pulse width experienced in a conventional hYsteresis ComParator circuit no longer takes Place. Thus it becomes possible to accuratelY
detect a Pulse width, and the chattering phenomenon can of course be effectivelY supPressed.
Furthermore, the circuit'-of the present invention uses a capacitor instead of a resistor as serving a conventional feedback impedance element so that it is not neCessarY to ~ a ~
provide a particular circuit seParatelY therebY savin8 the substrate accommodating space and manufacturing cost..
Moreover, it is Possible to varY the time required for allowing the voltage V+ at the non-inverted input terninal T12 of the comParator C~ to return to the voltage level of the reference voltage VR by varying the time constant.
_ Next, Fig. 4 shows a concrete circuit exa-Ple wherein a resistor is used as the inPut ImPedance element Z~ and a series circuit of a capacitor and a resistor is used as the feedback i-pedance element Z2 .
~ In Fig. 4, the inPut resistor Rl1 is one that is used as the input impedance element Z1 and a series circuit of a feedback capacitor CF1 and a feedback resistor RF2 is one that is used asthe feedback imPedance element Z2. The feedback cspacitor CF1, feedback resistor RF2. and inPut resistor Rl1 are connected withone another so as to constitute a differential circuit when seenfrom the output terminal T1g side of the comParator CP. Other ComPOnents of this circuit are the same as those shown in Fi~. 2.
BY using such a serial circuit of the feedback capacitor CF1 and the feedback resistor RF2 as the feedback impedance element Z2. it becomes Possible to vary the width of the hYsteresis generating immediatelY after the output voltage VO of the comparator CP has changed from a HlGH-level to a LOW-level or vice versa. The width of this hYsteresis can be properlY
~08901~
deternined dependin~ on the kind of signal to be handled Moreover, the width of the hYsteresis can also ~e chan~ed in the saue uanner when the non-inverted inPut teruinal T12 of the cosparator CP is grounded throu8h a resistor Other ~eatures are the saoe as those of the hYsteresis couparator circuit shown in Fi~ 2 _ A second eubodioent of the Present invention will be explained in detail with reference to Figs 5 throuRh 7 As shown In Fig 5, this hYsteresis coeParator circuit }s couPosed of the inPut resistor R~l servin8 as the input iapedance ele-ent Zl of Fi8. 1, a feedback capacitor C~l, feedback resistor RF5.
RF4 and diodes D~, D2 serving as the feedback inpedance eleuent Z2. with the re-ainin8 Portion belns the saoe as that in Fi8. 1.
That is, the feedback iuPedance eleuent is constituted such that a series circuit ot the feedback resistor RF3 (an i-pedance elenent) and the diode D, (a first unilateral conductive elesent) is connected Parallel to a series circuit of the feedback resistor RF4 (a second iuPedance elenent) and the diode D2 (a second unilateral current conductive ele~ent) and the feedback capacitor C~l is connected in series with the parallel circuit In this case, the values for the feedback resistors are set differentlY
With this arrangeoent, w~en the outPut voltage VO of the couparator CP chanses frou a HlGH-level to a LOW-level at the risetiue of the target si~nal V~, the diode D, is turned on and .
the diode D2 is turned off so that the width of hYsteresis becomes RIl/(RIl ~ RF3)- Vo and the time constant of hY-steresis attenuation beco-es Cpl/(RIl + Rp~-Furthermore when the outPUt volta8e YO of the comparatorCP turns from a LOW-level to a HlGH-level at the falltiue of the target si8nal VB~ the diode D1 is turned off and the other diode D2 is turned on so that the width of hYst~eresis becomes R~l/(RII ~ Rp4) Vo and the time constant of hYsteresis attenuation becomes Cpl/(RI~ ~ Rp4).
With this arrangement, it becomes Possible to intentionallY varY the hYsteresis characteristics at the risetime and the iallti-e of the target signal V8 Namely, the hYsteresis width and hYsteresls attenuation characteristics at the time when the outPUt voltage VO of the comparator CP turns from a HlGH-level to a LOW-level in the risetime of the target si8nal V8 can be differentiated from those when the outPut voltage VO of the comparator CP
subsequently turns from a LOW-level to a HlGH-level at the falltime of the target si8nal V8.
For example, when more than two target signals V5 to be detected are inPutted in sequence, it is Possible to ignore (mask) those following the first signal by intentionally increasing the time constant ~
Figs 6 and 7 are waveform diagrams showin8 an oPeration of the hYsteresis comparator circuit of Fig 5 wherein Figs 6(a) ~ ' ' ' ' " :' ' ~:
and 7(a) corresPond to Fig. 3(a), ancl 3(b) resPectivelY.
Fis. 6 shows a waveform when the time elapsed from the generation of a hYsteresis to the termination thereof at the risetime of a target signal VB jS matle sufficiently shorter than the Pulse width oi an analog Pulse signal as the target signal VB and the time elaPsed from the generation of a hYsteresis to the termination thereof at the falltime o~f the signal V~ is made longer than that at the risetime of the signal.
BY setting such a characteristic, even if an analog Pulse signal inPutted as the target signal V8 has irregulaties at the trailing-edge thereof, it becomes possible to accurately detect onlY the width of the first wave of the signal bY ignoring its succeeding waves.
Fig. 7 shows a wavefor- when the time elapsed from the generation of a hYsteresis to the termination thereof at the risetlme of the target signal VB is sufficientlY longer than the pulse width of analog pulse signal as the target signal V~ and the tlue elaPsed from the generation of a hysteresis to the termination thereof at the falltime of the signal is made shorter than that at the risetime thereof.
BY setting such a characteristic, even if analog pulse signals are inPutted in sequence as the signal V~, it becomes possible to ignore all the Pulse signals following the first one.
Therefore, it becomes easY to Perform a Pulse number counting operation bY excluding the ignored pulse signals.
, ' -~8~
The renaining portion is the saoe as that of the hysteresis comparator circuit of Fig. 2.
BY the waY, a similar oPeration can be Performed even if the inPut resistor R11 and the Parallel circuit consisting of the feedback resistors RF3~ RF4 and diodes D1, D2 are exchangd with each other in the circuit disclosed in Fig. 5.
_ A third embodiment of the present in~vention will be explained with reference to Fi8. 8.
As shown in Fig. 8, the hYsteresis comparator circuit according to this embodiment uses a Parallel circuit consisting of a first series circuit including an input resist-`or RI2 and a diode D3 and a second series circuit including an inPut resistor Rlg and a diode D4, instead of the input resistor Rl1 of Fig. 5.
The resaining Portion is the same as those oi Fig. 5.
In this case, the resistance values of the inPut resistors RI2. RI~ and the feedback resistor RF3. RF4 are so set as to satisfY a relationshiP of RI2 : RI9 ~ Rl9 : RI4.
In the case of the circuit configuration of Fig. 5, the hYsteresis width and time constant change together, but in the Fig. 8 embodiment, it becomes Possible to varY onlY the tine constant with the hYsteresis width kept unchanged.
BY the waY, it is possible to set the ratio between the values oi the inPut resistor Rl2. RI3 and the values of the feedback resistors RF3 and RF4 SO as to satisfy the equation of RI2 + RF3 = RI3 + RF4. In that case, it is Possible to vary ~9~14 onlY the hYsteresis width while keePing the time constant unchanged Now, a hYsteresis comparator circuit as a fourth embodiment of the Present invention will be exPlained by referring to Fig 11 and 12 In the circuit shown In Fig Il, the output voltage VO of the comParator CP is at a High-level when the signal V, to be detected (target signal) is smaller than the reference voltage level V+1 However, as shown in Fig 12, when the tar8et signal V~ exceeds the reference voltage level V+, at the rise time of the signal, the outPut voltage VO of the comParator CP changes from a Hi~h-level to a Low-level AccordinglY, the voltage Y+ at the non-inverted input terminal T12 of the comParator CP imaediatelY changes (decreases) from the voltage level V+l by an amount equivalent to the amount of variation of the output voltage VO That is, the voltage V+
at the non-inverted inPut ter'minal T12 of the comparator CP
changes bY an amount corresponding to the difference between the High-level outPut volta~e VO and Low-level output voltage VO
However, the voltage V+ thus decreased once increases with a time constant CF1.(R11/RF1) to finally reach the reference voltage level V+2 On the other hand, at the fall time of the target signal V~, when the target signal V~ is smaller than the reference voltage level V+2, the outPut voltage VO of the comParator CP changes from a Low-level to a High-level ~89~1~
Consequently, the voltage V+ at the non-inverted input terminal T1 2 also changes (increases) immediatelY from the voltage level V+2 by the amount oi variation of the outPut voltage. That is, the voltage V+ changes by an amount corresponding to the difference between the high-level voltage VO and the low-level voltage Vo. However, the voltage V, thus increased once decreases with the time constant CF1.(RI~/RFl) to finallY resch the reference voltage level V+,.
Accordingly, it is possible for the circuit to have a large hYsteresis onlY for a Poriod requlred to Prevent chatterings immediatelY after the inversion of the outPut voltage VO of the co~lParator CP.
As a result, the generation of chatterings due to noises can be controlled.
In addition, since the circuit of this embodiment does not require the provision oi any'separate particular circuit excePt the oere addition of a caPacitor to be connected to the resistor so as to serve as a conventional ieedback imPedance eleoent, there is no increase In the substrate receiving space or in the cost of manufacturing the circuit.
Moreover, by changing the tice constant, it is possible to varY the tlme required for the voltage V+ at the non-inverted inPut terminal Tl2 of the co~arator CP to reach the reference voltage levels V+~ and V+2.
Claims (7)
1 A hysteresis comparator circuit comprising a comparator, an input impedance element connected to a non-inverted input terminal of said comparator and a feedback impedance element connected between an output terminal of said comparator and said non-inverted input terminal, and wherein said feedback impedance element and said input impedance element are connected with each other to cooperatively constitute a differentiation circuit when seen from the output terminal side of said comparator.
2. A hysteresis comparator circuit in accordance with claim 1 in which said input impedance element is a resistor and said feedback impedance element is a capacitor.
3. A hysteresis comparator circuit in accordance with claim 1 in which said input impedance element is a resistor and said feedback impedance element is a series circuit of a capacitor and a resistor.
4. A hysteresis comparator circuit in accordance with claim 1 in which said input impedance element is a resistor and said feedback impedance element is a Parallel circuit of a capacitor and a resistor.
5. A hysteresis comparator circuit in accordance with claim 1 in which at least either of said feedback impedance element or said input impedance element comprises a parallel circuit consisted of a first series circuit of a first unilateral conductive element allowing current to flop in one direction only and a first impedance element and a second series circuit of a second unilateral conductive element allowing current to flow only in a direction opposite the direction of the current flowing through said first unilateral conductive element and a second impedance element, and in which the impedance value of a unilateral current path passing through said first series circuit is made different from the impedance value of a unilateral current path passing through said second series circuit.
6. A hysteresis comparator circuit in accordance with claim 5 in which said feedback impedance element comprises a capacitor connected in said parallel circuit.
7. A hysteresis comparator circuit in accordance with claim 4 or 5 in which said first and second unilateral conductive elements are diodes, respectively, and said first and second impedance elements are resistors, respectively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2639992 | 1992-02-13 | ||
| JP026399/1992 | 1992-02-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2089014A1 true CA2089014A1 (en) | 1993-08-14 |
Family
ID=12192484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2089014 Abandoned CA2089014A1 (en) | 1992-02-13 | 1993-02-08 | Hysteresis comparator circuit |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0558971A1 (en) |
| JP (1) | JPH05291899A (en) |
| AU (1) | AU3303493A (en) |
| CA (1) | CA2089014A1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2339982A (en) * | 1998-07-17 | 2000-02-09 | Ford Motor Co | Crankshaft angle signal thresholder with asymmetric hysteresis |
| US8519744B2 (en) * | 2011-06-28 | 2013-08-27 | General Electric Company | Method of utilizing dual comparators to facilitate a precision signal rectification and timing system without signal feedback |
| JP6399761B2 (en) * | 2014-02-07 | 2018-10-03 | キヤノン株式会社 | Power supply device and image forming apparatus |
| JP6935280B2 (en) * | 2017-09-13 | 2021-09-15 | ニッタン株式会社 | Signal detection circuit |
| CN108736862A (en) * | 2018-07-02 | 2018-11-02 | 华北电力大学 | A kind of quick trigger circuit for zero-acrross ing moment under positive-negative polarity lightning impulse |
| JP2021040257A (en) * | 2019-09-04 | 2021-03-11 | ローム株式会社 | Voltage comparison circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58188923A (en) * | 1982-04-28 | 1983-11-04 | Nippon Denso Co Ltd | Period signal detecting circuit |
-
1993
- 1993-02-04 JP JP5017163A patent/JPH05291899A/en active Pending
- 1993-02-08 CA CA 2089014 patent/CA2089014A1/en not_active Abandoned
- 1993-02-11 EP EP93102134A patent/EP0558971A1/en not_active Withdrawn
- 1993-02-12 AU AU33034/93A patent/AU3303493A/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| AU3303493A (en) | 1993-08-19 |
| JPH05291899A (en) | 1993-11-05 |
| EP0558971A1 (en) | 1993-09-08 |
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| Date | Code | Title | Description |
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| FZDE | Dead |