CA2086386A1 - Interface chip for a voice processing system - Google Patents

Interface chip for a voice processing system

Info

Publication number
CA2086386A1
CA2086386A1 CA 2086386 CA2086386A CA2086386A1 CA 2086386 A1 CA2086386 A1 CA 2086386A1 CA 2086386 CA2086386 CA 2086386 CA 2086386 A CA2086386 A CA 2086386A CA 2086386 A1 CA2086386 A1 CA 2086386A1
Authority
CA
Canada
Prior art keywords
communication
processing system
voice processing
chip
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2086386
Other languages
French (fr)
Other versions
CA2086386C (en
Inventor
Daniel F. Daly
John J. Dwyer
Thomas C. Grandy
Mark N. Harris
Salvatore J. Morlando
Mark Sekas
Shamla V. Sharma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dictaphone Corp
Original Assignee
Dictaphone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dictaphone Corp filed Critical Dictaphone Corp
Publication of CA2086386A1 publication Critical patent/CA2086386A1/en
Application granted granted Critical
Publication of CA2086386C publication Critical patent/CA2086386C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

An interface chip is capable of receiving requests from two processors and coordinating the flow of the data therebetween. The chip functions as a dual port controller for interaction of associated RAMs and processors of a voice processing system. A plurality of interfaces of the instant invention can be placed in communication with a host computer (PC) of a voice processing system that determines the priority of requests that are received from units of the system. The interface circuits are in communication with the host computer for the purpose of accepting requests in sequence and outputting data over a bus. The host computer is in communication with a RAM interface of each chip that interfaces local peripheral board processor through a dual port RAM which resides on the peripheral board. The interface chip contains the circuitry that creates communication with the resident RAM.
CA 2086386 1991-12-31 1992-12-29 Interface chip for a voice processing system Expired - Fee Related CA2086386C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81651691A 1991-12-31 1991-12-31
US816,516 1991-12-31

Publications (2)

Publication Number Publication Date
CA2086386A1 true CA2086386A1 (en) 1993-07-01
CA2086386C CA2086386C (en) 1997-04-29

Family

ID=25220854

Family Applications (1)

Application Number Title Priority Date Filing Date
CA 2086386 Expired - Fee Related CA2086386C (en) 1991-12-31 1992-12-29 Interface chip for a voice processing system

Country Status (2)

Country Link
CA (1) CA2086386C (en)
GB (1) GB2263047B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05265883A (en) * 1992-03-19 1993-10-15 Fujitsu Ltd Dual port ram interface system
JPH07121181A (en) * 1993-10-27 1995-05-12 Sony Corp Sound information processor
GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
GB2343596A (en) 1998-11-06 2000-05-10 Ibm VLSI chip macro interface

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4620118A (en) * 1982-10-01 1986-10-28 At&T Bell Laboratories Dual port access circuit with automatic asynchronous contention resolving capability
US4586133A (en) * 1983-04-05 1986-04-29 Burroughs Corporation Multilevel controller for a cache memory interface in a multiprocessing system
GB8430004D0 (en) * 1984-11-28 1985-01-09 Plessey Co Plc Microprocessor interface device
GB2228348A (en) * 1989-01-13 1990-08-22 Texas Instruments Ltd Memory interface integrated circuit
US5072420A (en) * 1989-03-16 1991-12-10 Western Digital Corporation FIFO control architecture and method for buffer memory access arbitration

Also Published As

Publication number Publication date
GB9227120D0 (en) 1993-02-24
CA2086386C (en) 1997-04-29
GB2263047B (en) 1996-06-26
GB2263047A (en) 1993-07-07

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed