CA2084039A1 - Systeme de controle de traitement de donnees en parallele - Google Patents

Systeme de controle de traitement de donnees en parallele

Info

Publication number
CA2084039A1
CA2084039A1 CA2084039A CA2084039A CA2084039A1 CA 2084039 A1 CA2084039 A1 CA 2084039A1 CA 2084039 A CA2084039 A CA 2084039A CA 2084039 A CA2084039 A CA 2084039A CA 2084039 A1 CA2084039 A1 CA 2084039A1
Authority
CA
Canada
Prior art keywords
computers
data processing
processing progress
pieces
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2084039A
Other languages
English (en)
Other versions
CA2084039C (fr
Inventor
Kenichi Ishizaka
Masayuki Katori
Masayuki Ikeda
Shigeru Nagasawa
Hiroshi Komatsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Kenichi Ishizaka
Masayuki Katori
Masayuki Ikeda
Shigeru Nagasawa
Hiroshi Komatsuda
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kenichi Ishizaka, Masayuki Katori, Masayuki Ikeda, Shigeru Nagasawa, Hiroshi Komatsuda, Fujitsu Limited filed Critical Kenichi Ishizaka
Publication of CA2084039A1 publication Critical patent/CA2084039A1/fr
Application granted granted Critical
Publication of CA2084039C publication Critical patent/CA2084039C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
CA002084039A 1991-11-28 1992-11-27 Systeme de controle de traitement de donnees en parallele Expired - Fee Related CA2084039C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3-314164 1991-11-28
JP3314164A JP2552784B2 (ja) 1991-11-28 1991-11-28 並列データ処理制御方式

Publications (2)

Publication Number Publication Date
CA2084039A1 true CA2084039A1 (fr) 1993-05-29
CA2084039C CA2084039C (fr) 1999-01-19

Family

ID=18050017

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002084039A Expired - Fee Related CA2084039C (fr) 1991-11-28 1992-11-27 Systeme de controle de traitement de donnees en parallele

Country Status (6)

Country Link
US (1) US5832261A (fr)
EP (1) EP0544535B1 (fr)
JP (1) JP2552784B2 (fr)
AU (1) AU649176B2 (fr)
CA (1) CA2084039C (fr)
DE (1) DE69228293T2 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3526492B2 (ja) * 1995-09-19 2004-05-17 富士通株式会社 並列処理システム
US7346664B2 (en) * 2003-04-24 2008-03-18 Neopath Networks, Inc. Transparent file migration using namespace replication
US8539081B2 (en) 2003-09-15 2013-09-17 Neopath Networks, Inc. Enabling proxy services using referral mechanisms
US8190741B2 (en) * 2004-04-23 2012-05-29 Neopath Networks, Inc. Customizing a namespace in a decentralized storage environment
US8195627B2 (en) * 2004-04-23 2012-06-05 Neopath Networks, Inc. Storage policy monitoring for a storage network
JP4372043B2 (ja) * 2005-05-12 2009-11-25 株式会社ソニー・コンピュータエンタテインメント コマンド実行制御装置、コマンド実行指示装置およびコマンド実行制御方法
US8832697B2 (en) * 2005-06-29 2014-09-09 Cisco Technology, Inc. Parallel filesystem traversal for transparent mirroring of directories and files
US8131689B2 (en) * 2005-09-30 2012-03-06 Panagiotis Tsirigotis Accumulating access frequency and file attributes for supporting policy based storage management
CN100571183C (zh) * 2007-08-24 2009-12-16 中国科学院计算技术研究所 一种基于胖树拓扑的屏障操作网络系统、装置及方法
US20100049307A1 (en) * 2008-08-25 2010-02-25 Aga Medical Corporation Stent graft having extended landing area and method for using the same
US8924984B2 (en) * 2009-06-26 2014-12-30 Microsoft Corporation Lock-free barrier with dynamic updating of participant count
JP5549574B2 (ja) * 2010-12-17 2014-07-16 富士通株式会社 並列計算機システム、同期装置、並列計算機システムの制御方法
WO2012127534A1 (fr) * 2011-03-23 2012-09-27 富士通株式会社 Procédé de synchronisation de barrières, dispositif de synchronisation de barrières et dispositif de traitement

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2530887C3 (de) * 1975-07-10 1980-07-17 Ibm Deutschland Gmbh, 7000 Stuttgart Steuereinrichtung zum Informationsaustausch
JPS5222406A (en) * 1975-08-13 1977-02-19 Nec Corp Control system among information processing units
US4412285A (en) * 1981-04-01 1983-10-25 Teradata Corporation Multiprocessor intercommunication system and method
US5047925A (en) * 1985-05-06 1991-09-10 Motorola, Inc. Logical ring in a virtual single machine
US4829422A (en) * 1987-04-02 1989-05-09 Stellar Computer, Inc. Control of multiple processors executing in parallel regions
US4914583A (en) * 1988-04-13 1990-04-03 Motorola, Inc. Method of indicating processes resident within a cell of a data processing system
US5127092A (en) * 1989-06-15 1992-06-30 North American Philips Corp. Apparatus and method for collective branching in a multiple instruction stream multiprocessor where any of the parallel processors is scheduled to evaluate the branching condition
IL93239A (en) * 1990-02-01 1993-03-15 Technion Res & Dev Foundation High flow-rate synchronizer/schedular apparatus for multiprocessors
DE69130630T2 (de) * 1990-09-14 1999-09-09 Hitachi Ltd Synchrones Verfahren und Gerät für Prozessoren
US5365228A (en) * 1991-03-29 1994-11-15 International Business Machines Corporation SYNC-NET- a barrier synchronization apparatus for multi-stage networks
JP3285629B2 (ja) * 1992-12-18 2002-05-27 富士通株式会社 同期処理方法及び同期処理装置

Also Published As

Publication number Publication date
EP0544535B1 (fr) 1999-01-27
CA2084039C (fr) 1999-01-19
EP0544535A2 (fr) 1993-06-02
US5832261A (en) 1998-11-03
JP2552784B2 (ja) 1996-11-13
JPH05151173A (ja) 1993-06-18
DE69228293T2 (de) 1999-06-02
DE69228293D1 (de) 1999-03-11
AU649176B2 (en) 1994-05-12
EP0544535A3 (fr) 1994-10-12
AU2970492A (en) 1993-07-08

Similar Documents

Publication Publication Date Title
AU3307489A (en) Object management facility for maintaining data in a computer system
EP0602909A3 (fr) Architecture SIMD avec un bus pour transférer des données entre les unités de traitement
AU589815B2 (en) Bus interface circuit for digital data processor
EP0652668A3 (fr) Système et procédé pour l'échange de fonctions de traitement de données d'ordinateurs.
CA2118995A1 (fr) Logique d'arbitrage pour ordinateur a bus multiples
AU5244393A (en) Generalized shared memory in a cluster architecture for a computer system
CA2080401A1 (fr) Ordinateur de reseau et methode de gestion de logiciels connexe
DE69636663D1 (de) System und Verfahren zur Zugriffsverteilung von Mehrfachspeichermatrixen zwischen Mehrfachwirtrechnersystemen
CA2084039A1 (fr) Systeme de controle de traitement de donnees en parallele
DE69409602T2 (de) Datenspeicherungssystemarchitektur
EP0330475A3 (fr) Système de commande de configuration
JPS6458013A (en) Method and data processing system for guaranteeing large area identification and management of data memory
AU1695288A (en) Computer system for advanced financial applications
EP0378427A3 (fr) Transmission de données à haute vitesse sur un bus de système ordinateur
EP0326671A3 (fr) Système à calculateur et méthode pour la surveillance des structures de données transitoires dans un système à calculateur
DE68927869D1 (de) Rechnersystem mit Hochgeschwindigkeitsdatenübertragungsfähigkeiten
EP0194415A3 (fr) Convertisseur de bus à bus
EP0083002A3 (fr) Système d'interruption pour unité de commande périphérique
EP0259050A3 (fr) Circuit d'accès de mémoire multicanal
AU570701B2 (en) Bypass for direct memory access channels
WO1995006286A3 (fr) Adaptateur hote integre a branchements multiples
EP0384621A3 (fr) Opérations de transfert de données entre deux bus asynchrones
CA2116826A1 (fr) Systeme de traitement de donnees utilisant un bus d'adresses et un bus de donnees asynchrones non multiplexes
CA2114374A1 (fr) Systeme de traitement d'informations pour realiser une multiplicite d'acces a un bus
EP0343343A3 (fr) Circuit de bloquage pour une mémoire tampon additionnelle

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed