CA2081156A1 - Process for digital information transmission - Google Patents

Process for digital information transmission

Info

Publication number
CA2081156A1
CA2081156A1 CA002081156A CA2081156A CA2081156A1 CA 2081156 A1 CA2081156 A1 CA 2081156A1 CA 002081156 A CA002081156 A CA 002081156A CA 2081156 A CA2081156 A CA 2081156A CA 2081156 A1 CA2081156 A1 CA 2081156A1
Authority
CA
Canada
Prior art keywords
signal
responsive
phase
decision circuit
information transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002081156A
Other languages
French (fr)
Inventor
Winfried Guba
Detlef Ernst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KE Kommunikations Elektronik GmbH and Co
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2081156A1 publication Critical patent/CA2081156A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0079Receiver details
    • H04L7/0083Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Abstract

ABSTRACT OF THE DISCLOSURE

A process for digital information transmission is indicated, in which the transmitted signals at the end of the transmission section are scanned by means of a clock recovery device (7) and are then processed further and also supplied to a decision circuit (10); to achieve an optimal scanning time, the input signal (ES) and the output signal (AS) of the decision circuit (10) are fed to a summing junction or an adding point; the differential values (D) of the two signals of the decision circuit (10) are fed from the adding point (11) to a controller (12), by means of which a mean value is continuously formed from the differential values and a couple phase modifier (8), coupled with the clock recovery device (7) and affecting the scanning time, undergoes a change in phase whenever the mean value in question is stabilized.

Description

2 ~
PROCESS FOR_DIGITAL INFORMATION TRANSMISSION

Technical Field The invention relates to a process for digital information transmission, in which the transmitted signals at the end of the transm:ission section are scanned by means of a clock recovery device and are then processed further and fed to a decision circuit.

Backqround of the Invention Signals for information transmission can be transmitted in a line-bound or wireless manner by means of a process of this type. For the line-bound transmission, cables with electrical or optical transmission paths are used. Wireless transmission proceeds, for e~ample, via radio relay or satellite radio. ~ variation in the transmission function of the transmission channel, for example, by a change in the length of a cable with metallic conductors, results not only in a change in the form of the signals received (pulses), but also a change in the temporal location of the particular pulse maximum. The overall pulse shaping is also affected by the temperature drift and the tolerances of the components used in the transmitter and receiver and of the cable. It is first time-dependent and subject to a certain scattering. In the case of synchronously operated transmission systems grouped in a cable, cyclic stationary interferences also occur, whose power fluctuates periodically with time. These interferences are described in the German Journal "FREQUENZ" 45 (1991) 1-2, pp~ 15-22. The ratio of useful signal to noise signal (signal-to-noise ratio) and, thus, the bit error ratio that can be achieved or the bridgeable distance of the signal transmission depends significantly on the influencing variables described. In all cases, it must be made certaîn that, in the scanning of the signals arriving at the receiver, a quantity that can be processed further and that does not exceed preset limits in the bit error ratio is obtained. In this case, the location of the scanning time is also of importance.
In known processes and circuits, the time of scanning for the clock phase are generally balanced ones in the manufacture of the particular assemblies. This means not only additional balancing work, but the influencing variables described above are not taken into consideration at all or only to an inadequate extent.
In the Journal "IEEE TRANSACTIONS ON
CO~MUNICATIONS", Vol. COM-35, No. 9, September 1987, pp.
961-968, aside -from the basic design of a circuit with scanning of the signals and feeding of these to a decision circuit, no measures are described by means of which the above-mentioned influencing variables are taken into consideration. This applies also to the process described in the German Journal "FREQUENZ", also mentioned above, by means of which the scanning values delivered by the scanner are processed further by the use of a linear and a decision fed-back equalizer and an off-norm value predictor with a relatively high circuit effort.

Disclosure of Invention The invention is based on the task of further developing the process described above in such a way that the maintenance of a reliable bit error ratio is ensured, and the range of transmission can be increased.
According to the invention, this problem is solved by the fact that:
- the input signal and the output signal of the decision circuit are fed to an adding point;

- the differential values of the two signals of the decision circuit are fed from the adding point to a controller;
- the mean value is continuously formed from the differential values in the controller; and - the phase of a phase modifier coupled with the clock recovery device and affecting the scanning time has its phase modified by the controller whenever the particular mean value is stabilized.
In addition to the clock recovery device, a phase modifier is therefore also used, which is controlled by a controller, for example, a microcontroller. The differential values between the signals at the input of the decision circuit on the one hand and those at the output of the decision circuit on the other hand are fed from the adding point to the controller. The controller forms a mean value from the differential values supplied to it--for e~ample, the quadratic mean value or the quantitative mean value--and, after stabilization of this value, adjusts the phase modifier by a preset amount. It is a determining factor for the time of an adjustment of the phase modifier that the system, after an adjustment, is always again in a steady state, so that a stable mean value of the differential values is obtained. The scanning time is thus continuously adapted to the circumstances in each case. As a result of the adaptive readjustment achieved in this way, the scanning is basically car~ied out at the optimal time. All changes during transmission are automatically taken into 3~ consideration. This also applies, in particular, for cyclic stationary crosstalk interferences. A balancing of the components used in the transmitter and receiver is not required. The bit error ratio can therefore be reduced, as compared with known processes, and the range of the signals to be transmitted via a cable can be correspondingly increased.

2 ~

The process according to the invention will now be explained with reference to the drawings as an embodiment.

Brief Description of the Drawinqs Fig. 1 is a schematic representation of a receiver of a digital transmission section.
Fig. 2 is a circuit for carrying out the process according to the invention.
Fig. 3 is a flow diagram for the course of the process.

Best Mode for CarrYing Out the Invention The process accordiny to the invention--as already mentioned previously--can be used both for line-bound information transmission via electrical or optical cables, and for wireless information transmission. The process is of particular importance in information transmission via electric cables, in which symmetrical twin wires are grouped together with metallic conductors.
The electrical cable will therefore be considered as a transmission medium below, as representative for the other transmission possibilities.
According to Fig. 1, the distorted digital signals superposed by interferences, pass from a cable 1 to a receiver 2, which contains a receive filter 3, a scanning device 4 and a detector 5. The more detailed design of the receiver 2 is shown in Fig. 2:
An analog-digital converter (A-D converter) 6, which contains the scanning device 4, is connected with the input E of the receiver 2 via the receive filter 3. A
phase modifier 8 connected with a clock recovery device 7, acts on the A-D converter 6. The detector 5, containing a filter unit 9 and a decision circuit 10 is 2 ~
connected to the A-D converter 6. By means of the decision circuit lo, the origina]ly-transmitted source signals are recovered from the processed signals supplied by the filter unit 9. The input signal ES and output signal AS of the decision circuit 10 are fed to an adding point 11. The output signal AS of the decision circuit 10 can also be applied to the filter unit 9 for evaluation. The differential signal D produced in the adding point 11 is applied to a controller 12 which, in turn, drives the phase modifier 8.
The circuit according to Fig. 2 operates as follows, in accordance with Fig. 3:
At the start of the transmission (start~, the phase modifier 8 is roughly adjusted. The corresponding value is stored in the controlier 12 as the starting value ~.
The digital signal emitted by the A-D converter 6, after scanning and processing by the filter unit ~, reaches the decision circuit 10. The input sianal ES and output signal AS of the decision circuit 10 are applied to the adding point 11, which forms the differential values D
from the two signals supplied. The differential values D
are fed to the controller 12, which forms a mean value from the differential values D. If the mean value is stable, the phase modifier ~ has its phase modified by an amount ~ in accordance with the stable mean value M(i) present at the time "i".
In this way, the scanning time undergoes a change of phase. The signals from the A-D converter 6 and filter unit 9 are changed. Additional differential values D are fed via the adding point 11 to the controller 12 which forms additional mean values from them. Each stable meah value M(i) leading to a change in the phase modifier 8 can be stored in the control unit 12.
The amount ~ by which the phase modifier 8 is displaced in each case, is to be adapted to the circumstances. It should not be too small, so that the adaptation of the optimal scanning time will not take too long. On the other hand, an excessively large value of is not meaningful, because, in that case, the adaptation will possibly fluctuate continuously and, under certain conditions, the optimum will not be reached. In a preferred embodiment, the amount ~ by which the phase modifier 8 is changed remains constant.
A meaningful value of ~ is, for example, one percent of the total clock phase. However, the amount of ~ can also be variable. This may be appropriate when larger deviations occur.
If, after an adjustment o-f the phase modifier 8, a new stable mean value M(i) is reached, then a further adjustment of the phase modifier 8 by the same amount as before can be carried out. For this purpose, the new stable mean value M(i) is first compared with the preceding stable mean value M(i-1) used for an adjustment of the phase modifier 8. If the new mean value M(i) is smaller than the preceding one, then the adjustment of the phase of the scanning time by the amount ~ was made in the right direction. The next adjustment by an amount of ~ will then take place in the same direction. If, on the other hand, the new mean value M~i) is larger than the preceding one, then the phase is adjusted in the opposite direction by the amount of ~. The time of adjustment can also be set by the controller 12~ An adjustment, in any case, will take place only when the system has reached a steady state and the mean value M(i) in question is thus stable. There is accordingly a pause between two adjustments of the scanning time.
Examples of units t~at can be used as phase modifiers 8 are digital delay circuits or delay units.
The filter unit 9 preferably consists of digital filters.
Filters of this type are described, for example, in the previously-ment oned German Journal "FREQUENZ"
The decision circuit 10 can be a component known in information transmission technology, such as, for example, a comparator or a logic circuit.

2~31~
The controller 12 can be an intelligent module with memories, for example, a microprocessor or microcontroller. However, gate arrays or other logic circuits can also be used.

Claims (8)

1. Process for digital information transmission, in which the transmitted signals at the end of the transmission section are scanned by means of a clock recovery device and are then processed further and fed to a decision circuit, characterized by the fact that - an input signal (ES) and an output signal (AS) of the decision circuit (lo) are fed to an adding point (11) i - differential values (D) of the two signals (ES, AS) of the decision circuit (10) are applied from the adding point (11) to a controller (12);
- a mean value is repeatedly formed from the differential values (D) in the controller (12); and - a phase modifier (8) coupled with the clock recovery device (7) and affecting the scanning time has its phase changed by the controller (12) whenever a particular mean value is stabilized.
2. Use of the process according to claim 1 for line-bound information transmission.
3. Use of the process according to claim 1 for information transmission with symmetric double wires with metallic conductors grouped together in an electric cable.
4. Process as in claim 1, characterized in that the phase modifier (8) has its phase changed by a constant amount (.DELTA..PHI.).
5. Use of the process according to claim 2 for line-bound information transmission.
6. Use of the process according to claim 2 for information transmission with symmetric double wires with metallic conductors grouped together in an electric cable.
7. Circuit arrangement for digital information transmission, comprising:
- a decision circuit (10), responsive to an input signal (ES), for providing an output signal (AS);
- an adding point (11), responsive to the input signal (ES) and the output signal (AS), for providing a differential signal (D);
- a controller (12), responsive to the differential signal (D), for providing an incremental phase modifying signal (.DELTA..PHI.);
- a phase modifier (8), responsive to a clock signal from a recovery device (7) and responsive to the incremental phase modifying signal (.DELTA..PHI.), for providing a clocked phase modifying signal; and - a scanning device (6,9) responsive to the phase modifying signal and to an information signal (E) for modifying a scanning time.
8. Circuit arrangement for digital information transmission in which, at the end of a transmission channel, a scanning device with a clock recovery device, a filter unit and a decision circuit are connected, wherein the circuit arrangement further comprises:
- an adding point (11), responsive to input (ES) and output (AS) signals of the decision circuit (10), for providing a differential signal (D); and wherein the arrangement further comprises:
- a controller (12), responsive to the differential signal (D), for providing an incremental phase modifying signal (.DELTA..PHI.);
- a phase modifier (8) connected with the clock recovery device, responsive to the incremental phase modifying signal for providing a clocked phase modifying signal; and - wherein the scanning device is responsive to the clocked phase modifying signal and to a filtered information signal from the filter unit for modifying a scanning time of the information signal.
CA002081156A 1991-11-06 1992-10-22 Process for digital information transmission Abandoned CA2081156A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4136474A DE4136474A1 (en) 1991-11-06 1991-11-06 DIGITAL MESSAGE TRANSMISSION METHOD
DEP4136474.0 1991-11-06

Publications (1)

Publication Number Publication Date
CA2081156A1 true CA2081156A1 (en) 1993-05-07

Family

ID=6444162

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002081156A Abandoned CA2081156A1 (en) 1991-11-06 1992-10-22 Process for digital information transmission

Country Status (8)

Country Link
EP (1) EP0540946B1 (en)
CN (1) CN1072301A (en)
AT (1) ATE162351T1 (en)
CA (1) CA2081156A1 (en)
DE (2) DE4136474A1 (en)
DK (1) DK0540946T3 (en)
ES (1) ES2111597T3 (en)
IL (1) IL103624A0 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2710219B1 (en) * 1993-09-13 1995-12-01 Trt Telecom Radio Electr Clock rhythm recovery device and modem comprising such a device.
AT413252B (en) * 1997-09-29 2005-12-15 Molisch Andreas F Dr METHOD FOR DETERMINING THE OPTIMAL SAMPLING TIME OF DIGITAL SIGNALING ACCORDING TO TRAINING RESULTS
DE10156112A1 (en) * 2001-11-16 2003-06-05 Philips Intellectual Property Receive circuit for receiving message signals
DE10156111A1 (en) * 2001-11-16 2003-06-05 Philips Intellectual Property Receive circuit for receiving message signals

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298255A (en) * 1986-06-18 1987-12-25 Fujitsu Ltd Identifying device

Also Published As

Publication number Publication date
DE4136474A1 (en) 1993-05-13
ATE162351T1 (en) 1998-01-15
DE59209132D1 (en) 1998-02-19
EP0540946B1 (en) 1998-01-14
EP0540946A3 (en) 1994-01-19
CN1072301A (en) 1993-05-19
DK0540946T3 (en) 1998-03-16
ES2111597T3 (en) 1998-03-16
EP0540946A2 (en) 1993-05-12
IL103624A0 (en) 1993-04-04

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Legal Events

Date Code Title Description
FZDE Discontinued