CA2072393A1 - Dispositif a retard variable - Google Patents

Dispositif a retard variable

Info

Publication number
CA2072393A1
CA2072393A1 CA2072393A CA2072393A CA2072393A1 CA 2072393 A1 CA2072393 A1 CA 2072393A1 CA 2072393 A CA2072393 A CA 2072393A CA 2072393 A CA2072393 A CA 2072393A CA 2072393 A1 CA2072393 A1 CA 2072393A1
Authority
CA
Canada
Prior art keywords
variable delay
circuit
variable
output signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2072393A
Other languages
English (en)
Other versions
CA2072393C (fr
Inventor
Fumiaki Honda
Nobukazu Hosoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Fumiaki Honda
Nobukazu Hosoya
Sanyo Electric Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fumiaki Honda, Nobukazu Hosoya, Sanyo Electric Co., Ltd. filed Critical Fumiaki Honda
Publication of CA2072393A1 publication Critical patent/CA2072393A1/fr
Application granted granted Critical
Publication of CA2072393C publication Critical patent/CA2072393C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks
    • H03H11/265—Time-delay networks with adjustable delay

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Picture Signal Circuits (AREA)
  • Networks Using Active Elements (AREA)
CA002072393A 1991-06-28 1992-06-26 Dispositif a retard variable Expired - Fee Related CA2072393C (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3-158983 1991-06-28
JP3158983A JP2675455B2 (ja) 1991-06-28 1991-06-28 可変遅延装置

Publications (2)

Publication Number Publication Date
CA2072393A1 true CA2072393A1 (fr) 1992-12-29
CA2072393C CA2072393C (fr) 2000-08-15

Family

ID=15683653

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002072393A Expired - Fee Related CA2072393C (fr) 1991-06-28 1992-06-26 Dispositif a retard variable

Country Status (6)

Country Link
US (1) US5285122A (fr)
EP (1) EP0520485B1 (fr)
JP (1) JP2675455B2 (fr)
KR (1) KR100270792B1 (fr)
CA (1) CA2072393C (fr)
DE (1) DE69210693T2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3688392B2 (ja) * 1996-05-31 2005-08-24 三菱電機株式会社 波形整形装置およびクロック供給装置
US8570881B2 (en) * 2006-03-28 2013-10-29 Advanced Micro Devices, Inc. Transmitter voltage and receiver time margining
US20070230646A1 (en) * 2006-03-28 2007-10-04 Talbot Gerald R Phase recovery from forward clock
US7817761B2 (en) * 2007-06-01 2010-10-19 Advanced Micro Devices, Inc. Test techniques for a delay-locked loop receiver interface
JP5012901B2 (ja) 2007-07-27 2012-08-29 富士通株式会社 可変遅延回路、可変遅延回路制御方法及び入出力回路

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4041533A (en) * 1974-09-28 1977-08-09 Matsushita Electric Industrial Co., Ltd. Delay circuitry
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
US4766559A (en) * 1986-03-31 1988-08-23 Tektronix Inc. Linearity correcting control circuit for tunable delay line
JPS6369314A (ja) * 1986-09-11 1988-03-29 Sony Corp Ｃｍｏｓ回路を用いた可変遅延装置
JP3077813B2 (ja) * 1990-05-11 2000-08-21 ソニー株式会社 プログラマブル遅延回路
FI913869A (fi) * 1990-09-27 1992-03-28 Philips Nv Anordning foer foerbaettring av signaloevergaongar.

Also Published As

Publication number Publication date
EP0520485A1 (fr) 1992-12-30
KR100270792B1 (ko) 2000-12-01
JPH0514150A (ja) 1993-01-22
KR930001399A (ko) 1993-01-16
JP2675455B2 (ja) 1997-11-12
DE69210693T2 (de) 1997-01-23
EP0520485B1 (fr) 1996-05-15
US5285122A (en) 1994-02-08
DE69210693D1 (de) 1996-06-20
CA2072393C (fr) 2000-08-15

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Legal Events

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