CA2071890A1 - Gate turnoff thyristor control circuit with shorted gate detection - Google Patents
Gate turnoff thyristor control circuit with shorted gate detectionInfo
- Publication number
- CA2071890A1 CA2071890A1 CA002071890A CA2071890A CA2071890A1 CA 2071890 A1 CA2071890 A1 CA 2071890A1 CA 002071890 A CA002071890 A CA 002071890A CA 2071890 A CA2071890 A CA 2071890A CA 2071890 A1 CA2071890 A1 CA 2071890A1
- Authority
- CA
- Canada
- Prior art keywords
- thyristor
- gate
- switch
- turnoff
- magnitude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/72—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
- H03K17/73—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
- H03K17/732—Measures for enabling turn-off
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
Landscapes
- Ignition Installations For Internal Combustion Engines (AREA)
- Power Conversion In General (AREA)
- Electrotherapy Devices (AREA)
Abstract
For responding to a shorted gate in a gate turnoff thyristor (71) the gate electrode of which is connected by means of a controllable switch (89) to a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, the controllable switch (89) being arranged to conduct negative gate current in response to a thyristor turnoff command, voltage comparing means (127) is coupled to the controllable switch for detecting when the switch is conducting negative gate current of relatively high magnitude, timing means (117) is active for a predetermined interval following the start of said thyristor turnoff command, and logic means (100) operative to cause the switch to stop conducting negative gate current if the voltage comparing means (127) detects high gate current at the end of such interval.
Description
wo 92/05~36 ;~ ~ 7 1 ~ ~ ~ PCl/U~91/05105 GATE TURN(:)FF THYRISTOR CO~OL CIRCUIT
WITH SHORTED GATE DE:TECT:[ON
~,~
Th~s i~ention relates generally to the corltrol of a high-speed, solid-state, unidirectional electric valve of the lsind ~at ~vill s~itch from a non-conduc~ng (off) state to a conduc$ing ~tate (on) in response to a relatiYely positive control voltage being applie~ to a gate electrode of the valve and that5 ~rill subsequently turn ofF in response to a negative control voltage being alternatively applied to the same gate, and it relates more particularly to means for detecting snd responding to a malfimctioning YalYe that fails to turn of~when rlegati~e control voltage is applied to its gate.
A valYe of the kind described is knowrl generally as a gate turno~f 10 (GTO) thyristor. It i~ a multi-layer semieonductor designed to freely conduct nforwasd" anode current (i.e., current flowing into its anode and out of it~ cathode~ when it~ gate electrode is trig~ered by a sultable turn-on or finng fiignal. A GTO thyn~tor i~ diætiI~guished fros~ a conventional ~ -thyri~tor by it~ ability to i~terrupt or blosl~ forwart anode cur~ent if a 15 ~oltag~ of` relativ~ly ~iegative polarity and appropriat~ magnitudle and - ::
duratio~ iu applied acros~ it~ gate-cathode junction. Such Yoltage i~
~egati~e in the sen&~ that the electrical pote~tial of ehe ~a~e is nega~ve with re~pect to the ca~ode. It cau~es current to flow in a reverse direetion in the t~ tor's gate. In ot~er word~, to tur~ off a GTO thyri~tor curreIlt i~ ~ ~
20 drained f~om the gate. Her~ina~er ~uch current is referred to a~ either "l~e~'d~e gat0 curr~nt" or t~e "turnof~ ~ignsl."
ormsl operat;ion, th~ anode curre~t-blocki~g or tur~o~ procesa of a GTO thyristor ~ ba iDitiated at a~y time ~without waitillg for a ~atural or ~ste~lly forced zean crosaillg of the a~l~e ~nt. D~ the tur~of~
25 proce~s the ~gat~e gat~ c~rrent rapiay ri~e~ to a bigh pe~ ~hat depend~
:: on t~ ma~tud~ of :anod~ cu~rent to ba ~terrupted and ~ sub~id~s a~
th~ thyri~tor reco~rera it~ ability to withstand of ~-atat~ anode voltage. On~ a .;:
. .:
~V ~ PCI/US91/05105 Wo 92/05636 f turnoff process is successfully completed, the resistance of the gate-cathode junction i3 very high and limit~ negative gate current to a tr~vial magnitude.
Occasionally a GTO thyristor malfimctions, failing to turn ofF af~er the S turnoff si~al is applied to its gate. Typically the failure mode is an internal short circl~t between the anode and the cathode of the thyr~stor, and this normally result~ in a shorted gat~. Means for detecting such a failure would be useful for both diagnostic and protective purposes. When a shorted gate occurs~ the gate-cathode resistance of the thyristor remains 10 low and ~ill not limit gate current efi~ectiYely. IJnder this abllormal condition an undesirably high magnitude of negati~lre gate current would continue to flow so long as the negative control voltage is applied to the gate, and the large amount of energ~ drained from the failed Gl~:) thyristor could senously oYerheat or otherwise damage the associated control 15 circuit.
mrnar~ of the Inventio~a A general objective of the present in~ention i~ to provide ;mproved means responsive to a failed GTO thyristor for protecting the control circuit 20 that provides the turnoff signal for the GTO th~stor. : .:
Another objectiYe i8 to provide, in a GTO thyristor control circuit, improved means for detectin~ a ~horted gate of the th~stor.
Yet another objective of the in~rention i8 the pro~nsion of an improved method of ~horted gate protection. ~ ~ -In carrying out the invention in one form, a high-speed, solid-state gate turnoff electnc valve i~ connected bet~eerl a ~ource of electrical power and an elect~ic load circuit. Thi8 vslve ha~ alternative on and o~ Btat~. In i~ on gl;at~ the valve ha~ negligible re~istanca alld fireely conduct~ load current, wherea~ in th3 of~ atate it has a resis1;anc~ of very high ohmic 30 valu~ that resembles arl open circuit and e~ecti~rely decouple~ the power source from the load circuit. Control means is coupled to the ga~ of the ~alve for prosiding alternati~re turQ o~ and ~ oi9~ aignals thereto. The turI~o~ BigI12311 i8 provided by means of a co~trollable ~witch con~ectet bet~een the gate ~nd 8 control voltage terminal ~a~ing a negative poterltial 3S with respect to the cathode potential of ~e ~ e. I~ D~ormal operatioII the co~trollable ~witch i~ caused ~ conduct "neg~ re" gate culTeIlt from the : , . ,;
. . .
~ ` . : ; ;. ,.~ , ., ; , ;
9 ~ pCr/~91/05105 thyri~tor gate to the control ~oltage te~inal in response to a valve turnof~
command and to not conduct ~uch current in response to a valve turn on command.
In one aspect of the invention, the valve control means includes fir6t S means coupled to the aforesaid controllable sw~tch and having alternati~e first and ~econd output states, the first output siate being true if negative gate current being conducted by the switch exce~eds a predetermined threshold magnitude that is less than the lowest peak magnitude needed to turn of ~ the valve but greater than the magnitude no,~nally conducted af~er 10 the ~ e i8 in its o~tate, and the secont output 8tat~ being $rue otherwise.
Second means associated with the control means is operative to cause the switch to ~top conducting negative gate current i~ response to the firse output state of said first means being true, and third means is provided for delaying operation of the second means until the end of a predetermined 15 interval following the start of the aforesaid valve turnof~ command, $hereby ensuring ïhat the sw~tch continuou~ly conducts negati~e gate current throughout such intervall. By the end of thia interval, the first means wou~d be in its second state if the valve turnoff process were normal but would be in its first state if the valve has a shorted gate. In the latter event, 20 the second mea~s is operative to protect the valve control mean~ by terminating the co~ducting state of the controllable s~tch. Preferably, the control mean8 also includes mean~ responsive to operation of the secorld mean3 for en~uring that the se~d mean9 rema~n8 operatiSve for at lea~t a predete~ned "latch-in" period regardless of the output state of ~e first 25 mea~s durirlg 'chi8 period.
Irl other aspect~ of the ;nvention, the fir~t mean~ comprises ~oltage comparing mean~ the first output state of which i8 true only when the voltage acro~s th~ co~trollable 8Wit~l e~ceeds a predetermined magnitude that i8 attained whenever the magnitude of negative gate current equals 30 the a~oresaid threshold magnitude9 arld logic means i8 pro~ided ~or indieating the coeDstence of a ~alve tumof3E comma~d andl the first Btate of ~aid f;rst means.
The invelltioD wiD be better underatood a~d it~ ma3ly objecti~es ~d advantage~ ~nll b8 more fully appreciated from the fi4110Willg d~8cription 35 take~ Dq3unction with the accompa}lying drswin~.
Wo 92/0~636 2 0 7 ~ PC~/US91/05105 FIG. 1 i9 a block diagram of a typical electrical power ~ystem including a (3T0 thyristor;
FIG. 2 is an e~panded block diagram of tl e GT0 control means shown S a~ q single b!oc~s in FIG. 1; and FI(~. 3 i~ a ~unctional block diagTam of the logr~c means used in the GT0 control means to implement the present invention.
lO The ~ystem shown in FIG. 1 includes a 80urce 18 of electric power, an electric load circuit 20, and means ~r interconnecting the ~ource 18 and load 20. The latter mean~ comprises a first conductor N connected directly between an output terrninal of the source 18 and one end of the load 20, a second conductor P connected to another output terminal of the source 18, a 15 third conductor 66 connected to the other end of the load 20, and a high-speed, solid~tate controllable electric Yslve 71 connected between conductorn P and 660 In the illustrated application of the invention, the power source 18 supplie~ direct current to the load circuit, and suitable control means 26 is associated therewith for the purpose of varying the 20 magr~itude of voltage between the output conductor~ P and N as desired. In other prsctical applications of the invention, the output voltage of the ~ource i~ either a u~ipolanty voltag~ of relati~lely con~tant magnitude or an alternating ~roltage of r elatiYely const~t amplitude.
The electric valve 71 is l~own g¢nerally a~ a gate tun~ofl~thy istor or 25 GT0 device. It i~ poled to conduct load current in one direction only, i.e.g from conductor P to conductor 66. Although not ~hown in FIG. 1, in practice an in~ersely polet solid-~tate diude ~nd a suitable snubber circuit ar~ u~ually colm~d in parallel circuit relatioll~hip wîth the val~ 71.
Voltage limiting means (not shown) i~ connected acro~s the load cir~t 20 30 if needed.
The GT0 de~ic0 71 w~ll conduct for~rard load curre~t (i.e.~ ~ent flo~m~g L~to its a3lode and out of its cathode) whe~ it3 ~a~ electrod~
ltnggered by a auitsble tu~-o~ or finng ~ d ~ effectively blo~
such current ater a tur~-off ~ignal i~ alter~atiYely a~plied to t~ ~ame 3S gate. I~ ons app~icatio~ of the invention, thi~ deYice i rated t~ co~duct ~teady 8ta~: unidirectional load currerlt of 450 ampere~ ~vh~ turn~d on .. . . . - . ~ ; .
, . . . . , - .. . .... .
WITH SHORTED GATE DE:TECT:[ON
~,~
Th~s i~ention relates generally to the corltrol of a high-speed, solid-state, unidirectional electric valve of the lsind ~at ~vill s~itch from a non-conduc~ng (off) state to a conduc$ing ~tate (on) in response to a relatiYely positive control voltage being applie~ to a gate electrode of the valve and that5 ~rill subsequently turn ofF in response to a negative control voltage being alternatively applied to the same gate, and it relates more particularly to means for detecting snd responding to a malfimctioning YalYe that fails to turn of~when rlegati~e control voltage is applied to its gate.
A valYe of the kind described is knowrl generally as a gate turno~f 10 (GTO) thyristor. It i~ a multi-layer semieonductor designed to freely conduct nforwasd" anode current (i.e., current flowing into its anode and out of it~ cathode~ when it~ gate electrode is trig~ered by a sultable turn-on or finng fiignal. A GTO thyn~tor i~ diætiI~guished fros~ a conventional ~ -thyri~tor by it~ ability to i~terrupt or blosl~ forwart anode cur~ent if a 15 ~oltag~ of` relativ~ly ~iegative polarity and appropriat~ magnitudle and - ::
duratio~ iu applied acros~ it~ gate-cathode junction. Such Yoltage i~
~egati~e in the sen&~ that the electrical pote~tial of ehe ~a~e is nega~ve with re~pect to the ca~ode. It cau~es current to flow in a reverse direetion in the t~ tor's gate. In ot~er word~, to tur~ off a GTO thyri~tor curreIlt i~ ~ ~
20 drained f~om the gate. Her~ina~er ~uch current is referred to a~ either "l~e~'d~e gat0 curr~nt" or t~e "turnof~ ~ignsl."
ormsl operat;ion, th~ anode curre~t-blocki~g or tur~o~ procesa of a GTO thyristor ~ ba iDitiated at a~y time ~without waitillg for a ~atural or ~ste~lly forced zean crosaillg of the a~l~e ~nt. D~ the tur~of~
25 proce~s the ~gat~e gat~ c~rrent rapiay ri~e~ to a bigh pe~ ~hat depend~
:: on t~ ma~tud~ of :anod~ cu~rent to ba ~terrupted and ~ sub~id~s a~
th~ thyri~tor reco~rera it~ ability to withstand of ~-atat~ anode voltage. On~ a .;:
. .:
~V ~ PCI/US91/05105 Wo 92/05636 f turnoff process is successfully completed, the resistance of the gate-cathode junction i3 very high and limit~ negative gate current to a tr~vial magnitude.
Occasionally a GTO thyristor malfimctions, failing to turn ofF af~er the S turnoff si~al is applied to its gate. Typically the failure mode is an internal short circl~t between the anode and the cathode of the thyr~stor, and this normally result~ in a shorted gat~. Means for detecting such a failure would be useful for both diagnostic and protective purposes. When a shorted gate occurs~ the gate-cathode resistance of the thyristor remains 10 low and ~ill not limit gate current efi~ectiYely. IJnder this abllormal condition an undesirably high magnitude of negati~lre gate current would continue to flow so long as the negative control voltage is applied to the gate, and the large amount of energ~ drained from the failed Gl~:) thyristor could senously oYerheat or otherwise damage the associated control 15 circuit.
mrnar~ of the Inventio~a A general objective of the present in~ention i~ to provide ;mproved means responsive to a failed GTO thyristor for protecting the control circuit 20 that provides the turnoff signal for the GTO th~stor. : .:
Another objectiYe i8 to provide, in a GTO thyristor control circuit, improved means for detectin~ a ~horted gate of the th~stor.
Yet another objective of the in~rention i8 the pro~nsion of an improved method of ~horted gate protection. ~ ~ -In carrying out the invention in one form, a high-speed, solid-state gate turnoff electnc valve i~ connected bet~eerl a ~ource of electrical power and an elect~ic load circuit. Thi8 vslve ha~ alternative on and o~ Btat~. In i~ on gl;at~ the valve ha~ negligible re~istanca alld fireely conduct~ load current, wherea~ in th3 of~ atate it has a resis1;anc~ of very high ohmic 30 valu~ that resembles arl open circuit and e~ecti~rely decouple~ the power source from the load circuit. Control means is coupled to the ga~ of the ~alve for prosiding alternati~re turQ o~ and ~ oi9~ aignals thereto. The turI~o~ BigI12311 i8 provided by means of a co~trollable ~witch con~ectet bet~een the gate ~nd 8 control voltage terminal ~a~ing a negative poterltial 3S with respect to the cathode potential of ~e ~ e. I~ D~ormal operatioII the co~trollable ~witch i~ caused ~ conduct "neg~ re" gate culTeIlt from the : , . ,;
. . .
~ ` . : ; ;. ,.~ , ., ; , ;
9 ~ pCr/~91/05105 thyri~tor gate to the control ~oltage te~inal in response to a valve turnof~
command and to not conduct ~uch current in response to a valve turn on command.
In one aspect of the invention, the valve control means includes fir6t S means coupled to the aforesaid controllable sw~tch and having alternati~e first and ~econd output states, the first output siate being true if negative gate current being conducted by the switch exce~eds a predetermined threshold magnitude that is less than the lowest peak magnitude needed to turn of ~ the valve but greater than the magnitude no,~nally conducted af~er 10 the ~ e i8 in its o~tate, and the secont output 8tat~ being $rue otherwise.
Second means associated with the control means is operative to cause the switch to ~top conducting negative gate current i~ response to the firse output state of said first means being true, and third means is provided for delaying operation of the second means until the end of a predetermined 15 interval following the start of the aforesaid valve turnof~ command, $hereby ensuring ïhat the sw~tch continuou~ly conducts negati~e gate current throughout such intervall. By the end of thia interval, the first means wou~d be in its second state if the valve turnoff process were normal but would be in its first state if the valve has a shorted gate. In the latter event, 20 the second mea~s is operative to protect the valve control mean~ by terminating the co~ducting state of the controllable s~tch. Preferably, the control mean8 also includes mean~ responsive to operation of the secorld mean3 for en~uring that the se~d mean9 rema~n8 operatiSve for at lea~t a predete~ned "latch-in" period regardless of the output state of ~e first 25 mea~s durirlg 'chi8 period.
Irl other aspect~ of the ;nvention, the fir~t mean~ comprises ~oltage comparing mean~ the first output state of which i8 true only when the voltage acro~s th~ co~trollable 8Wit~l e~ceeds a predetermined magnitude that i8 attained whenever the magnitude of negative gate current equals 30 the a~oresaid threshold magnitude9 arld logic means i8 pro~ided ~or indieating the coeDstence of a ~alve tumof3E comma~d andl the first Btate of ~aid f;rst means.
The invelltioD wiD be better underatood a~d it~ ma3ly objecti~es ~d advantage~ ~nll b8 more fully appreciated from the fi4110Willg d~8cription 35 take~ Dq3unction with the accompa}lying drswin~.
Wo 92/0~636 2 0 7 ~ PC~/US91/05105 FIG. 1 i9 a block diagram of a typical electrical power ~ystem including a (3T0 thyristor;
FIG. 2 is an e~panded block diagram of tl e GT0 control means shown S a~ q single b!oc~s in FIG. 1; and FI(~. 3 i~ a ~unctional block diagTam of the logr~c means used in the GT0 control means to implement the present invention.
lO The ~ystem shown in FIG. 1 includes a 80urce 18 of electric power, an electric load circuit 20, and means ~r interconnecting the ~ource 18 and load 20. The latter mean~ comprises a first conductor N connected directly between an output terrninal of the source 18 and one end of the load 20, a second conductor P connected to another output terminal of the source 18, a 15 third conductor 66 connected to the other end of the load 20, and a high-speed, solid~tate controllable electric Yslve 71 connected between conductorn P and 660 In the illustrated application of the invention, the power source 18 supplie~ direct current to the load circuit, and suitable control means 26 is associated therewith for the purpose of varying the 20 magr~itude of voltage between the output conductor~ P and N as desired. In other prsctical applications of the invention, the output voltage of the ~ource i~ either a u~ipolanty voltag~ of relati~lely con~tant magnitude or an alternating ~roltage of r elatiYely const~t amplitude.
The electric valve 71 is l~own g¢nerally a~ a gate tun~ofl~thy istor or 25 GT0 device. It i~ poled to conduct load current in one direction only, i.e.g from conductor P to conductor 66. Although not ~hown in FIG. 1, in practice an in~ersely polet solid-~tate diude ~nd a suitable snubber circuit ar~ u~ually colm~d in parallel circuit relatioll~hip wîth the val~ 71.
Voltage limiting means (not shown) i~ connected acro~s the load cir~t 20 30 if needed.
The GT0 de~ic0 71 w~ll conduct for~rard load curre~t (i.e.~ ~ent flo~m~g L~to its a3lode and out of its cathode) whe~ it3 ~a~ electrod~
ltnggered by a auitsble tu~-o~ or finng ~ d ~ effectively blo~
such current ater a tur~-off ~ignal i~ alter~atiYely a~plied to t~ ~ame 3S gate. I~ ons app~icatio~ of the invention, thi~ deYice i rated t~ co~duct ~teady 8ta~: unidirectional load currerlt of 450 ampere~ ~vh~ turn~d on .. . . . - . ~ ; .
, . . . . , - .. . .... .
2 ~ 7 ~ ~ 9 ~ PCI/US91/05tOS
S
and ~o withs~and a forwart Yoltage in exces~ of 1,600 Yolt~ when turned off, such deYice being capable of successfully turr~ing of3E current as high a~
1,200 amperes in response to a turnof~ sigrlal of sui~able magnitude W~henever the GT0 dPvice or valve 71 i~ in a turned on state, it S prese;lt3 negligible ~sis~nce to for~ard load current, and such current can freely flow from output conductor P of the electMc power source 18 through the conductor 66 and the load circuit 20 to conductor N. But in its turned off state the valve resistance ha9 such a high ohmic value as to block or intenupt a~y load current. To change the GT0 valve 71 between 10 these two alternative states, control means 80, lsbeled "GTO Control,~ i~
assQciated therewith. The control means 80 i~ operati~le in re~ponse to receipt of a discrete signal on a line 33 to change the GT0 valve 71 from on to off states and at the same time to change a normally ~igh "status" signal on an output line 81 to a low state. The corltrol means 80 is slso operatiYe in 15 response to receipt of another discrete signal on a separate input lin~ 82 tochange the GT0 val~e 71 from o~ to on states. The lines 33 and 82 ~n~ate in suit~ble syatem control means 84.
In the illustrated application of the invention, the ~ystem control means 84 is arranged to produce a signal on the line 82 that normally 20 maintain~ the v~lve 71 in its turned on state (which si~nal is hereina~er referret to ~s the "enable" signal) and ~ atively, if ~nd ~hen a certain malfu~eti3ll i8 detected, to produce a "~ault" signal OII the Une 33 that cause~ the valv~ 71 immediately to turn of~. ~er the m~lfiunc~ion i8 cured, the ~nable ~ignal is res~ored. The presently preferred manner in which 25 this i accomplishet i~ disclo~ed and claimed in copending U.S. patent application S.N. (20~ 1583) filed concurrelltly herewith for R. B. Bailey et al and as~igned to G ener~l Elect~c Company, which di~closure i~
e:l~pressly incorporated herein by ref~rence. ~ a differellt appl;catio~ of the i~ventioll, the GTO Y~lYe 71 i8 one of a plurality of interconnected v~fe~
30 that are repe'dtively turIled oll and o~ in a well J~nown manner to form the power sectiorl o~ a polyphase electric power i~verter, ill ~hich case th~
sy~ltem co~trol meal~3 84 would be arra~lged ~ produce a fir~t trail~ of periodic, di~cret~ ~ignal~ on the line 82 a~d a~other trai~ of periodic, discret~ ~ignal~ o~ ~e line 33, the latter ~ignsl~ beillg staggered ~ith 3S r~pect to ~ al8 iIl th* fir~t train and th~ timing of ~a~h tr~ being controned ~8 de~iredO
WO 92/05636 ~ PCI/US91/0510 The tum of~ process of the GT~ valve 71 a~tually ha~ three stages.
Once a GTO ~rnof~signal is applied ~o the gate sf thi9 valve, there is a brief dèlay (known as the "storage" time) be~ore ~orward load current beg~n~ to decrease. Then, d~ring a very short interval known af~ the "fall" time, S current decrease5 rapidly to a very low magnitude. The turnof~ tirne of valve 71 (e.g., approximately 15 microseconds) is the sum of ~he storage and fall times. However, the turno~ signal mu~t not be removed before the end of a longer inte~al (known as ~he "tail" time) w~uch i9 requ~red ~or the vahe to recover fully its ability to withstand 0~-3tate voltage without .
10 prematurely rever~g to a turned on state. During the latter interval the val~e will continue to conduct a relatively small arnount of forward load current (known ss"tail" current) a~ its resistance increases and the voltage acros~ it ri8e~ At the conclusion of this process, there i8 no load curTent in the GTO valve 71, the o~-state voltage applied to the main lS electrode~ of this ~alYe is the same aR the voltage acros~ the output conductors P,N of the power source 18, and the source 18 i8 ef~ectively decoupled from the load circuit 20.
A~ previously described, the GTO valve 71 is changed between its on and of ~ states by the control means 80 in response to the fault signal on line 20 33 and the enable ~ignal on line 82. The presently preferred embodiment of th~ control means 80 i8 illustrated i~ FIG. 2 whic~ ~nll now b~ descnbed.
It comprises suitabl~ gating mean~ 85 fior ~upplying the gate eleetrode of the vallre 71 with either a posit;ve current that e~ect3 turn-on of ~ de~nce, or a relati~ely negati~e current that effects turn-o~ o~ the same device.
25 FIG. 2 includes a simplified schematic diagram of gs~ing rneans used in the flasho~er protection system that i~ disclosed in the prev~ously referenced copending patent application S.N. (20-I~1583). To ~upply the turn-o~ ~ignal, a s i~able ~ource of po~ e poten~al of appro~imately 5 ~rolts with respect to the c~thode potential of v~lve 71 ;s connected to th~ gate 30 of tha GTO valve 71 through a re3istor 8~ of low ohmic value (e.g., 0.6 ohm), firs~ controllabl~ solid-state switch 87, and a line 88. Preferably the ~witch 87 i~ a con~ tional power field e~ect t~an~iator (F~T). A capa~tor 90 i~ conr~ected bet~eea the high side of thi8 E~WitCh snd the cathode of the GTO val~ 71. Whe~ the 8tate of the fir~t s~ntch 87 is chan~ed from non-35 co~ducting to co~ducting~ the +5 volt8 turII-o~ sig~al source i immediately applied to the GTO gats electrodeO Preferably thi~ source : : :
~07~a WO 92/~5636 Pcr/US9l/05105 includes electric energy storing meang (e.g., a capacitor of relatively high capacitanre value pre-charged to a higher level of voltage, for example 13 volts) that rapidly discharge9 when the switch 87 starts conducting so that an initia~ pulse of turn-on energy is supplied to the gate-cathode junction of S GTO 71, after wki~h th~ swit~h B7 continues condlucting the required holding current fron~ the +5 volt~ source.
To supply the turnoff signal for the GTO valve 71, it~ gate is coxmect~d to a control voltage terminal having a negative poten~ial of approximately 13 volts with respect to the GTO cathote through the line 88 and a second 10 controllable solid-state switch 89 which pre~erably comprises a parallel array of three FETs arranged to turn on and o~i~ unison. The second switch 89 is shunted by a bias resistor 91 and al90 by a circl~it comprising another resistor in senes w~th a capacitor 92. When the second sw~tch 89 changes to its sonducting (turned-on) state, the resistance of tbe drain-15 source path in each of the three parallel F~:T~ that fio~ this 6~v~tch i~abruptly changed ~rom a high ohmic ~ralue to a low ohmic ~ralue, and consequently the res~stance between the main terminal~ of the ~;witch 89 decreases to a very low ~ralue (e.g., appro~nmately 0.007 o~). This allows the capacitor 92 to dischsrge through the 8witch 89, thereby reversing the 20 direction of current in the line 88~ CulTent in the gate-$athode j~mction of the GTO valve will chsnge rapidly (e.g., approgimately 40 amps per microsecond) from it~ positi~e holdin~ current m~gnitude (e.g., +6 ampere~) to a peak negati~e m~e~de (e.g., appronmately 100 amperes or more, depending o~ the m~gnitude of load current~ needed to restore the 2S ~rslve'~ ability to block forward load curre~t. A~ the GTO ~alYe i~ tu~ng of~, the resistance of` it~ gate-cathode jullction increases and the negative gate oulTent sub~ide~ i~rom tbe aforesaid peal; magI~itude to a triYial magnit~de. Negati~s current sub~ide~ at a alo~rer rate thaIl it ri~es te.g., appro~cimstely 25 amps per microsecond~O OncQ the val~re turn~ of~ d the 30 tail time e~pire~, it ~ remain off until another turn~D~ 8igllal i~l applied to its gate. Th~ gat~ potential of the GTO ~ re i~ slightly above cathodl3 po~ential w~en thi~ deviee i~ on, and i8 nearly th~ 3~e aa the potential of the -13 volt~ terminal ~Ivhen the valve 71 i~ ofiE and ~hB se~o~d ~witch 89 g turned OIl.
35 The conduc~ng ~tates o~ the two swi~hes 87 a~ld 89 are selecti~ely co~t~olled by assoc~ated logie means 93 and 100 so ~at ol~ly or~e s~tt:h iB
, . . , : .............. . :: ............. ..
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wo 92/05636 2 0 71~ 9 ~ Pcr/us91/05lo~ :
conducting (turned on) at any time. An output line 94 of the first logic means 93 is coupled through an smplifier 95 to the control terminal of the first switch 87, and an output l;ne 96 of the second logic means 100 is coupled through a duplicate amplifier 95 to the control term~nal of the S second switch 8g. The first logic means 93 i3 supplied with both t,ha ~ult signal on the line 33 and the enable signal on line 82, the lines 33 and 82 being respectively connected to two different inputs of thi~ log~c mea~s through suitable optical couplers 98. A second output liIle of the first logi~
means 93 is optic~lly coupled to the line 81 O~ which the ~tatu~ ~ignal is 10 provided. The second logic means 100 has two input~: one i~ connected to a third output line 11~ of the fir~t 1QgiC means 93; the other i9 coupled to the second switch 89 via a line 99 which supplie~ it with a ~eedback value that is a measure of the voltage magnitude across the s~itch 89.
The logic means 93 i8 ~;0 con~tn~cted and a~Ta:nged that the signal 15 produced on its first output line 94 has a high or "C)NI' 6tate gO long a~
enable signsl i8 present on the line 82 but will change ~rom high to low state3 i~ response to a fault signal being receivsd on the line 33.
Concurrently with the latter event, the logic mean~ 93 change~ the 6ignal on its second output line ~rom high to low, thereby ef~ecting a 20 corre~ponding chaDge of the atatus signal that the GTO control mean9 80 provides on line 81. A~ "off-pu}~e" ~mer in the logic mean~ ~ will preYent the first output signal on the line 94, afl;er chan~g ~rom high to low state~, Prom res~g i~ high state for a predetermined delay period (~.g., appro$imately one second). T~i~ timer ~lso e~abl¢~ a high 8tatu~ Bignal k~
25 retur~ on lins 81 upo~ espiral~on of ~uch delay period. On its third output line 115 the fir~t logic mesn~ 93 prodluces aII input sign~l for the 6econd logic mea~ 100, 1;~ ~tate of thi8 input 8ignal b~lIlg opposite to ~ state of the fir~t output 8ig~1 ODI lîne ~4; thst i~, the ~put ~igDal O~ iB lOW
WheneV2r t~h8 fir~t outpult ~ignal ;~ high and i~ high ~vhenever the fir~t 30 output 8ig~1al i~l low. Circuit details of the pre~ tly prefierred embodimentof the fir~t logi~ mean3 93 are more fully di~clo~ed in th8 previou~ly refererlced copending patellt applicatiorl S.N. (2C~L~1583).
Each low~ hig~ transi~on of the fir~t output ~i~al o~ line 94 ~ill cau e the fir~t swi~ 87 to conduct, thereby ~!hanging the coIl~rollabl GTO
35 ~alve 71 to i~ tur~ o~ Btate. Altematively, a lo~ ~g~al o~ e 94 ~vill bia~ r~t ~ h 87 t~ on-conducting ~tate. ~hUB a high output ~ . .
.. . . .
- - : . . -..... :
W092/0~636 2071~,~a PCI/US91/05~05 ~ignal on line 94 function~ a~ a valve tur~ on comma~ld. In a manner that will soon be e~pla~ned, the ~econd logic mean~ 100 re~pond~ to the input signal on the line 115 by normally producing a 6ignal on it~ output line 96 that has a high or ~OFF" sta~e 80 long a~ the input si~al i~ high but has a S low state otherwise. Each low~ hign transition of the output signal on line 96 will cause the second ~witch 89 to conduct, thereby changing the Gl`O valve 71 to its turned-off 8tate. Alter~ati~rely, while the input 6igIlal iS
low the ~ignal on the line 96 i~ low ao a3 to bias the 6econd swi~ch 89 ~ itR
non-conducting 6tate, which will be tme whene~r the aigI~al on the output 10 line 94 of the first logic means 93 i3 iII it8 ON state. ThU!3 a high input signal on line 115 fi~nction~ a3 a va~Ye turDoff command.
The presently preferred embodiment of the lo~c mean~ 100 i~ shown in FIG. 3 and will ~ow be de~cribed. It employs several dual input analog logic c;rcuits suitably intercor~nected and arranged to perfonn the ~arious 15 functions described belo~. For the ~ake of conveniense, the indi~idual logic circuit~ have been shown symbolically in a 60mewhat simplified form in ~IG. 3 and are hereinafter called "units." One type of unit has a high t"l") output state orlly when it~ first input is high and it~ other input i9 IOW (''O''), the latter input b~,ing re~e~Ted to a~ a "notn input. In practic~, this 6ame 20 function could be per~orm~d by other equivalent logic circuits, s~ach as the combination of a conventional ~ logic circuit wit~ a polarity inverter ahead of its second input, or the combinatio~ of a conv~ntional NOR lo~c circuit with a polarity ir~erteT ahead of it~ fir~t il~pUt.
In accordallc~ with the prexellt i~Yen~ioIl, the i~put line 115 of th~
25 logio mea:~s 100 i~ connected to th~ output lin~ 96 by mearl~ of arl OR logicunit 116 ha~ring t~o input~, one input b~L~g connected through a timer 117 aabeled "mi~ o~') tD the line 115 ancl the other input being connected via a line 118 to the ou~p~t of ano~her u~it 119 th~ first input of which i8 comlected to the li~le 116 and the not i~put of wl~ connected to a li~e 30 120 on which a h;gh ~gn~l i8 pro~ricled whe~ lhe GTID val~e i~ on but not whe~ the GTO ~ o~ wlder normal conditiona. The ltimer 117 is a collYentional N~lle-~ho~ time telay circl~it, the first output of which i8 normally low but ~ll cl~ ge to a temporary high ~tate a~ 8003~ as the sigDal applied ~ t~ ~put of the ~rcuit ~a~ges firom lo~ ~ high, will 35 the~ remai~ ~ig~h for a fi~d inter\ral of ti~e e~re~l if the input signal ohanges ~oo~er f~m ~igh to low, aIld w~ll automatically retuT~ to ;t~
, -WO 92/05636 2 0 7 1 ~ ~ J pcr/us91/o5lo5 normal low state at the end of such inter~ral even if the input 6ignal remains high. So long a~ the signal on output line 94 of the first logic means 93 (FIG. 2) i~ high, the input Sigllal on line 11S ia low and therefore the output state of the OR logic ~Lnit 116 is low. But whenever a high signal S i~ applied to the line 33, the si~nal on output line 94 changes 9tate Çroal high to low, the input signal on line 11~ goes high, and the staeu~ Sigrlal on lin~ 81 changes ~om high to low. The system control means 84 ~FIG. 1) will respond to this 8tatu8 ~hange by immediately changing the enable signal on line 82 ~om high to low 6tste~ ~nd later re~toAng the high ~tate 10 of thi9 signal. The min-of~ timer 117 in FIG. 3 re~ponds to the lo~-to-high transition of the input signal on line 115 by temporarily ~upplying a high signal to the {)R u~it 116 which consequently produce~ a high signal on the output line 96 ~i.e., the aforesaid OFF state t`or turning off the GTO valve 71). Once produced in this manner, the high signal on line 96 will rernain 15 high for a desired minimum interval measured from the moment of time when the 6igllal on line 11~ changed from low to higlh ~tates. The timer 117 is ~uitably adjusted to ensure that the duration of any turnoff ~ignal applied to the gat~ of the valve 71 ~ll equal or e~cceed the ~um oiE the aforesaid turnoff and tail times of this valve.
20 Throughout the interval that the enable signal on line 82 i8 IOW, the 8ignal on output l;ne 94 ~ th~ fir~t logic mean~ 93 tFIG. 2) is low, no GTO
turD-on ~ignal ca~ be producsd by the co~trol means 80, and the OFF Btate of the 8ig~ on the output line 96 of the logic meang 100 i3 ~ustained ~as~ ng there is ~o high ~ignal o~ the line 1a0). But a~ EoQn a~ th@ high 25 Btate of thi3 enable ~ignal is restored and the aforesaid of ~-pul6e delay penod e~pires, the logic mean~ 93 return~ the ~ignal on li~e 115 to a low sSate, the si~al on output lirlQ 96 changes states from high to lo~r thereby te~na~g the ~1'0 turnoffsign~l, and concurrently the 8;~1al on output line 94 cbange~ ~rom low to high thereby cau8~0g the GTO ga~Dg mean~ 85 30 to apply a tur~-on ~ig~l to tbe gate of the GTO YalY~ 71. Person~ 91silled ill the ar1; ~nll apprsciat0 the advantage~ of suataining tb e OFF state of the Bignal on the output lin~ 96 until a valve tum o~ eommand i~ recei~ed.
Brief~y ststed, the OFF ~tate on line 96 keep~ the turnof~ switch 89 in a ccnducting ~tate ~hich con'dnuously cl~mps the gate of the G~O valYe 71 to 35 ths -13 Yolt~ control ~olt~ge terminal, thereby p~eventi~g u~de~ired .. . , . . . . ~ .
, .. . .. . . . .
. : . , . ~ , .
, W O 92/05636 2 ~ 718 9 ~ P ~ /US91/05105 "avalanche" firing of the turned ofF valve if the anode~ cathode path become~ forward biased by a high or rapidly rising~roltage In the event the GTO valve 71 has a shorted gate, 'thi8 deYice will fail to turn of~ when a turno~ sigTlal iS applied to its gate. In accordance ~ith the S present invention, the log~c mean~ 10Q includ~s !nean~ Çor d8tecting this abnormal event and for protecting the GTO control means 80 from resulting damage. As i~ illustrated in FIC3. 3, it comprises the min-off timer 117, the logic unit 119, an OR logic unit 121, another timer 123 ~labeled "temp latch"), and suitable means 127 for comparing the feedbac~
10 value on line 99 (i.e., the actual volts across the tu~nof~ s~ritch 89 ill FIG. 2) ~vith a predetermined, relatively small reference ~magnitude K4 (e.g, appro~mately 0.7 ~olt). K4 i~ selected to be equal to the voltage developed across the turnoff switch 89 whenever this switch is in its conducting state and negative current in the gate of the GTO Yalve 71 equals a certain high 15 threshold magn~tude that is normally experienced only during the tu~noff and tail times of a ~uccess~ul tum off process of thi~ valve, and it i5 much less than the volt~ across the switch 89 when biased to its non-conducting ~tate. This threshold magnitude of gate culTent (e.g., appro~cimately 100 amps) is select~d to be greater than the magnitude conducted by the switch 20 89 when the valve 71 is turned of ~ and preferably less than the lowest peak mag~itude needed to change the val~re from on to off state3. The comparing means 127 has a ~ output state ~o long as the feedbac~ Yalue on line 99 is greater than X4, which i8 true if either the turnoi~ switeh 89 i~ turned on and conducting high current or both the turnof~ ~witch and t~e G~O ~alve 25 a~ turned o~ but i~ not true if the tumo* ~witch 89 i3 tumed on andl not co~ducting appreciable current. I~ the latter evellt, the com p~ring m eaIls output ha~ a low ~tato.
Ihe output of t~e comparing means 127 i~ coImected b~ mean~ of a line 126 to one i~put of the OR w3it 121. The tem~latch timer 123~ which 30 has a llormally lo~ output, i6 connected between the ou~I)ut line 96 of the logic meaIl~ 100 alld the ~eco~d input of the u~it 121. The l;imer 123 i~
~lar to the min~ ~mer 117 but i8 activa~ ~y a highto low tra~sition of ~he output Bi&pl~l 0~ ~bne 96. O~ce sc~vated,the timer 123 w ~l ~upply a high ~ al to th~ aecond input of the OR unit 121 for a predetermi~ed 35 r~lati-~ely shor/; nlBtCh-iXI" period of tiDle te.g., appro;~Lmately 30 micro-~cond~). Thu~ th0 outpu$ of the ~t 121 i~ in a b;gh ~tate du ing the WO 92/05636 ~ ~) '7 ~ pcr/us91/o5 temporary latch-in period a~er the OFF stat8 of the ~ignal on the output line 96 terminate~ or whenever ~he comparing means 127 ha~ a high output state, and otherwis~ it is low. The output state of unit 121 is conveyed by the line 120 to the not input of the logic unit 119. So long a~ thisS input is low, the output of the latter unit (i.e., the signal oh line 118) track the high and low 13tate~ of the signal on the line 115; otherw~se the signal on line 118 is low.
In operation, the ~ignal orl line 115 change~ from low to high in response to a high fault 13igI18l being supplied to the logic mean~ 93, which 10 event marks the stsrt of a GTO valve tumoff command. At the ~ame time the output of the min-of~ timer 117 changes frnm its normal low state to a high state which subsi~ts until the end of the aforementioned minimum in~erval. This temporary high output is coupled by the OR logic unit 116 to the output line 96 of the logic means 100, thereby turning on the turno~
15 switch 89 which conducts the negative gate cur~ent required to turn off the GTO valve 71 as prev~ou~ly described. When the switch 89 initially turn~
on, the voltage across it collapse~ to a negligible magnitude and the signal on the output line 126 of the comparing mean~ 127 changes firom high to low. Concurrently, the output of the OR unit 121 changes firom high to low, 20 and the un~t 119 causea the 5igIlal on line 118 to change !~rom low to high.
Thereafter the negative GTO gate current i~ the switch 8~ rapidly increases and SOOR e~cceed~ the thre5hold magl~itude at which the voltage ~eedback value o~ line 99 equa3~ ~4, whereupon the signal~ on line~ 126 and 120 respectively retur~ to their former high ~tates and the ~ignal on 25 line 118 temporarily retums to it6 former low Btate.
During a nor~al GTO turnoff proce~3, negatiYe gate t~o~ current sub~ide3 ~rom a high peak value to a tn~ial mag~tude, and the volts across the turno~ ~itc~ 89 will decrease to les~ th~ R4 before the end of th~ tail time of th~ valve 71. A~ ~uch voltage de~resses belo~ X4, ~he 30 ~ignal~ on lines 126 and 120 again change to their low 8tate~1 and the unit 119 concurrently c~s the 8igQal on line 118 to it~ higll atat~. The la~ter ~ignal i~ coupled b~ the OR unit 116 to the output line 96, thereby sustainis~g the OFF ~tate of t~e output ~ignal orl thia line a~er l;he output of the min-oflE
timer 117 au~omatic~lly revert~ to its low 8tate at the e~d of the mi~mum 35 int~r~ral. Througho~st thi8 normal turnof~ pFOCel~8, the output OI ~e temp la~ timer 123 wi~l be lo~.
: .
- , ' ~ ' ~ ~ 7 ~ P~T/US91/051û5 However, if th~ gate of the GTO valve 71 were shorted, negative gate current would not ~ubside during the attempted turn off proces~. In this event, the volts acro~s ths sw~tch $9 would not decrease below K4, the SigIlal9 on both lines 126 and 120 would remain hi~h, unit 119 would keep S the signal on its output line 11~ lo~, and the output Blg-ilal on line 96 would return to a low state as 800n a8 the output of the ~lin-off timer 117 returns to its normal, low state at the end of the minimum tu~off interval The resulting low signal on the output line 96 of the logic means 100 will bia3 the switch 89 to it~ off state, thereby removil-g tlhe low~resi~tance path that 10 thi~ switch would otherwi~e provide, if it ~ere not tulned o~, &om the gate of the GTO valve to the -13 ~volts control voltage termunal ~see FIG. 2) and causing the switch to stop conducting negative gate current. Interrupting negativ~ current in the shorted gate of the val~e 71 ~ll protect the switch 89 from damage caused by continuin~ to conduct high current af~er the 15 minimum turnof~inter~al expires. To ensure proper operation of the shorted gate de~ector in the illu trated embodiment of the invention, the minimum turnof~interral i5 approximately 80 microseconds. In e;f~ect, the min-o~ t;imer 117 delays the protective operation of the logic unit :l19 1mtil the end of the rninimum turnoflE interval fiollowing the ~tart of the aforesaid 20 valve turnoff command, thereby preventing a ~alse re~ponse to the tempQrsrily low signal on the line 118 during a normal GTO turnoff process and ensunng that the logic means 10t) continue~ to apply a high ~ignal ~ia it~ output line 96 to the turnof~ switch 89 throughout the ~imum turno~ interval.
AR soon as the output signal o~ line 96 changes from high to low in delayed response to the volts across the tur~of~ ntch 89 increaQing above K4 (wl~ch in tu~ cau~ed the high~ lo~ tran~itio~ of the ~ignal on the out;put li~e 118 o~l~e ~t 119 a8 descnbed above), the output of ~e temp-latch timer 123 Ch8Dge3 firom low to high. Thi~ ensure~ that the high si~nal OII line 120 and the lo~v ~ignal on line 118 ~nll both remain u~lchar~ged during th~ ensu~ng lateh-in pe~od, regardle~ of whether the ~ignal on lirle 126 is high or low. Thu~ the temp-latch ~n0r 123 inhibit3 unde~irable oscillation of the output 8ignal Oi~l lir~e 96 if the ou~ut ~ of ths oomparing me~ 127 ~vere to change fr~m high to lo~ du~ng ~uch 35 period. Such a cl~ vill occur when the turnof3~ al applied to tbe ~ralYa 71 i8 termi~ated and the gate vol~ge Ari2~g8~ ~egativ~ du~ to :;
, . . .. , ; ,. . . ~ , , 2~'7~
WO 92/05636 Pcr/US9l/0510 osc~llatory interaction of the snubber capacitance across the valve and the inherent inductanc~ in the gate circuit.
The detection of a ~hor~ed gat~ also causes a low-to-high state change of an output signal on a line 125 interconnecting the ]logic means 93 and 5 100. As jB showr. in FIC-. 3, the latter signal i~ providecl by a log~c unit 128 whose ~lrat input i~ connected to the line 115 snd 1whose not input is eonnected to the line 118. The signal on line 118 wouldl be low if a shorted GTO gate were de~ected while the 5i~al on line 115 i8 hi~h (i.e., while turno~ of the GTO valve i~ being commanded). In this event, the unit 128 i8 10 effective to provide a high output sigr~al on line 125. The logic means 93 includes suitable meaIlY for msintair~ing a low status signal on the line 81 throughout the delsy period provided by the prenously mentioned off-pulse timer or ~vhenever the signal on line 125 is high. It will ~e obser~ed that during the previou~ly described normal turnof~process of ~e GTO valve 71 15 the output of the comparing means 127 is high, due to the voltage feedback ~value on the line 99 temporarily rising above K4, for a short period of time during which the unit 1~8 w~ll provide a high output signal on the line 125 even though there i8 no ~horted gate. In 80me application~ of the inYentio~
this temporary high signal on line 125 duri}2g a normal GTO turnoff 20 process may provide 8 useful indication that such turnof~ proce8s i3 taking place.
While only o~ embodiment of the invention has been ~hown and de~cribed rby way of e~ample, many modifioation3 will undollbtedly occur to per~on~ ~lcilled in the art. The concluding claims are therefor~ intended to 25 cover all such modifications that fall within the kue spirit and ~oope of the inventio~.
"', ' ', ~
~. ,.
S
and ~o withs~and a forwart Yoltage in exces~ of 1,600 Yolt~ when turned off, such deYice being capable of successfully turr~ing of3E current as high a~
1,200 amperes in response to a turnof~ sigrlal of sui~able magnitude W~henever the GT0 dPvice or valve 71 i~ in a turned on state, it S prese;lt3 negligible ~sis~nce to for~ard load current, and such current can freely flow from output conductor P of the electMc power source 18 through the conductor 66 and the load circuit 20 to conductor N. But in its turned off state the valve resistance ha9 such a high ohmic value as to block or intenupt a~y load current. To change the GT0 valve 71 between 10 these two alternative states, control means 80, lsbeled "GTO Control,~ i~
assQciated therewith. The control means 80 i~ operati~le in re~ponse to receipt of a discrete signal on a line 33 to change the GT0 valve 71 from on to off states and at the same time to change a normally ~igh "status" signal on an output line 81 to a low state. The corltrol means 80 is slso operatiYe in 15 response to receipt of another discrete signal on a separate input lin~ 82 tochange the GT0 val~e 71 from o~ to on states. The lines 33 and 82 ~n~ate in suit~ble syatem control means 84.
In the illustrated application of the invention, the ~ystem control means 84 is arranged to produce a signal on the line 82 that normally 20 maintain~ the v~lve 71 in its turned on state (which si~nal is hereina~er referret to ~s the "enable" signal) and ~ atively, if ~nd ~hen a certain malfu~eti3ll i8 detected, to produce a "~ault" signal OII the Une 33 that cause~ the valv~ 71 immediately to turn of~. ~er the m~lfiunc~ion i8 cured, the ~nable ~ignal is res~ored. The presently preferred manner in which 25 this i accomplishet i~ disclo~ed and claimed in copending U.S. patent application S.N. (20~ 1583) filed concurrelltly herewith for R. B. Bailey et al and as~igned to G ener~l Elect~c Company, which di~closure i~
e:l~pressly incorporated herein by ref~rence. ~ a differellt appl;catio~ of the i~ventioll, the GTO Y~lYe 71 i8 one of a plurality of interconnected v~fe~
30 that are repe'dtively turIled oll and o~ in a well J~nown manner to form the power sectiorl o~ a polyphase electric power i~verter, ill ~hich case th~
sy~ltem co~trol meal~3 84 would be arra~lged ~ produce a fir~t trail~ of periodic, di~cret~ ~ignal~ on the line 82 a~d a~other trai~ of periodic, discret~ ~ignal~ o~ ~e line 33, the latter ~ignsl~ beillg staggered ~ith 3S r~pect to ~ al8 iIl th* fir~t train and th~ timing of ~a~h tr~ being controned ~8 de~iredO
WO 92/05636 ~ PCI/US91/0510 The tum of~ process of the GT~ valve 71 a~tually ha~ three stages.
Once a GTO ~rnof~signal is applied ~o the gate sf thi9 valve, there is a brief dèlay (known as the "storage" time) be~ore ~orward load current beg~n~ to decrease. Then, d~ring a very short interval known af~ the "fall" time, S current decrease5 rapidly to a very low magnitude. The turnof~ tirne of valve 71 (e.g., approximately 15 microseconds) is the sum of ~he storage and fall times. However, the turno~ signal mu~t not be removed before the end of a longer inte~al (known as ~he "tail" time) w~uch i9 requ~red ~or the vahe to recover fully its ability to withstand 0~-3tate voltage without .
10 prematurely rever~g to a turned on state. During the latter interval the val~e will continue to conduct a relatively small arnount of forward load current (known ss"tail" current) a~ its resistance increases and the voltage acros~ it ri8e~ At the conclusion of this process, there i8 no load curTent in the GTO valve 71, the o~-state voltage applied to the main lS electrode~ of this ~alYe is the same aR the voltage acros~ the output conductors P,N of the power source 18, and the source 18 i8 ef~ectively decoupled from the load circuit 20.
A~ previously described, the GTO valve 71 is changed between its on and of ~ states by the control means 80 in response to the fault signal on line 20 33 and the enable ~ignal on line 82. The presently preferred embodiment of th~ control means 80 i8 illustrated i~ FIG. 2 whic~ ~nll now b~ descnbed.
It comprises suitabl~ gating mean~ 85 fior ~upplying the gate eleetrode of the vallre 71 with either a posit;ve current that e~ect3 turn-on of ~ de~nce, or a relati~ely negati~e current that effects turn-o~ o~ the same device.
25 FIG. 2 includes a simplified schematic diagram of gs~ing rneans used in the flasho~er protection system that i~ disclosed in the prev~ously referenced copending patent application S.N. (20-I~1583). To ~upply the turn-o~ ~ignal, a s i~able ~ource of po~ e poten~al of appro~imately 5 ~rolts with respect to the c~thode potential of v~lve 71 ;s connected to th~ gate 30 of tha GTO valve 71 through a re3istor 8~ of low ohmic value (e.g., 0.6 ohm), firs~ controllabl~ solid-state switch 87, and a line 88. Preferably the ~witch 87 i~ a con~ tional power field e~ect t~an~iator (F~T). A capa~tor 90 i~ conr~ected bet~eea the high side of thi8 E~WitCh snd the cathode of the GTO val~ 71. Whe~ the 8tate of the fir~t s~ntch 87 is chan~ed from non-35 co~ducting to co~ducting~ the +5 volt8 turII-o~ sig~al source i immediately applied to the GTO gats electrodeO Preferably thi~ source : : :
~07~a WO 92/~5636 Pcr/US9l/05105 includes electric energy storing meang (e.g., a capacitor of relatively high capacitanre value pre-charged to a higher level of voltage, for example 13 volts) that rapidly discharge9 when the switch 87 starts conducting so that an initia~ pulse of turn-on energy is supplied to the gate-cathode junction of S GTO 71, after wki~h th~ swit~h B7 continues condlucting the required holding current fron~ the +5 volt~ source.
To supply the turnoff signal for the GTO valve 71, it~ gate is coxmect~d to a control voltage terminal having a negative poten~ial of approximately 13 volts with respect to the GTO cathote through the line 88 and a second 10 controllable solid-state switch 89 which pre~erably comprises a parallel array of three FETs arranged to turn on and o~i~ unison. The second switch 89 is shunted by a bias resistor 91 and al90 by a circl~it comprising another resistor in senes w~th a capacitor 92. When the second sw~tch 89 changes to its sonducting (turned-on) state, the resistance of tbe drain-15 source path in each of the three parallel F~:T~ that fio~ this 6~v~tch i~abruptly changed ~rom a high ohmic ~ralue to a low ohmic ~ralue, and consequently the res~stance between the main terminal~ of the ~;witch 89 decreases to a very low ~ralue (e.g., appro~nmately 0.007 o~). This allows the capacitor 92 to dischsrge through the 8witch 89, thereby reversing the 20 direction of current in the line 88~ CulTent in the gate-$athode j~mction of the GTO valve will chsnge rapidly (e.g., approgimately 40 amps per microsecond) from it~ positi~e holdin~ current m~gnitude (e.g., +6 ampere~) to a peak negati~e m~e~de (e.g., appronmately 100 amperes or more, depending o~ the m~gnitude of load current~ needed to restore the 2S ~rslve'~ ability to block forward load curre~t. A~ the GTO ~alYe i~ tu~ng of~, the resistance of` it~ gate-cathode jullction increases and the negative gate oulTent sub~ide~ i~rom tbe aforesaid peal; magI~itude to a triYial magnit~de. Negati~s current sub~ide~ at a alo~rer rate thaIl it ri~es te.g., appro~cimstely 25 amps per microsecond~O OncQ the val~re turn~ of~ d the 30 tail time e~pire~, it ~ remain off until another turn~D~ 8igllal i~l applied to its gate. Th~ gat~ potential of the GTO ~ re i~ slightly above cathodl3 po~ential w~en thi~ deviee i~ on, and i8 nearly th~ 3~e aa the potential of the -13 volt~ terminal ~Ivhen the valve 71 i~ ofiE and ~hB se~o~d ~witch 89 g turned OIl.
35 The conduc~ng ~tates o~ the two swi~hes 87 a~ld 89 are selecti~ely co~t~olled by assoc~ated logie means 93 and 100 so ~at ol~ly or~e s~tt:h iB
, . . , : .............. . :: ............. ..
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,, . , .. , , . : ~ : . :
wo 92/05636 2 0 71~ 9 ~ Pcr/us91/05lo~ :
conducting (turned on) at any time. An output line 94 of the first logic means 93 is coupled through an smplifier 95 to the control terminal of the first switch 87, and an output l;ne 96 of the second logic means 100 is coupled through a duplicate amplifier 95 to the control term~nal of the S second switch 8g. The first logic means 93 i3 supplied with both t,ha ~ult signal on the line 33 and the enable signal on line 82, the lines 33 and 82 being respectively connected to two different inputs of thi~ log~c mea~s through suitable optical couplers 98. A second output liIle of the first logi~
means 93 is optic~lly coupled to the line 81 O~ which the ~tatu~ ~ignal is 10 provided. The second logic means 100 has two input~: one i~ connected to a third output line 11~ of the fir~t 1QgiC means 93; the other i9 coupled to the second switch 89 via a line 99 which supplie~ it with a ~eedback value that is a measure of the voltage magnitude across the s~itch 89.
The logic means 93 i8 ~;0 con~tn~cted and a~Ta:nged that the signal 15 produced on its first output line 94 has a high or "C)NI' 6tate gO long a~
enable signsl i8 present on the line 82 but will change ~rom high to low state3 i~ response to a fault signal being receivsd on the line 33.
Concurrently with the latter event, the logic mean~ 93 change~ the 6ignal on its second output line ~rom high to low, thereby ef~ecting a 20 corre~ponding chaDge of the atatus signal that the GTO control mean9 80 provides on line 81. A~ "off-pu}~e" ~mer in the logic mean~ ~ will preYent the first output signal on the line 94, afl;er chan~g ~rom high to low state~, Prom res~g i~ high state for a predetermined delay period (~.g., appro$imately one second). T~i~ timer ~lso e~abl¢~ a high 8tatu~ Bignal k~
25 retur~ on lins 81 upo~ espiral~on of ~uch delay period. On its third output line 115 the fir~t logic mesn~ 93 prodluces aII input sign~l for the 6econd logic mea~ 100, 1;~ ~tate of thi8 input 8ignal b~lIlg opposite to ~ state of the fir~t output 8ig~1 ODI lîne ~4; thst i~, the ~put ~igDal O~ iB lOW
WheneV2r t~h8 fir~t outpult ~ignal ;~ high and i~ high ~vhenever the fir~t 30 output 8ig~1al i~l low. Circuit details of the pre~ tly prefierred embodimentof the fir~t logi~ mean3 93 are more fully di~clo~ed in th8 previou~ly refererlced copending patellt applicatiorl S.N. (2C~L~1583).
Each low~ hig~ transi~on of the fir~t output ~i~al o~ line 94 ~ill cau e the fir~t swi~ 87 to conduct, thereby ~!hanging the coIl~rollabl GTO
35 ~alve 71 to i~ tur~ o~ Btate. Altematively, a lo~ ~g~al o~ e 94 ~vill bia~ r~t ~ h 87 t~ on-conducting ~tate. ~hUB a high output ~ . .
.. . . .
- - : . . -..... :
W092/0~636 2071~,~a PCI/US91/05~05 ~ignal on line 94 function~ a~ a valve tur~ on comma~ld. In a manner that will soon be e~pla~ned, the ~econd logic mean~ 100 re~pond~ to the input signal on the line 115 by normally producing a 6ignal on it~ output line 96 that has a high or ~OFF" sta~e 80 long a~ the input si~al i~ high but has a S low state otherwise. Each low~ hign transition of the output signal on line 96 will cause the second ~witch 89 to conduct, thereby changing the Gl`O valve 71 to its turned-off 8tate. Alter~ati~rely, while the input 6igIlal iS
low the ~ignal on the line 96 i~ low ao a3 to bias the 6econd swi~ch 89 ~ itR
non-conducting 6tate, which will be tme whene~r the aigI~al on the output 10 line 94 of the first logic means 93 i3 iII it8 ON state. ThU!3 a high input signal on line 115 fi~nction~ a3 a va~Ye turDoff command.
The presently preferred embodiment of the lo~c mean~ 100 i~ shown in FIG. 3 and will ~ow be de~cribed. It employs several dual input analog logic c;rcuits suitably intercor~nected and arranged to perfonn the ~arious 15 functions described belo~. For the ~ake of conveniense, the indi~idual logic circuit~ have been shown symbolically in a 60mewhat simplified form in ~IG. 3 and are hereinafter called "units." One type of unit has a high t"l") output state orlly when it~ first input is high and it~ other input i9 IOW (''O''), the latter input b~,ing re~e~Ted to a~ a "notn input. In practic~, this 6ame 20 function could be per~orm~d by other equivalent logic circuits, s~ach as the combination of a conventional ~ logic circuit wit~ a polarity inverter ahead of its second input, or the combinatio~ of a conv~ntional NOR lo~c circuit with a polarity ir~erteT ahead of it~ fir~t il~pUt.
In accordallc~ with the prexellt i~Yen~ioIl, the i~put line 115 of th~
25 logio mea:~s 100 i~ connected to th~ output lin~ 96 by mearl~ of arl OR logicunit 116 ha~ring t~o input~, one input b~L~g connected through a timer 117 aabeled "mi~ o~') tD the line 115 ancl the other input being connected via a line 118 to the ou~p~t of ano~her u~it 119 th~ first input of which i8 comlected to the li~le 116 and the not i~put of wl~ connected to a li~e 30 120 on which a h;gh ~gn~l i8 pro~ricled whe~ lhe GTID val~e i~ on but not whe~ the GTO ~ o~ wlder normal conditiona. The ltimer 117 is a collYentional N~lle-~ho~ time telay circl~it, the first output of which i8 normally low but ~ll cl~ ge to a temporary high ~tate a~ 8003~ as the sigDal applied ~ t~ ~put of the ~rcuit ~a~ges firom lo~ ~ high, will 35 the~ remai~ ~ig~h for a fi~d inter\ral of ti~e e~re~l if the input signal ohanges ~oo~er f~m ~igh to low, aIld w~ll automatically retuT~ to ;t~
, -WO 92/05636 2 0 7 1 ~ ~ J pcr/us91/o5lo5 normal low state at the end of such inter~ral even if the input 6ignal remains high. So long a~ the signal on output line 94 of the first logic means 93 (FIG. 2) i~ high, the input Sigllal on line 11S ia low and therefore the output state of the OR logic ~Lnit 116 is low. But whenever a high signal S i~ applied to the line 33, the si~nal on output line 94 changes 9tate Çroal high to low, the input signal on line 11~ goes high, and the staeu~ Sigrlal on lin~ 81 changes ~om high to low. The system control means 84 ~FIG. 1) will respond to this 8tatu8 ~hange by immediately changing the enable signal on line 82 ~om high to low 6tste~ ~nd later re~toAng the high ~tate 10 of thi9 signal. The min-of~ timer 117 in FIG. 3 re~ponds to the lo~-to-high transition of the input signal on line 115 by temporarily ~upplying a high signal to the {)R u~it 116 which consequently produce~ a high signal on the output line 96 ~i.e., the aforesaid OFF state t`or turning off the GTO valve 71). Once produced in this manner, the high signal on line 96 will rernain 15 high for a desired minimum interval measured from the moment of time when the 6igllal on line 11~ changed from low to higlh ~tates. The timer 117 is ~uitably adjusted to ensure that the duration of any turnoff ~ignal applied to the gat~ of the valve 71 ~ll equal or e~cceed the ~um oiE the aforesaid turnoff and tail times of this valve.
20 Throughout the interval that the enable signal on line 82 i8 IOW, the 8ignal on output l;ne 94 ~ th~ fir~t logic mean~ 93 tFIG. 2) is low, no GTO
turD-on ~ignal ca~ be producsd by the co~trol means 80, and the OFF Btate of the 8ig~ on the output line 96 of the logic meang 100 i3 ~ustained ~as~ ng there is ~o high ~ignal o~ the line 1a0). But a~ EoQn a~ th@ high 25 Btate of thi3 enable ~ignal is restored and the aforesaid of ~-pul6e delay penod e~pires, the logic mean~ 93 return~ the ~ignal on li~e 115 to a low sSate, the si~al on output lirlQ 96 changes states from high to lo~r thereby te~na~g the ~1'0 turnoffsign~l, and concurrently the 8;~1al on output line 94 cbange~ ~rom low to high thereby cau8~0g the GTO ga~Dg mean~ 85 30 to apply a tur~-on ~ig~l to tbe gate of the GTO YalY~ 71. Person~ 91silled ill the ar1; ~nll apprsciat0 the advantage~ of suataining tb e OFF state of the Bignal on the output lin~ 96 until a valve tum o~ eommand i~ recei~ed.
Brief~y ststed, the OFF ~tate on line 96 keep~ the turnof~ switch 89 in a ccnducting ~tate ~hich con'dnuously cl~mps the gate of the G~O valYe 71 to 35 ths -13 Yolt~ control ~olt~ge terminal, thereby p~eventi~g u~de~ired .. . , . . . . ~ .
, .. . .. . . . .
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, W O 92/05636 2 ~ 718 9 ~ P ~ /US91/05105 "avalanche" firing of the turned ofF valve if the anode~ cathode path become~ forward biased by a high or rapidly rising~roltage In the event the GTO valve 71 has a shorted gate, 'thi8 deYice will fail to turn of~ when a turno~ sigTlal iS applied to its gate. In accordance ~ith the S present invention, the log~c mean~ 10Q includ~s !nean~ Çor d8tecting this abnormal event and for protecting the GTO control means 80 from resulting damage. As i~ illustrated in FIC3. 3, it comprises the min-off timer 117, the logic unit 119, an OR logic unit 121, another timer 123 ~labeled "temp latch"), and suitable means 127 for comparing the feedbac~
10 value on line 99 (i.e., the actual volts across the tu~nof~ s~ritch 89 ill FIG. 2) ~vith a predetermined, relatively small reference ~magnitude K4 (e.g, appro~mately 0.7 ~olt). K4 i~ selected to be equal to the voltage developed across the turnoff switch 89 whenever this switch is in its conducting state and negative current in the gate of the GTO Yalve 71 equals a certain high 15 threshold magn~tude that is normally experienced only during the tu~noff and tail times of a ~uccess~ul tum off process of thi~ valve, and it i5 much less than the volt~ across the switch 89 when biased to its non-conducting ~tate. This threshold magnitude of gate culTent (e.g., appro~cimately 100 amps) is select~d to be greater than the magnitude conducted by the switch 20 89 when the valve 71 is turned of ~ and preferably less than the lowest peak mag~itude needed to change the val~re from on to off state3. The comparing means 127 has a ~ output state ~o long as the feedbac~ Yalue on line 99 is greater than X4, which i8 true if either the turnoi~ switeh 89 i~ turned on and conducting high current or both the turnof~ ~witch and t~e G~O ~alve 25 a~ turned o~ but i~ not true if the tumo* ~witch 89 i3 tumed on andl not co~ducting appreciable current. I~ the latter evellt, the com p~ring m eaIls output ha~ a low ~tato.
Ihe output of t~e comparing means 127 i~ coImected b~ mean~ of a line 126 to one i~put of the OR w3it 121. The tem~latch timer 123~ which 30 has a llormally lo~ output, i6 connected between the ou~I)ut line 96 of the logic meaIl~ 100 alld the ~eco~d input of the u~it 121. The l;imer 123 i~
~lar to the min~ ~mer 117 but i8 activa~ ~y a highto low tra~sition of ~he output Bi&pl~l 0~ ~bne 96. O~ce sc~vated,the timer 123 w ~l ~upply a high ~ al to th~ aecond input of the OR unit 121 for a predetermi~ed 35 r~lati-~ely shor/; nlBtCh-iXI" period of tiDle te.g., appro;~Lmately 30 micro-~cond~). Thu~ th0 outpu$ of the ~t 121 i~ in a b;gh ~tate du ing the WO 92/05636 ~ ~) '7 ~ pcr/us91/o5 temporary latch-in period a~er the OFF stat8 of the ~ignal on the output line 96 terminate~ or whenever ~he comparing means 127 ha~ a high output state, and otherwis~ it is low. The output state of unit 121 is conveyed by the line 120 to the not input of the logic unit 119. So long a~ thisS input is low, the output of the latter unit (i.e., the signal oh line 118) track the high and low 13tate~ of the signal on the line 115; otherw~se the signal on line 118 is low.
In operation, the ~ignal orl line 115 change~ from low to high in response to a high fault 13igI18l being supplied to the logic mean~ 93, which 10 event marks the stsrt of a GTO valve tumoff command. At the ~ame time the output of the min-of~ timer 117 changes frnm its normal low state to a high state which subsi~ts until the end of the aforementioned minimum in~erval. This temporary high output is coupled by the OR logic unit 116 to the output line 96 of the logic means 100, thereby turning on the turno~
15 switch 89 which conducts the negative gate cur~ent required to turn off the GTO valve 71 as prev~ou~ly described. When the switch 89 initially turn~
on, the voltage across it collapse~ to a negligible magnitude and the signal on the output line 126 of the comparing mean~ 127 changes firom high to low. Concurrently, the output of the OR unit 121 changes firom high to low, 20 and the un~t 119 causea the 5igIlal on line 118 to change !~rom low to high.
Thereafter the negative GTO gate current i~ the switch 8~ rapidly increases and SOOR e~cceed~ the thre5hold magl~itude at which the voltage ~eedback value o~ line 99 equa3~ ~4, whereupon the signal~ on line~ 126 and 120 respectively retur~ to their former high ~tates and the ~ignal on 25 line 118 temporarily retums to it6 former low Btate.
During a nor~al GTO turnoff proce~3, negatiYe gate t~o~ current sub~ide3 ~rom a high peak value to a tn~ial mag~tude, and the volts across the turno~ ~itc~ 89 will decrease to les~ th~ R4 before the end of th~ tail time of th~ valve 71. A~ ~uch voltage de~resses belo~ X4, ~he 30 ~ignal~ on lines 126 and 120 again change to their low 8tate~1 and the unit 119 concurrently c~s the 8igQal on line 118 to it~ higll atat~. The la~ter ~ignal i~ coupled b~ the OR unit 116 to the output line 96, thereby sustainis~g the OFF ~tate of t~e output ~ignal orl thia line a~er l;he output of the min-oflE
timer 117 au~omatic~lly revert~ to its low 8tate at the e~d of the mi~mum 35 int~r~ral. Througho~st thi8 normal turnof~ pFOCel~8, the output OI ~e temp la~ timer 123 wi~l be lo~.
: .
- , ' ~ ' ~ ~ 7 ~ P~T/US91/051û5 However, if th~ gate of the GTO valve 71 were shorted, negative gate current would not ~ubside during the attempted turn off proces~. In this event, the volts acro~s ths sw~tch $9 would not decrease below K4, the SigIlal9 on both lines 126 and 120 would remain hi~h, unit 119 would keep S the signal on its output line 11~ lo~, and the output Blg-ilal on line 96 would return to a low state as 800n a8 the output of the ~lin-off timer 117 returns to its normal, low state at the end of the minimum tu~off interval The resulting low signal on the output line 96 of the logic means 100 will bia3 the switch 89 to it~ off state, thereby removil-g tlhe low~resi~tance path that 10 thi~ switch would otherwi~e provide, if it ~ere not tulned o~, &om the gate of the GTO valve to the -13 ~volts control voltage termunal ~see FIG. 2) and causing the switch to stop conducting negative gate current. Interrupting negativ~ current in the shorted gate of the val~e 71 ~ll protect the switch 89 from damage caused by continuin~ to conduct high current af~er the 15 minimum turnof~inter~al expires. To ensure proper operation of the shorted gate de~ector in the illu trated embodiment of the invention, the minimum turnof~interral i5 approximately 80 microseconds. In e;f~ect, the min-o~ t;imer 117 delays the protective operation of the logic unit :l19 1mtil the end of the rninimum turnoflE interval fiollowing the ~tart of the aforesaid 20 valve turnoff command, thereby preventing a ~alse re~ponse to the tempQrsrily low signal on the line 118 during a normal GTO turnoff process and ensunng that the logic means 10t) continue~ to apply a high ~ignal ~ia it~ output line 96 to the turnof~ switch 89 throughout the ~imum turno~ interval.
AR soon as the output signal o~ line 96 changes from high to low in delayed response to the volts across the tur~of~ ntch 89 increaQing above K4 (wl~ch in tu~ cau~ed the high~ lo~ tran~itio~ of the ~ignal on the out;put li~e 118 o~l~e ~t 119 a8 descnbed above), the output of ~e temp-latch timer 123 Ch8Dge3 firom low to high. Thi~ ensure~ that the high si~nal OII line 120 and the lo~v ~ignal on line 118 ~nll both remain u~lchar~ged during th~ ensu~ng lateh-in pe~od, regardle~ of whether the ~ignal on lirle 126 is high or low. Thu~ the temp-latch ~n0r 123 inhibit3 unde~irable oscillation of the output 8ignal Oi~l lir~e 96 if the ou~ut ~ of ths oomparing me~ 127 ~vere to change fr~m high to lo~ du~ng ~uch 35 period. Such a cl~ vill occur when the turnof3~ al applied to tbe ~ralYa 71 i8 termi~ated and the gate vol~ge Ari2~g8~ ~egativ~ du~ to :;
, . . .. , ; ,. . . ~ , , 2~'7~
WO 92/05636 Pcr/US9l/0510 osc~llatory interaction of the snubber capacitance across the valve and the inherent inductanc~ in the gate circuit.
The detection of a ~hor~ed gat~ also causes a low-to-high state change of an output signal on a line 125 interconnecting the ]logic means 93 and 5 100. As jB showr. in FIC-. 3, the latter signal i~ providecl by a log~c unit 128 whose ~lrat input i~ connected to the line 115 snd 1whose not input is eonnected to the line 118. The signal on line 118 wouldl be low if a shorted GTO gate were de~ected while the 5i~al on line 115 i8 hi~h (i.e., while turno~ of the GTO valve i~ being commanded). In this event, the unit 128 i8 10 effective to provide a high output sigr~al on line 125. The logic means 93 includes suitable meaIlY for msintair~ing a low status signal on the line 81 throughout the delsy period provided by the prenously mentioned off-pulse timer or ~vhenever the signal on line 125 is high. It will ~e obser~ed that during the previou~ly described normal turnof~process of ~e GTO valve 71 15 the output of the comparing means 127 is high, due to the voltage feedback ~value on the line 99 temporarily rising above K4, for a short period of time during which the unit 1~8 w~ll provide a high output signal on the line 125 even though there i8 no ~horted gate. In 80me application~ of the inYentio~
this temporary high signal on line 125 duri}2g a normal GTO turnoff 20 process may provide 8 useful indication that such turnof~ proce8s i3 taking place.
While only o~ embodiment of the invention has been ~hown and de~cribed rby way of e~ample, many modifioation3 will undollbtedly occur to per~on~ ~lcilled in the art. The concluding claims are therefor~ intended to 25 cover all such modifications that fall within the kue spirit and ~oope of the inventio~.
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Claims (12)
1. Improved means for responding to a shorted gate in a gate turnoff thyristor to which alternative turn on and turnoff signals are applied, the turnoff signal being supplied by means of a controllable switch connected between the gate electrode of the thyristor and a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, the controllable switch having a control terminal coupled to control means that in normal operation causes the switch to conduct negative gate current from the thyristor gate to the control voltage terminal in response to a thyristor turnoff command and to not conduct such current in response to a thyristor turn on command, the improvement comprising:
a) first means coupled to said controllable switch and having alternative first and second output states, said first output state being true if negative gate current being conducted by said switch exceeds a predetermined threshold magnitude that is greater than the magnitude normally conducted after the thyristor is turned off, and said second output state being true otherwise;
b) second means associated with said control means and operative to cause said switch to stop conducting negative gate current in response to said first output state of said first means being true; and c) third means also associated with said control means for delaying operation of said second means until the end of a predetermined internal following the start of said thyristor turnoff command, thereby ensuring that the control means continues to cause said switch to conduct negative gate current throughout said interval.
a) first means coupled to said controllable switch and having alternative first and second output states, said first output state being true if negative gate current being conducted by said switch exceeds a predetermined threshold magnitude that is greater than the magnitude normally conducted after the thyristor is turned off, and said second output state being true otherwise;
b) second means associated with said control means and operative to cause said switch to stop conducting negative gate current in response to said first output state of said first means being true; and c) third means also associated with said control means for delaying operation of said second means until the end of a predetermined internal following the start of said thyristor turnoff command, thereby ensuring that the control means continues to cause said switch to conduct negative gate current throughout said interval.
2. The improvement of claim 1, in which said controllable switch is a parallel array of field effect transistors arranged to operate in unison.
3. The improvement of claim 1, in which and first means comprises voltage comparing means the first output state of which is true only when the voltage across said controllable switch exceeds a predetermined magnitude that is attained whenever the magnitude of negative gate current being conducted by said switch equals said threshold magnitude.
4. The improvement of claim 1 and further comprising fourth means responsive to operation of said second means for ensuring that said second means remains operative for at least a predetermined period of time regardless of the output state of said first means during such period.
5. The improvement of claim 1, in which said predetermined threshold magnitude is less than the lowest peak magnitude of negative gate current needed to turn off the thyristor.
6. Improved means for responding to a shorted gate in a gate turnoff thyristor to which alternative turn on and turnoff signals are applied, the turnoff signal being supplied by means of a controllable switch connected between the gate electrode of the thyristor and a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, the controllable switch having a control terminal coupled to control means that in normal operation causes the switch to conduct negative gate current from the thyristor gate to the control voltage terminal in response to a thyristor turnoff command and to not conduct such current in response to a thyristor turn on command, the improvement comprising:
a) first means coupled to said controllable switch and having alternative first and second output states, said first output state being true if the voltage across the switch exceeds a predetermined magnitude and said second output state being true otherwise, said predetermined magnitude being attained whenever the switch is conducting negative gate current of relatively high magnitude;
b) second means associated with said control means and operative to cause said switch to stop conducting negative gate current in response to said first output state of said first means being true; and c) third means also associated with said control means for delaying operation of said second means until the end of a predetermined internal following the start of said thyristor turnoff command, thereby ensuring that the control means continues to cause said switch to conduct negative gate current throughout said interval.
a) first means coupled to said controllable switch and having alternative first and second output states, said first output state being true if the voltage across the switch exceeds a predetermined magnitude and said second output state being true otherwise, said predetermined magnitude being attained whenever the switch is conducting negative gate current of relatively high magnitude;
b) second means associated with said control means and operative to cause said switch to stop conducting negative gate current in response to said first output state of said first means being true; and c) third means also associated with said control means for delaying operation of said second means until the end of a predetermined internal following the start of said thyristor turnoff command, thereby ensuring that the control means continues to cause said switch to conduct negative gate current throughout said interval.
7. In combination:
a) a gate turnoff thyristor connected between a source of electric power and an electrical load circuit and having alternative first and second states, said thyristor in its first state having negligible resistance in the path of load current and in its second state being effective to decouple said source from said load circuit;
b) control means for changing said thyristor from first to second states in response to a turnoff command being received by said control means and for returning said thyristor to its first state in response to an alternative turn on command being received;
c) said control means including a controllable switch connected between the gate electrode of said thyristor and a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, said controllable switch in normal operation conducting negative gate current from the thyristor gate to the control voltage terminal in response to said turnoff command and not conducting such current in response to said turn on command;
d) comprising means coupled to said controllable switch and having alternative first and second output states, said first output state being true if the voltage across the switch exceeds a predetermined magnitude and said second output state being true otherwise, said predetermined magnitude being attained only when negative gate current being conducted by said switch has a threshold magnitude that is greater than the magnitude normally conducted when said thyristor is in its second state; and e) logic means coupled to said comparing means and effective only when said control means is receiving said turnoff command for indicating whether or not said first output state of said comparing means is true.
a) a gate turnoff thyristor connected between a source of electric power and an electrical load circuit and having alternative first and second states, said thyristor in its first state having negligible resistance in the path of load current and in its second state being effective to decouple said source from said load circuit;
b) control means for changing said thyristor from first to second states in response to a turnoff command being received by said control means and for returning said thyristor to its first state in response to an alternative turn on command being received;
c) said control means including a controllable switch connected between the gate electrode of said thyristor and a control voltage terminal having a negative potential with respect to the cathode potential of the thyristor, said controllable switch in normal operation conducting negative gate current from the thyristor gate to the control voltage terminal in response to said turnoff command and not conducting such current in response to said turn on command;
d) comprising means coupled to said controllable switch and having alternative first and second output states, said first output state being true if the voltage across the switch exceeds a predetermined magnitude and said second output state being true otherwise, said predetermined magnitude being attained only when negative gate current being conducted by said switch has a threshold magnitude that is greater than the magnitude normally conducted when said thyristor is in its second state; and e) logic means coupled to said comparing means and effective only when said control means is receiving said turnoff command for indicating whether or not said first output state of said comparing means is true.
8. The combination of claim 7 and further comprising timer means for ensuring that the controllable switch continues to conduct negative gate current during a predetermined interval of time following the start of the turnoff command, and additional means operative at the end of said interval for causing the switch to stop conducting negative gate current if the first output state of said comparing means is then true.
9. The combination of claim 8 and further comprising means responsive to operation of said additional means for ensuring that said additional means remains operative for at least a predetermined period of time regardless of the output state of said comparing means during such period.
10. An improved method for responding to a turn-off failure of a gate turnoff thyristor having an anode, a cathode, and a gate electrode, the gate electrode being connected by means of a controllable switch to a control voltage terminal having a negative potential with respect to the thyristor's cathode potential, comprising the steps of:
a) normally responding to a thyristor turnoff command by turning on the controllable switch;
b) detecting when the switch is conducting gate command by relatively high magnitude; and c) indicating the coexistence of high gate current and the thyristor turnoff command.
a) normally responding to a thyristor turnoff command by turning on the controllable switch;
b) detecting when the switch is conducting gate command by relatively high magnitude; and c) indicating the coexistence of high gate current and the thyristor turnoff command.
11. The improvement of claim 10 comprising the additional steps of preventing any turn off of the controllable switch during a predetermined interval of time following the start of the thyristor turnoff command, and turning off the switch if high gate current is detected at the end of said interval.
12. The improvement of claim 10, in which the detecting step comprises comparing the magnitude of voltage across the controllable switch with a predetermined magnitude that is attained whenever the magnitude of gate current being conducted by the switch equals a threshold magnitude that is less than the peak magnitude needed to turn off the thyristor but greater than the magnitude conducted after the thyristor is successfully turned off.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58454190A | 1990-09-18 | 1990-09-18 | |
| US584,541 | 1990-09-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2071890A1 true CA2071890A1 (en) | 1992-03-19 |
Family
ID=24337743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002071890A Abandoned CA2071890A1 (en) | 1990-09-18 | 1991-07-19 | Gate turnoff thyristor control circuit with shorted gate detection |
Country Status (6)
| Country | Link |
|---|---|
| AU (1) | AU645830B2 (en) |
| BR (1) | BR9106076A (en) |
| CA (1) | CA2071890A1 (en) |
| MX (1) | MX9101114A (en) |
| NZ (1) | NZ239811A (en) |
| WO (1) | WO1992005636A1 (en) |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5932012B2 (en) * | 1978-08-24 | 1984-08-06 | 株式会社東芝 | Gate drive device for gate turn-off thyristor |
| JPS57162964A (en) * | 1981-03-31 | 1982-10-06 | Toshiba Corp | Protecting device for gate turn-off thyristor |
| JPS5893463A (en) * | 1981-11-30 | 1983-06-03 | Hitachi Ltd | Gate circuit for gate turn-off thyristor |
| US4597038A (en) * | 1984-07-26 | 1986-06-24 | Westinghouse Electric Corp. | Switching overlap protection by control gate impedance monitoring |
| DE3537050A1 (en) * | 1985-06-19 | 1987-01-02 | Siemens Ag | METHOD AND DEVICE FOR DETECTING THE LOCKED STATE OF A DISABLED THYRISTOR |
| DE3619740A1 (en) * | 1986-06-12 | 1987-12-17 | Bbc Brown Boveri & Cie | Method and arrangement for protecting gate-turn-off thyristors |
-
1991
- 1991-07-19 WO PCT/US1991/005105 patent/WO1992005636A1/en active Application Filing
- 1991-07-19 BR BR919106076A patent/BR9106076A/en not_active IP Right Cessation
- 1991-07-19 CA CA002071890A patent/CA2071890A1/en not_active Abandoned
- 1991-07-19 AU AU82905/91A patent/AU645830B2/en not_active Ceased
- 1991-09-16 NZ NZ23981191A patent/NZ239811A/en unknown
- 1991-09-17 MX MX9101114A patent/MX9101114A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| AU8290591A (en) | 1992-04-15 |
| WO1992005636A1 (en) | 1992-04-02 |
| NZ239811A (en) | 1994-04-27 |
| AU645830B2 (en) | 1994-01-27 |
| BR9106076A (en) | 1993-02-02 |
| MX9101114A (en) | 1992-05-04 |
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| Date | Code | Title | Description |
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| EEER | Examination request | ||
| FZDE | Dead |