CA2069911A1 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- CA2069911A1 CA2069911A1 CA 2069911 CA2069911A CA2069911A1 CA 2069911 A1 CA2069911 A1 CA 2069911A1 CA 2069911 CA2069911 CA 2069911 CA 2069911 A CA2069911 A CA 2069911A CA 2069911 A1 CA2069911 A1 CA 2069911A1
- Authority
- CA
- Canada
- Prior art keywords
- transistor
- transistors
- source
- semiconductor device
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000005669 field effect Effects 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 12
- 239000002800 charge carrier Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013642 negative control Substances 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000136 polysorbate Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Abstract
ABSTRACT
A semiconductor device, preferably for switching purposes, has a first field effect transistor (31, 32, 33) of enhancement type provided on a substrate (1). The transistor is separated from the substrate by an electrically insulating layer (2). On the transistor an insulating layer (9) is arranged and on this layer a second field effect transistor (51, 52, 53) is provided. The transistors are arranged such that their channel regions (32, 52) cover each other. The source regions (31, 51) and drain regions (33, 53) of the transistors have contacts (311, 511; 331, 531) for connection of control voltages between the source regions mutually and between the drain regions mutually. The transistors are of enhancement type.
One of the transistors is of N-type (N-conducting type) and the other transistor is of P-type (P-conducting type). By applying control voltages between the two source contacts mutually and the two drain contacts mutually and of such polarity that the transistor of P-type becomes positive in relation to the transistor of N-type, conducting channels are produced in the confronting surfaces of the channel regions, and the transistors change into conducting state.
Further, the component has connections (312, 332) for connection of a load circuit. (Fig. 1)
A semiconductor device, preferably for switching purposes, has a first field effect transistor (31, 32, 33) of enhancement type provided on a substrate (1). The transistor is separated from the substrate by an electrically insulating layer (2). On the transistor an insulating layer (9) is arranged and on this layer a second field effect transistor (51, 52, 53) is provided. The transistors are arranged such that their channel regions (32, 52) cover each other. The source regions (31, 51) and drain regions (33, 53) of the transistors have contacts (311, 511; 331, 531) for connection of control voltages between the source regions mutually and between the drain regions mutually. The transistors are of enhancement type.
One of the transistors is of N-type (N-conducting type) and the other transistor is of P-type (P-conducting type). By applying control voltages between the two source contacts mutually and the two drain contacts mutually and of such polarity that the transistor of P-type becomes positive in relation to the transistor of N-type, conducting channels are produced in the confronting surfaces of the channel regions, and the transistors change into conducting state.
Further, the component has connections (312, 332) for connection of a load circuit. (Fig. 1)
Description
,9 Serniconductor device TECHNICAL FIELD
The present lnvention relates to a semiconductor device comprising a first field efEect transistor of a first conductivity type, which transistor is arranged in a semiconductor body and has a source region provided with a source connection, a drain region provided with a drain connection, a channel region arranged between the source and drain regions, and members for creating a conducting channel in the channel region between the source and drain regions.
The invention relates in particular to a so-called semiconductor switch for use as a switching member.
BACKGROUND ART
It is previously known to use field effect -transistors of MOS type as switching members. Such a transistor may be given low on-state resistance. However, the very limited maximum permissible voltage of the insulating layer located between the control electrode of the transistor and its channel region limits the maximum voltage, at which a conventional MOS transistor may be used, to low values.
From Swedish published patent application 460 448 a semiconductor device of MOS type, intended for switching purposes, is already known. A device of this kind may be designed for considerably higher working voltage than a conventional MOS transistor. The maximally attainable charge carrier density in the channel region of the transistor during the conducting state of the transistor is, however, limited, which entails a higher on-state resistance of such a device than in a conventional MOS transistor.
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i.
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SUMMARY OE IHE INVENTION z~ 3~ ~
The present invention aims to provide a semiconductor device of the kind mentioned in the introductory part of the specification, which simultaneously exhibits a high power handling capacity per unit of surface and a high speed of action. To attain a high power handling capacity per unit of surface, both the abiIity to withstand a high off-state voltage and a low on-state resistance are required. This purpose is attained to a high degree with a semiconductor device according to the invention.
What characterizes such a device will be clear from the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the invention will be described with reference to the accompanying Figures 1-7. Figure 1 shows the fundamental configuration of a device according to the invention. Figure 2 schematically shows how a device according to the invention may be connected to control and load circuits. Figure 3 shows how the two transistors in a device according to the invention may be provided with so-called stop zones at the ends of the channel regions.
Figure 4 shows an alternative embodiment with one single stop zone for each transistor. Figures 5a and 5b show how, according to two alternative embodiments of the invention, control signals are supplied to the device and how members for generation of suitable control voltages are integrated with the device. Figure 6 shows an alternative embodiment in which the substrate consists of a silicon wafer, in which the lower of the two transistors of the device is produced.
Figures 7a, 7b, 7c and 7d show successive steps in one example of a method for the manufacture of a device according to the invention.
- ~, , , :.-.-:
DESCRIPTION OF THE PREFEE~R~D ~MBODIMENIS
Figure 1 shows a semiconductor device according to the invention. The device is arranged on a substrate 1 in the form of a silicon wafer. On the wafer an electrically insulating silicon dioxide layer 2 is produced, which separates the device from the substrate. On the surface of the silicon dioxide layer 2 a monoc:rys-talline silicon layer 3 is applied, in which a first field effect transistor is produced. The transistor has an N+--doped source region 31, a P-doped channel region 32 and an N+-doped drain region 33.
The source regi.on is provided with a connection contact 311 and a lead 312. The drain region is provided in similar manner with a contact 331 and a lead 332. On the surface of the silicon layer 3 an electrically insulating silicon dioxide layer 4 is arranged, and on top of this a second monocrystalline silicon layer 5 is arranged. In the latter silicon layer a second field effect transistor is produced, which has the P+-doped source region 51, the N-doped channel region 52 and the P+-doped drain region 53. The source region is provided with a contact 511 and a lead 512, and the drain region is provided with a contact 531 and a lead 532. The two field effect transistors are of enhancement type. In the lower field effect transistor 31-33 the source and drain regions are of N-type and the transistor is a so-called NMOS transistor. In the upper transistor 51-53 the source and drain regions are of P-type and the transistor is a so-called PMOS transistor.
The silicon dioxide layer 2 should have a thickness of at least 1 ~m and preferably has, at least at higher working voltages, a thickness of 5-10 ~m. The silicon layers 3 and 5 may have a thickness of 60 nm and the silicon dioxide layer 4 a thickness of 20 nm. The length of the channel regions of the field effect transistors (the distance between the source and drain contact of a transistor) depends on the working voltage for which the device is intended. The length may preferably lie within the interval , ~, :, , . , :
. . , , , ~ . :
10-100 ~m. At a maximum off-state voltage of, for example, 160 V, the length of the channel regions may be 18 ~lm and at a working voltage of 300 V it may be 30-50 ~m. The doping of the source and drain regions of the transistors may be within the interval 101~-1020 cm~3 and of their channel regions within the interval 10l5-1017 cm~3.
The channel regions should be formeci such that charge balance prevails between these two regions. This means that the number of doping atoms per unit of surface should be the same for both regions, i.e. that the product of layer thickness and impurity concentration per unit of volulne should be the same.
As will be clear from Figure 1, -the channel region 32 of the lower transistor has a somewhat greater length than the channel region 52 of the upper transistor. Also other embodiments are possible, and, for example, in the manner shown in dashed lines a and b, the source and drain regions of the lower transistor may be extended inwards towards the channel region so that the length thereof is the same as the length of the channel region of the upper transistor.
The width of the the channel regions ~their extent perpendicular to the plane of the paper in Figure 1) is adapted in a suitable manner in dependence on the desired current handling capacity of the component. Possibly, in order to achieve the desired current handling capacity, a plurality of components may be connected in parallel.
Alternatively, the component according to the invention may be arranged on an electrically insulating substrate, for example a sapphire plate. The oxide laye 2 may then be considerably thinner than what has been stated above.
According to another embodiment, the thick silicon dioxide layer 2 may be replaced by a polycrystalline diamond layer , ~ .
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The present lnvention relates to a semiconductor device comprising a first field efEect transistor of a first conductivity type, which transistor is arranged in a semiconductor body and has a source region provided with a source connection, a drain region provided with a drain connection, a channel region arranged between the source and drain regions, and members for creating a conducting channel in the channel region between the source and drain regions.
The invention relates in particular to a so-called semiconductor switch for use as a switching member.
BACKGROUND ART
It is previously known to use field effect -transistors of MOS type as switching members. Such a transistor may be given low on-state resistance. However, the very limited maximum permissible voltage of the insulating layer located between the control electrode of the transistor and its channel region limits the maximum voltage, at which a conventional MOS transistor may be used, to low values.
From Swedish published patent application 460 448 a semiconductor device of MOS type, intended for switching purposes, is already known. A device of this kind may be designed for considerably higher working voltage than a conventional MOS transistor. The maximally attainable charge carrier density in the channel region of the transistor during the conducting state of the transistor is, however, limited, which entails a higher on-state resistance of such a device than in a conventional MOS transistor.
. .
i.
. .
.. ..
SUMMARY OE IHE INVENTION z~ 3~ ~
The present invention aims to provide a semiconductor device of the kind mentioned in the introductory part of the specification, which simultaneously exhibits a high power handling capacity per unit of surface and a high speed of action. To attain a high power handling capacity per unit of surface, both the abiIity to withstand a high off-state voltage and a low on-state resistance are required. This purpose is attained to a high degree with a semiconductor device according to the invention.
What characterizes such a device will be clear from the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
In the following the invention will be described with reference to the accompanying Figures 1-7. Figure 1 shows the fundamental configuration of a device according to the invention. Figure 2 schematically shows how a device according to the invention may be connected to control and load circuits. Figure 3 shows how the two transistors in a device according to the invention may be provided with so-called stop zones at the ends of the channel regions.
Figure 4 shows an alternative embodiment with one single stop zone for each transistor. Figures 5a and 5b show how, according to two alternative embodiments of the invention, control signals are supplied to the device and how members for generation of suitable control voltages are integrated with the device. Figure 6 shows an alternative embodiment in which the substrate consists of a silicon wafer, in which the lower of the two transistors of the device is produced.
Figures 7a, 7b, 7c and 7d show successive steps in one example of a method for the manufacture of a device according to the invention.
- ~, , , :.-.-:
DESCRIPTION OF THE PREFEE~R~D ~MBODIMENIS
Figure 1 shows a semiconductor device according to the invention. The device is arranged on a substrate 1 in the form of a silicon wafer. On the wafer an electrically insulating silicon dioxide layer 2 is produced, which separates the device from the substrate. On the surface of the silicon dioxide layer 2 a monoc:rys-talline silicon layer 3 is applied, in which a first field effect transistor is produced. The transistor has an N+--doped source region 31, a P-doped channel region 32 and an N+-doped drain region 33.
The source regi.on is provided with a connection contact 311 and a lead 312. The drain region is provided in similar manner with a contact 331 and a lead 332. On the surface of the silicon layer 3 an electrically insulating silicon dioxide layer 4 is arranged, and on top of this a second monocrystalline silicon layer 5 is arranged. In the latter silicon layer a second field effect transistor is produced, which has the P+-doped source region 51, the N-doped channel region 52 and the P+-doped drain region 53. The source region is provided with a contact 511 and a lead 512, and the drain region is provided with a contact 531 and a lead 532. The two field effect transistors are of enhancement type. In the lower field effect transistor 31-33 the source and drain regions are of N-type and the transistor is a so-called NMOS transistor. In the upper transistor 51-53 the source and drain regions are of P-type and the transistor is a so-called PMOS transistor.
The silicon dioxide layer 2 should have a thickness of at least 1 ~m and preferably has, at least at higher working voltages, a thickness of 5-10 ~m. The silicon layers 3 and 5 may have a thickness of 60 nm and the silicon dioxide layer 4 a thickness of 20 nm. The length of the channel regions of the field effect transistors (the distance between the source and drain contact of a transistor) depends on the working voltage for which the device is intended. The length may preferably lie within the interval , ~, :, , . , :
. . , , , ~ . :
10-100 ~m. At a maximum off-state voltage of, for example, 160 V, the length of the channel regions may be 18 ~lm and at a working voltage of 300 V it may be 30-50 ~m. The doping of the source and drain regions of the transistors may be within the interval 101~-1020 cm~3 and of their channel regions within the interval 10l5-1017 cm~3.
The channel regions should be formeci such that charge balance prevails between these two regions. This means that the number of doping atoms per unit of surface should be the same for both regions, i.e. that the product of layer thickness and impurity concentration per unit of volulne should be the same.
As will be clear from Figure 1, -the channel region 32 of the lower transistor has a somewhat greater length than the channel region 52 of the upper transistor. Also other embodiments are possible, and, for example, in the manner shown in dashed lines a and b, the source and drain regions of the lower transistor may be extended inwards towards the channel region so that the length thereof is the same as the length of the channel region of the upper transistor.
The width of the the channel regions ~their extent perpendicular to the plane of the paper in Figure 1) is adapted in a suitable manner in dependence on the desired current handling capacity of the component. Possibly, in order to achieve the desired current handling capacity, a plurality of components may be connected in parallel.
Alternatively, the component according to the invention may be arranged on an electrically insulating substrate, for example a sapphire plate. The oxide laye 2 may then be considerably thinner than what has been stated above.
According to another embodiment, the thick silicon dioxide layer 2 may be replaced by a polycrystalline diamond layer , ~ .
~ , ~
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2~
arranged on a si].:icon substrate, on which diamond layer a thin silicon dioxide layer may be arranged.
Figure 2 shows the principle of how the component according to the invention is connected to a control and load circuit.
The component is schematically shown as being included in an integrated circuit A. In addition to the component shown in Figure 1, the circuit also comprises the resistors 61, 62 connected between the source connections 312, 512 and drain connections 532, 332, respectively, oE the -transistors. Ihe source connection 312 and drain connnection 332 o~ the lower transistor constitute the main connections of the circuit and are shown in Figure 2 eonnected into a schematic load circuit consisting of a voltage source 9 and a load object 10. Control voltage sources 71, 72 are connected between the source connections 312, 512 and the drain connections 332, 532, respectively, of the two transistors. The control voltage sources are switched on and off with the aid of switching members with the contacts 81, 82. The control voltage sources suitably supply equally large voltages.
In the position of the switching member 81, 82 shown in Figure 2, the supplied control voltage u is ~ero, and the source regions of the two transistors are kept at the same potential with the aid of the resistor 61, and the two drain regions are kept at mutually the same potential with the aid of -the resistor 62. With the polarity of the voltage source 9 shown in Figure 2, the junction of the lower transistor shown on the lefthand side in Figure 2 and the junction of the upper transistor shown on the righthand side in Figure 2 are blocking. Space charge regions are formed at the blocked junctions and absorb the applied voltage. Because of the relatively weaker doping of the channel regions, the extent of the space charge layers will be greatest in these regions, which take up the greater part of the applied voltage.
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When switching on the control voltage by closing the contacts 81, ~2, the control signal u will be equal to the voltage of the control voltage sources. ~he upper transistor is given a positive po-tentlal in relation to the lower one. The voltage of the control voltage sources and hence the potential difference between the two transistors may, for example, be 5 V. The potential difference causes a P-conducting channel to be induced in the channel region of the upper transistor nearest the insulating layer q, and an N-conducting channel to be induced in the channel region of the lower transistor nearest the insulating layer 4. Thus, the two transistors change from conducting state and a load current may flow from the voltage source 9 through the lower transistor and the load object 10. The two induced channels influence and strengthen each other, and a high charge carrier density may be obtained in the channels, typically 5X1012 - 1013 cm~2. This charge carrier density is considerably higher -than what has been possible to achieve in prior art components of the kind in question, for example in the component known from Swedish published patent application 460 448. This high charge carrier density imparts to the conducting channels high conductance, of the same order of magnitude as a conventional MOS transistor, and the component according to the invention therefore has low on-state resistance. At the same time, a component according to the invention is able, in non- conducting state, to take up high voltage be-tween the source and drain contacts, which is due to the weak doping in the channel regions and to the space charges in the channel regions on either side of the insulating layer 4 balancing each other.
A component according to the invention will therefore have a considerably higher power handling capacity per unit of surface than prior art MOS transistors. The power handling capacity approaches that of bipolar transis-tors, but a component according to the invention, because of the absence of minority charge carriers, has a considerably higher speed of action than a bipolar transistor.
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As mentioned above, in the non-conducting state one of the two junctions of a transistor is blocking. Because of the balanced dopin~s and the thin intermediate oxide, a space charge region, both in the upper and the lower transistor, extends from the drain region and up to the source region.
The applied voltage between the source and drain regions may then, at the source region, create an electric field which acts in an injecting manner. At a certain length of the channel region and a certain maximum applied voltage, therefore, the doping in the channel region must be so high that the injecting field does not reach to the opposite PN- -junction. This limits the maximum working voltage of the component. Figure 3 shows how this problem can be eliminated by providing the channel region nearest the source and drain regions with stop zones which have the same conductivity type as the channel region but higher doping than this. Figure 3 shows such an embodiment of a component according to the invention, and the stop zones are there designated 54, S5 and 34, 35, respectively. When the voltage applied across the component increases, the stop zone with its higher doping reduces the lateral field intensity so as to avoid injection. In such a component, the doping of the channel region may be made considerably weaker than in a component according to Figures 1 and 2. In Figure 3 this weaker doping has been designated v and ~, respectively. The weak doping of the channel regions causes the field intensity through the whole channel region to be high and approximately constant in non-conducting state, which makes possible a high working voltage of the component. In the embodiment of a component according to the invention shown in Figure 3, however, a maximum field intensity is obtained at the blocking junction, which limits the maximum voltage applied.
The disadvantage mentioned above may be eliminated with the aid of the embodiment shown in Figure 4. In this embodiment, each transistor has only one stop zone 35 and 54, respectively, and these are arranged at opposite ends of , , B ~ 3~
the channel regions. Whell a positive voltage is applied to the source regions 31, 51 of the transistors in relation to the drain regions 33, 53, the field intensity in the channel regions will be approximately constant and equal to the maximum field intensity occurring in the component. This results in a very good voltage-absorbing capacity of the component. However, this is only true at the polarity of the applied voltage just mentioned. To make possible a high voltage-absorbing capacity in both directions, therefore, two oppositely directed components according to Figure 9 may be connected in series.
In the embodiment of the invention described above, the applied control voltage is zero in non-conducting state.
Alternatively, a negative control voltage may be applied during this interval. A negative control voltage between the two transistor systems also suppresses the injection.
The need of stop layers and their degree of doping may thus be optimi~ed with respect to the degree oE negative control voltage when the switch is to be non-conducting.
In a semiconductor device according to the invention, the doping profiles of the channel regions should preferably be such tha-t the potentials in the two channel regions accompany each other, i.e. that within the entire extent of -the channel regions the potentials of the two points in each arbitrary pair of oppositely positioned points in the two channel regions are equal or as equal as possible. In this way voltage stresses across the insulating layer 4, other than those caused by the control voltage, are avoided. This can be achieved, for example, by making the doping of the channel regions low, as in the components shown in Figures 3 and 4. The field intensity in each channel region will then be approximately constant and the potential in each channel region varies linearly between the source and drain regions.
This entails the desirable equality of potential between the two points of each pair of two oppositely located points of the two channel regions.
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Figure 5a shows how, in an embodiment of the invention, members for supplying control voltages are integrated with the actual component. The component A thus consists of an integrated circuit which, in addition to the two field effect transistors, also comprises the resistors 61, 62 and two diode bridges 11, 12. The component has connections B, C for the load current. When the component is -to be brought into conducting state, the connections 17, 18 are supplied with an alternating voltage signal s. This is supplied to the rectifier bridges via capacitors 13, 14 and 15, 16, respectively. From the diode bridges the direct voltages u are then obtained, which, in the manner described above, control the component to conducting state.
Figure 5b shows an alternative embodiment of the device according to Figure Sa. The integra-ted circuit A comprises, in addition to the two field effect transistors, two sets of rectifier bridges, namely lla, llb and 12a, 12b, respectively, and two sets of inverters, namely Ila, Ilb, Ilc and I2a, I2b, I2c, respectively. The bridges lla, 12a are supplied with a constant alternating voltage P via the connections 17a, 17b and the capacitors 13a, 13b, 15a, 15b, for example o~ such an amplitude that the bridges deliver direct voltages of the order of magnitude 5 V. These direct voltages are supplied to the inverters as supply voltages.
When the component is to be conducting, a control signal in the form of an alternating voltage S is supplied to the control connections 18a, 18b. This causes a control direct voltage to be generated across the resistors 61a, 62a, which makes the output signals of the inverters Ila and I2a "low"
and of the inverters Ilb and I2b "high", i.e. the control voltages "u" become positive and the component becomes conducting and is maintained conducting for as long as the control signal S is supplied. When the control signal S is removed, the output voltage from the bridges llb, 12b becomes zero, the output signals from the inverters Ila and I2a become "high" and from the inverters Ilb and I2b "low", - , .
', : ~':. , : , : ~ , ~i :
. , and the control voltages "u" become negative. The component becomes non-conducting and the negative control voltage "u"
suppresses injection and thus increases the maximum permissible voltage of the component.
In the embodiments of the invention described above, both the field effect transistors are produced in thin semiconductor layers of which -the lower is arranged on an electrically insulating layer located on a substrate.
Figure 6 shows an alternative embodiment oE the invention, in which the lower transistor is produced directly in the substrate, which consists of a monocrystalline silicon body 1. At the lower transistor this body has a P-doped zone 32a, which constitutes the channel region of the transistor.
In this zone N-conducting regions 31a, 33a are produced, which constitute the source and drain regions of the transistor. Otherwise, the component is formed in the manner previously described.
A component accord.ing to the invention may be manufactured in a plurality of different ways. A preferred method of manufacture will be described in the following with reference to Figure 7. In a monocrystalline silicon wafer X
there are generated, by ion implantation of oxyqen and nitrogen, respectively, through the upper surface of the wafer in the figure, a silicon dioxide layer 101 and a silicon nitrode layer 102 (SiXNy). Those parts, 104, 105, 106, of the silicon body which are positioned outside the two layers just mentioned are not influenced by this treatment. Fiqure 7a shows the silicon body after the ion implantation. Thereafter there is generated, by some known method (e.g. thermal oxidation and/or deposition), a silicon dioxide layer 103 on the surface of the body, which is shown in Figure 7b. Figure 7c shows the silicon body X turned upside down. A second body Y of monocrystalline silicon has been provided, in a similar known manner, wi-th a silicon dioxide layer 201 on its surface. The two bodies are brought toqether in the manner indicated by the arrow in ': ,'', ~ :
-: .:
~' ~ ~ ,,;; ' :
Figure 7c. Even at room temperature a bonding then takes place between the plates. The bonding may be reinforced by a heat treatment in the temperature range ~00-1000C. By a subsequent treatment by etching, part 106 of the silicon body X is etched away, the nitride layer 102 then serving as stop layer during the etching. Then the nitride layer 102 is etched away. The body thus manufactured is shown in Figure 7d. The silicon body Y constitutes a substrate; the silicon dioxide layers 201 and 103 form an electrically insulating layer between the substrate and the semiconductor component according to the invention; in the monocrystalline thin silicon layer 109 the lower transistor of the component is produced; the silicon dioxide layer 101 serves as electrical insulation between the two transistors of the component; and in the upper monocrystalline silicon layer 105 the upper transistors of the component are produced.
The desired doping of the different regions of the transistors may, for example, be made with the aid of ion implantation, either after the manufacturing steps described above, or earlier during the manufacturing process.
The component according to the invention has been described above as a semiconductor switch for use as switching member.
The component may have other fields of use as well, for example as a controllable element in integrated digital circuits. Besides as switching member, the component may also be used for stepless control in analog circuits.
In Figure 2, the output circuit of the component consists of a voltage source and a load object. However, the output circuit may be of an arbitrary kind, for example a digital or analog circuit element or circuit.
.
:, . ~, : ~ . .:
: : .,,, ~ ' '
arranged on a si].:icon substrate, on which diamond layer a thin silicon dioxide layer may be arranged.
Figure 2 shows the principle of how the component according to the invention is connected to a control and load circuit.
The component is schematically shown as being included in an integrated circuit A. In addition to the component shown in Figure 1, the circuit also comprises the resistors 61, 62 connected between the source connections 312, 512 and drain connections 532, 332, respectively, oE the -transistors. Ihe source connection 312 and drain connnection 332 o~ the lower transistor constitute the main connections of the circuit and are shown in Figure 2 eonnected into a schematic load circuit consisting of a voltage source 9 and a load object 10. Control voltage sources 71, 72 are connected between the source connections 312, 512 and the drain connections 332, 532, respectively, of the two transistors. The control voltage sources are switched on and off with the aid of switching members with the contacts 81, 82. The control voltage sources suitably supply equally large voltages.
In the position of the switching member 81, 82 shown in Figure 2, the supplied control voltage u is ~ero, and the source regions of the two transistors are kept at the same potential with the aid of the resistor 61, and the two drain regions are kept at mutually the same potential with the aid of -the resistor 62. With the polarity of the voltage source 9 shown in Figure 2, the junction of the lower transistor shown on the lefthand side in Figure 2 and the junction of the upper transistor shown on the righthand side in Figure 2 are blocking. Space charge regions are formed at the blocked junctions and absorb the applied voltage. Because of the relatively weaker doping of the channel regions, the extent of the space charge layers will be greatest in these regions, which take up the greater part of the applied voltage.
.
, ~ : . . .:
~: -; . , :: ,.
. '. . ,~
When switching on the control voltage by closing the contacts 81, ~2, the control signal u will be equal to the voltage of the control voltage sources. ~he upper transistor is given a positive po-tentlal in relation to the lower one. The voltage of the control voltage sources and hence the potential difference between the two transistors may, for example, be 5 V. The potential difference causes a P-conducting channel to be induced in the channel region of the upper transistor nearest the insulating layer q, and an N-conducting channel to be induced in the channel region of the lower transistor nearest the insulating layer 4. Thus, the two transistors change from conducting state and a load current may flow from the voltage source 9 through the lower transistor and the load object 10. The two induced channels influence and strengthen each other, and a high charge carrier density may be obtained in the channels, typically 5X1012 - 1013 cm~2. This charge carrier density is considerably higher -than what has been possible to achieve in prior art components of the kind in question, for example in the component known from Swedish published patent application 460 448. This high charge carrier density imparts to the conducting channels high conductance, of the same order of magnitude as a conventional MOS transistor, and the component according to the invention therefore has low on-state resistance. At the same time, a component according to the invention is able, in non- conducting state, to take up high voltage be-tween the source and drain contacts, which is due to the weak doping in the channel regions and to the space charges in the channel regions on either side of the insulating layer 4 balancing each other.
A component according to the invention will therefore have a considerably higher power handling capacity per unit of surface than prior art MOS transistors. The power handling capacity approaches that of bipolar transis-tors, but a component according to the invention, because of the absence of minority charge carriers, has a considerably higher speed of action than a bipolar transistor.
'~ .
.
~r~ 3~3~
As mentioned above, in the non-conducting state one of the two junctions of a transistor is blocking. Because of the balanced dopin~s and the thin intermediate oxide, a space charge region, both in the upper and the lower transistor, extends from the drain region and up to the source region.
The applied voltage between the source and drain regions may then, at the source region, create an electric field which acts in an injecting manner. At a certain length of the channel region and a certain maximum applied voltage, therefore, the doping in the channel region must be so high that the injecting field does not reach to the opposite PN- -junction. This limits the maximum working voltage of the component. Figure 3 shows how this problem can be eliminated by providing the channel region nearest the source and drain regions with stop zones which have the same conductivity type as the channel region but higher doping than this. Figure 3 shows such an embodiment of a component according to the invention, and the stop zones are there designated 54, S5 and 34, 35, respectively. When the voltage applied across the component increases, the stop zone with its higher doping reduces the lateral field intensity so as to avoid injection. In such a component, the doping of the channel region may be made considerably weaker than in a component according to Figures 1 and 2. In Figure 3 this weaker doping has been designated v and ~, respectively. The weak doping of the channel regions causes the field intensity through the whole channel region to be high and approximately constant in non-conducting state, which makes possible a high working voltage of the component. In the embodiment of a component according to the invention shown in Figure 3, however, a maximum field intensity is obtained at the blocking junction, which limits the maximum voltage applied.
The disadvantage mentioned above may be eliminated with the aid of the embodiment shown in Figure 4. In this embodiment, each transistor has only one stop zone 35 and 54, respectively, and these are arranged at opposite ends of , , B ~ 3~
the channel regions. Whell a positive voltage is applied to the source regions 31, 51 of the transistors in relation to the drain regions 33, 53, the field intensity in the channel regions will be approximately constant and equal to the maximum field intensity occurring in the component. This results in a very good voltage-absorbing capacity of the component. However, this is only true at the polarity of the applied voltage just mentioned. To make possible a high voltage-absorbing capacity in both directions, therefore, two oppositely directed components according to Figure 9 may be connected in series.
In the embodiment of the invention described above, the applied control voltage is zero in non-conducting state.
Alternatively, a negative control voltage may be applied during this interval. A negative control voltage between the two transistor systems also suppresses the injection.
The need of stop layers and their degree of doping may thus be optimi~ed with respect to the degree oE negative control voltage when the switch is to be non-conducting.
In a semiconductor device according to the invention, the doping profiles of the channel regions should preferably be such tha-t the potentials in the two channel regions accompany each other, i.e. that within the entire extent of -the channel regions the potentials of the two points in each arbitrary pair of oppositely positioned points in the two channel regions are equal or as equal as possible. In this way voltage stresses across the insulating layer 4, other than those caused by the control voltage, are avoided. This can be achieved, for example, by making the doping of the channel regions low, as in the components shown in Figures 3 and 4. The field intensity in each channel region will then be approximately constant and the potential in each channel region varies linearly between the source and drain regions.
This entails the desirable equality of potential between the two points of each pair of two oppositely located points of the two channel regions.
' ' ~?~iC.3~
Figure 5a shows how, in an embodiment of the invention, members for supplying control voltages are integrated with the actual component. The component A thus consists of an integrated circuit which, in addition to the two field effect transistors, also comprises the resistors 61, 62 and two diode bridges 11, 12. The component has connections B, C for the load current. When the component is -to be brought into conducting state, the connections 17, 18 are supplied with an alternating voltage signal s. This is supplied to the rectifier bridges via capacitors 13, 14 and 15, 16, respectively. From the diode bridges the direct voltages u are then obtained, which, in the manner described above, control the component to conducting state.
Figure 5b shows an alternative embodiment of the device according to Figure Sa. The integra-ted circuit A comprises, in addition to the two field effect transistors, two sets of rectifier bridges, namely lla, llb and 12a, 12b, respectively, and two sets of inverters, namely Ila, Ilb, Ilc and I2a, I2b, I2c, respectively. The bridges lla, 12a are supplied with a constant alternating voltage P via the connections 17a, 17b and the capacitors 13a, 13b, 15a, 15b, for example o~ such an amplitude that the bridges deliver direct voltages of the order of magnitude 5 V. These direct voltages are supplied to the inverters as supply voltages.
When the component is to be conducting, a control signal in the form of an alternating voltage S is supplied to the control connections 18a, 18b. This causes a control direct voltage to be generated across the resistors 61a, 62a, which makes the output signals of the inverters Ila and I2a "low"
and of the inverters Ilb and I2b "high", i.e. the control voltages "u" become positive and the component becomes conducting and is maintained conducting for as long as the control signal S is supplied. When the control signal S is removed, the output voltage from the bridges llb, 12b becomes zero, the output signals from the inverters Ila and I2a become "high" and from the inverters Ilb and I2b "low", - , .
', : ~':. , : , : ~ , ~i :
. , and the control voltages "u" become negative. The component becomes non-conducting and the negative control voltage "u"
suppresses injection and thus increases the maximum permissible voltage of the component.
In the embodiments of the invention described above, both the field effect transistors are produced in thin semiconductor layers of which -the lower is arranged on an electrically insulating layer located on a substrate.
Figure 6 shows an alternative embodiment oE the invention, in which the lower transistor is produced directly in the substrate, which consists of a monocrystalline silicon body 1. At the lower transistor this body has a P-doped zone 32a, which constitutes the channel region of the transistor.
In this zone N-conducting regions 31a, 33a are produced, which constitute the source and drain regions of the transistor. Otherwise, the component is formed in the manner previously described.
A component accord.ing to the invention may be manufactured in a plurality of different ways. A preferred method of manufacture will be described in the following with reference to Figure 7. In a monocrystalline silicon wafer X
there are generated, by ion implantation of oxyqen and nitrogen, respectively, through the upper surface of the wafer in the figure, a silicon dioxide layer 101 and a silicon nitrode layer 102 (SiXNy). Those parts, 104, 105, 106, of the silicon body which are positioned outside the two layers just mentioned are not influenced by this treatment. Fiqure 7a shows the silicon body after the ion implantation. Thereafter there is generated, by some known method (e.g. thermal oxidation and/or deposition), a silicon dioxide layer 103 on the surface of the body, which is shown in Figure 7b. Figure 7c shows the silicon body X turned upside down. A second body Y of monocrystalline silicon has been provided, in a similar known manner, wi-th a silicon dioxide layer 201 on its surface. The two bodies are brought toqether in the manner indicated by the arrow in ': ,'', ~ :
-: .:
~' ~ ~ ,,;; ' :
Figure 7c. Even at room temperature a bonding then takes place between the plates. The bonding may be reinforced by a heat treatment in the temperature range ~00-1000C. By a subsequent treatment by etching, part 106 of the silicon body X is etched away, the nitride layer 102 then serving as stop layer during the etching. Then the nitride layer 102 is etched away. The body thus manufactured is shown in Figure 7d. The silicon body Y constitutes a substrate; the silicon dioxide layers 201 and 103 form an electrically insulating layer between the substrate and the semiconductor component according to the invention; in the monocrystalline thin silicon layer 109 the lower transistor of the component is produced; the silicon dioxide layer 101 serves as electrical insulation between the two transistors of the component; and in the upper monocrystalline silicon layer 105 the upper transistors of the component are produced.
The desired doping of the different regions of the transistors may, for example, be made with the aid of ion implantation, either after the manufacturing steps described above, or earlier during the manufacturing process.
The component according to the invention has been described above as a semiconductor switch for use as switching member.
The component may have other fields of use as well, for example as a controllable element in integrated digital circuits. Besides as switching member, the component may also be used for stepless control in analog circuits.
In Figure 2, the output circuit of the component consists of a voltage source and a load object. However, the output circuit may be of an arbitrary kind, for example a digital or analog circuit element or circuit.
.
:, . ~, : ~ . .:
: : .,,, ~ ' '
Claims
121. A semiconductor device comprising a first field effect transistor of a first conductivity type (N), which transistor is arranged in a semiconductor body (3) and has a source region (31) provided with a source connection (311), a drain region (33) provided with a drain connection (331), a channel region (32) arranged between the source and drain regions, and members (5, 71, 72) for producing a conducting channel in the channel region between the source and drain regions, characterized in that it comprises an insulating layer (4) provided on the semiconductor body and a first layer (5), arranged on the insulating layer, of semiconducting material in which a second field effect transistor is produced, the conductivity type (P) of which is opposite to the conductivity type of said first field effect transistor and which has a source region (51), a drain region (53) and a channel region (52), the channel region (52) of the second transistor is adapted so as to at least overlap the channel region (32) of the first transistor, the voltage-absorbing directions of the two transistors at least substantially coincide, the source region (51) of the second transistor is provided with a connection (511) for connection of a control voltage (u) between the source regions (31, 51) of the first transistor and the second transistor, the drain region (53) of the second transistor is provided with a connection (531) for connection of a control voltage (u) between the drain regions (33, 53) of the first transistor and the second transistor, and that the source and drain regions (31, 33) of one of the two transistors are provided with connection members (311, 312, 331, 332) for connection of an output circuit (9, 10).
2. A semiconductor device according to claim 1, characterized in that the doping concentrations and the thicknesses of the channel regions (32, 52) of the two transistors are selected such that charge balance prevails between the two channel regions.
3. A semiconductor device according to any of the preceding claims, characterized in that the two transistors are of enhancement type.
4. A semiconductor device according to any of the preceding claims, characterized in that a stop zone (34, 35) of the same conductivity type (P) as the channel region (32) of a transistor, but with a higher degree of doping than the channel region, is provided between the channel region (32) and at least one of the source and drain regions (31, 33) of the transistor.
5. A semiconductor device according to claim 4, characterized in that a first stop zone (39) is provided between the channel region (32) of the transistor and its source region (31) and a second stop zone (35) is provided between the channel region of the transistor and its drain region (33).
6. A semiconductor device according to claim 4, characterized in that stop zones are provided in both the transistors.
7. A semiconductor device according to claim 6, characterized in that one transistor has a stop zone (54) between its channel region (52) and its source region (51) and that the other transistor has a stop zone (35) between its channel region (32) and its drain region (33).
8. A semiconductor device according to any of the preceding claims, characterized in that said semiconductor body (3) consists of a second layer of semiconducting material provided on an insulating base (2).
9. A semiconductor device according to any of the preceding claims, characterized in that it comprises control voltage-generating members (11, 12) adapted, in dependence on a received control signal (s), to supply said control voltages (u) to the source and drain connections of the transistors for control of the transistors between conducting and non-conducting states.
10. A semiconductor device according to claim 9, characterized in that the control voltage-generating members are adapted to supply to the source and drain connections of the transistors, for control of the component to conducting state, control voltages of a first polarity and for control of the component to non-conducting state, control voltages of the opposite polarity.
11. A semiconductor device according to claim 9 or 10, characterized in that said control voltage-generating members are so designed that said control voltages are mutually equally great.
12. A semiconductor device according to any of the preceding claims, characterized in that it is provided with potential-controlling members (61, 62) adapted, in the non-conducting state of the transistors, to maintain the source regions (31, 51) of the two transistors at a first potential and the drain regions (33, 53) of the two transistors at a second potential.
13. A semiconductor device according to claim 12, characterized in that the potential-controlling members consist of a first resistance element (61) connected between the source regions of the transistors and a second resistance element (62) connected between the drain regions of the transistors.
19. A semiconductor device according to any of the preceding claims, characterized in that the doping profiles of the channel regions (32, 52) are so chosen that, in the non-conducting state of the transistors, the potential at each point of the channel region of one of the transistors is as equal as possible to the potential in that part of the channel region of the other transistor which is located opposite to said point.
2. A semiconductor device according to claim 1, characterized in that the doping concentrations and the thicknesses of the channel regions (32, 52) of the two transistors are selected such that charge balance prevails between the two channel regions.
3. A semiconductor device according to any of the preceding claims, characterized in that the two transistors are of enhancement type.
4. A semiconductor device according to any of the preceding claims, characterized in that a stop zone (34, 35) of the same conductivity type (P) as the channel region (32) of a transistor, but with a higher degree of doping than the channel region, is provided between the channel region (32) and at least one of the source and drain regions (31, 33) of the transistor.
5. A semiconductor device according to claim 4, characterized in that a first stop zone (39) is provided between the channel region (32) of the transistor and its source region (31) and a second stop zone (35) is provided between the channel region of the transistor and its drain region (33).
6. A semiconductor device according to claim 4, characterized in that stop zones are provided in both the transistors.
7. A semiconductor device according to claim 6, characterized in that one transistor has a stop zone (54) between its channel region (52) and its source region (51) and that the other transistor has a stop zone (35) between its channel region (32) and its drain region (33).
8. A semiconductor device according to any of the preceding claims, characterized in that said semiconductor body (3) consists of a second layer of semiconducting material provided on an insulating base (2).
9. A semiconductor device according to any of the preceding claims, characterized in that it comprises control voltage-generating members (11, 12) adapted, in dependence on a received control signal (s), to supply said control voltages (u) to the source and drain connections of the transistors for control of the transistors between conducting and non-conducting states.
10. A semiconductor device according to claim 9, characterized in that the control voltage-generating members are adapted to supply to the source and drain connections of the transistors, for control of the component to conducting state, control voltages of a first polarity and for control of the component to non-conducting state, control voltages of the opposite polarity.
11. A semiconductor device according to claim 9 or 10, characterized in that said control voltage-generating members are so designed that said control voltages are mutually equally great.
12. A semiconductor device according to any of the preceding claims, characterized in that it is provided with potential-controlling members (61, 62) adapted, in the non-conducting state of the transistors, to maintain the source regions (31, 51) of the two transistors at a first potential and the drain regions (33, 53) of the two transistors at a second potential.
13. A semiconductor device according to claim 12, characterized in that the potential-controlling members consist of a first resistance element (61) connected between the source regions of the transistors and a second resistance element (62) connected between the drain regions of the transistors.
19. A semiconductor device according to any of the preceding claims, characterized in that the doping profiles of the channel regions (32, 52) are so chosen that, in the non-conducting state of the transistors, the potential at each point of the channel region of one of the transistors is as equal as possible to the potential in that part of the channel region of the other transistor which is located opposite to said point.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE8903761-8 | 1989-11-09 | ||
| SE8903761A SE464949B (en) | 1989-11-09 | 1989-11-09 | SEMICONDUCTOR SWITCH |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2069911A1 true CA2069911A1 (en) | 1991-05-10 |
Family
ID=20377432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2069911 Abandoned CA2069911A1 (en) | 1989-11-09 | 1990-10-19 | Semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0540516A1 (en) |
| JP (1) | JPH05501479A (en) |
| CA (1) | CA2069911A1 (en) |
| SE (1) | SE464949B (en) |
| WO (1) | WO1991007780A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5684320A (en) * | 1991-01-09 | 1997-11-04 | Fujitsu Limited | Semiconductor device having transistor pair |
| JP3135939B2 (en) * | 1991-06-20 | 2001-02-19 | 富士通株式会社 | HEMT type semiconductor device |
| SE513283C2 (en) * | 1996-07-26 | 2000-08-14 | Ericsson Telefon Ab L M | MOS transistor structure with extended operating region |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS577161A (en) * | 1980-06-16 | 1982-01-14 | Toshiba Corp | Mos semiconductor device |
| US4593300A (en) * | 1984-10-31 | 1986-06-03 | The Regents Of The University Of Minnesota | Folded logic gate |
| SE460448B (en) * | 1988-02-29 | 1989-10-09 | Asea Brown Boveri | DOUBLE DIRECT MOS SWITCH |
-
1989
- 1989-11-09 SE SE8903761A patent/SE464949B/en not_active IP Right Cessation
-
1990
- 1990-10-19 JP JP51546390A patent/JPH05501479A/en active Pending
- 1990-10-19 WO PCT/SE1990/000678 patent/WO1991007780A1/en not_active Application Discontinuation
- 1990-10-19 EP EP19900916841 patent/EP0540516A1/en not_active Withdrawn
- 1990-10-19 CA CA 2069911 patent/CA2069911A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| SE8903761D0 (en) | 1989-11-09 |
| JPH05501479A (en) | 1993-03-18 |
| WO1991007780A1 (en) | 1991-05-30 |
| SE8903761L (en) | 1991-05-10 |
| EP0540516A1 (en) | 1993-05-12 |
| SE464949B (en) | 1991-07-01 |
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