CA2066282A1 - Circuit arrangement for amplifying an electrical signal - Google Patents
Circuit arrangement for amplifying an electrical signalInfo
- Publication number
- CA2066282A1 CA2066282A1 CA 2066282 CA2066282A CA2066282A1 CA 2066282 A1 CA2066282 A1 CA 2066282A1 CA 2066282 CA2066282 CA 2066282 CA 2066282 A CA2066282 A CA 2066282A CA 2066282 A1 CA2066282 A1 CA 2066282A1
- Authority
- CA
- Canada
- Prior art keywords
- circuit arrangement
- resistor
- voltage divider
- transistor
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
- H03F1/48—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers
- H03F1/483—Modifications of amplifiers to extend the bandwidth of aperiodic amplifiers with field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
- H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
- H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Abstract Circuit Arrangement for Amplifying an Electrical Signal The invention relates to a circuit arrangement for amplifying a signal used in optical data transmissions. To improve the transmission behavior of the amplifier for the output signal of a photodiode, particularly a PIN diode, a transistor amplifier configured as current amplifier is provided with a current shunt feedback connection by way of a negative feedback network including capacitive voltage dividers. By suitably dimensioning the capacitive voltage divider formed of a transmission voltage divider (C1, R1, C2, R2) and a loop voltage divider (C, C1, R1), sufficient gain with an adequate signal to noise ratio is ensured also for high frequencies.
(Figure 2)
(Figure 2)
Description
Translation CIRCUIT ARRANGEMENT ~OR ANPLIFYING AN ELECTRICAL SIGNAL
The invention relates to a circuit arrangement for amplifying an electrical signal, particularly the photocur-rent of a photodiode, which is generated as a function of the intensity of the light incident on the photodiode.
In a known circuit arrangement of this type (D. Lutzke, "Lichtwellenleitertechnik" [Light Waveguide Technology], published by R. Pflaum Verlag, Munich, 1986, pages 282-285), a transimpedance amplifier is provided which includes a feedback resistor as its negative feedback network. With this circuit arrangement, it is possible to realize a transmission behavior with which a low impedance voltage source for the further amplification is formed from the high impedance current source (photodiode). However, the band-width of this circuit is limited by the influence of the feedback resistor.
In a further circuit arrangement (H.-D. Kirschbaum, "Transistorverst~rker Z, Teil 1" tTransistor Amplifier 2, Part 1], Teubner Studienskripten [Teubner Study Scripts], Stuttgart, 1985, pages 199-202) a transistor amplifier connected as current amplifier is provided with a current 2o6g~2 shunt feedback composed of a resistance network. The circuit described here includes two transistor stages and a divided emitter resistor at the second transistor as well as a negative feedback resistor that is coupled back from the center tap of this emitter resistor to the input, more precisely to the base, of the first transistor. This prior art circuit is suitable for the amplification of particularly small input currents as they are generated, for example, by photodiodes upon the detection of light signals. In this connection, it is of particular significance to ensure a sufficient signal to noise ratio for the further evaluation of the current of the photodiode also after the necessary amplification of the current so that the error rate in the subsequent information processing can be kept as low as possible. The relationships between the error rate and the signal to noise ratio are described, for example, in the book by G. Grau, entitled "Optische Nachrichtentechnik" rOptical Data Communications], published by Springer Verlag Berlin, Heidelberg, New York, at page 264. Additionally, it must be considered that the gain should also be sufficient at high frequencies since in optical data communications the band-width to be transmitted is very wide.
~ his prior art circuit arrangement also has the drawback that if the photocurrent of a photodiode, particularly a PIN
The invention relates to a circuit arrangement for amplifying an electrical signal, particularly the photocur-rent of a photodiode, which is generated as a function of the intensity of the light incident on the photodiode.
In a known circuit arrangement of this type (D. Lutzke, "Lichtwellenleitertechnik" [Light Waveguide Technology], published by R. Pflaum Verlag, Munich, 1986, pages 282-285), a transimpedance amplifier is provided which includes a feedback resistor as its negative feedback network. With this circuit arrangement, it is possible to realize a transmission behavior with which a low impedance voltage source for the further amplification is formed from the high impedance current source (photodiode). However, the band-width of this circuit is limited by the influence of the feedback resistor.
In a further circuit arrangement (H.-D. Kirschbaum, "Transistorverst~rker Z, Teil 1" tTransistor Amplifier 2, Part 1], Teubner Studienskripten [Teubner Study Scripts], Stuttgart, 1985, pages 199-202) a transistor amplifier connected as current amplifier is provided with a current 2o6g~2 shunt feedback composed of a resistance network. The circuit described here includes two transistor stages and a divided emitter resistor at the second transistor as well as a negative feedback resistor that is coupled back from the center tap of this emitter resistor to the input, more precisely to the base, of the first transistor. This prior art circuit is suitable for the amplification of particularly small input currents as they are generated, for example, by photodiodes upon the detection of light signals. In this connection, it is of particular significance to ensure a sufficient signal to noise ratio for the further evaluation of the current of the photodiode also after the necessary amplification of the current so that the error rate in the subsequent information processing can be kept as low as possible. The relationships between the error rate and the signal to noise ratio are described, for example, in the book by G. Grau, entitled "Optische Nachrichtentechnik" rOptical Data Communications], published by Springer Verlag Berlin, Heidelberg, New York, at page 264. Additionally, it must be considered that the gain should also be sufficient at high frequencies since in optical data communications the band-width to be transmitted is very wide.
~ his prior art circuit arrangement also has the drawback that if the photocurrent of a photodiode, particularly a PIN
2~fi~82 diode, is amplified, the transmission behavior at high frequencies is not the best.
It is an object of the invention to provide a circuit arrangement having the features defined in the preamble of the main ~laim for amplifying an electrical signal in which the transmiesion behavior during the amplification of the photocurrent of a photodiode is improved.
This is accomplished according to the invention by the characterizing features of the main claim.
The circuit arrangement according to the invention is of advantage primarily because of the use of a negative feedback network composed of two capacitive voltage dividers, which is very easy to realize from a circuit engineering point of view and which does not adversely affect the other characteristics of the current amplifier principle but nevertheless ensures a considerable improvement of the transmission characteristics of the circuit arrangement at high frequencies with a sufficient signal to noise ratio in the signal to be process-ed.
one embodiment of the circuit arrangement according to the invention, incorporating the features of claim 2, permits in an advantageous manner an optimum loop gain by way of suitable dimensioning of the resistors and capacitors of the capacitive voltage dividers, with particularly the low 2~66~82 impedance circuit point at the source terminal of the second transistor stage being utilized. This makes it possible to select the resistor disposed in the negative feedback path of the voltage divider to be highly resistant and to obtain a favorable signal to noise ratio. This high resistance value is possible since the relatively low impedance circuit point at the center tap of the capacitive voltage divider allows the latter to be capacitively loaded, thus permitting the use of a relatively small capacitor in the negative feedback path. However, it can always be ensured that the time constants of the two components of the capacitive voltage divider are identical and a dividing ratio of, for example, 1:10 can be realized. With this embodiment, an excellent transmission behavior is thus also ensured for high frequencies.
In the embodiment of the circuit arrangement according to claim 3 of the invention which includes two field effect transistors, the advantages resulting from a combination of a PIN diode with a current amplifier circuit become particular-ly evident. The use of a PIN diode is advantageous particu-larly compared to the usually employed avalanche photo-diodes, since the latter, although they have a very high sensitivity, are very expensive and a high voltage is required to supply such a photodiode with voltage. Thus the 2~66282 circuit arrangement is significantly simplified and made less expensive.
Other advantageous features of the invention are disclosed in the remaining dependent claims.
One embodiment of the invention will now be described and explained with reference to Figures 1 to 4. It is shown in:
Figure 1, a block circuit diagram for a current ampli-fier with current-current feedback;
Figure 2, a basic circuit arrangement for a current amplifier including a PIN photodiode at its input;
Figure 3, a basic circuit diagram for a loop voltage divider;
Figure 4, a basic circuit diagram for a transmission voltage divider;
Figure 5, an example of an output circuit for the current amplifier of Figure 2 including a connected gate drain stage;
Figure 6, a further example of an output circuit for the current amplifier including a transimpedance amplifier.
Figure 1 shows a block circuit diagram including two series connected amplifier stages Tl and T2 which are 2;~66282 constructed as current amplifier including a current shunt negative feedback by way of a voltage divider composed of resistors R1 and R~. Resistor R1 is here fed back from the second stage T2 to the input of the first stage Tl. A
current source Q is disposed at the input of the first amplifier stage T1 and furnishes a current Io as the signal to be amplified. An output resistor R at which the output voltage U can be pi~ked up is disposed at the output of the second amplifier stage T2. A current Io here flows through resistor R1, a current Io' = Io R1/R2 flows through resistor R2 and a current Io'' according to the equation Io'' = Io (1 + R1/R2) flows at the output of the second stage, with the resulting transmission constant of the current amplifier being Io''tIo.
Figure 2 shows a basic embodiment of the circuit arrangement according to the invention in which the current source is a PIN diode which is connected as photodiode P
between the gate G1 of a first amplifier stage formed of a field effect transistor FET1 and the positive pole of the operating voltage UB. This photodiode P furnishes a current Io as the input signal for the current amplifier. Between gate G1 of field effect transistor FETl and the zero 2~6282 potential of operating voltage UB, there is disposed a capacitance C which is essentially composed of the switching capacitances of the input region of the circuit arrangement including the inherent capacitances of photodiode P and of field effect transistor FETl. Connected thereto is a capacitive transmission voltaqe divider composed of a first parallel connection of a resistor R1 and a capacitor Cl and a ~econd parallel connection of a resistor R2 and a capacitor C2. The transmission voltage divider is shown individually in Figure 4, with the transmission constant being derivable from the relationship Uo/U. Figure 3 is a schematic repre-sentation of a loop voltage divider formed of a capacitance C
and the parallel connection of R1 and C1 which is determina-tive for the calculation of the loop gain and can be repre-sented by a calculated separation of the negative feedback path.
The source terminal SO1 of the first field effect transistor FETl (Figure 2) is connected directly to the zero potential of operating voltage UB and the drain terminal Dl is connected, on the one hand, by way of a resistor X1 to the positive pole of operating voltage UB and, on the other hand, directly to the gate G2 of a second field effect transistor FET2.
20~82 The source terminal S2 of the second field effect transistor FET2 is brought to a center tap M of the capaci-tive voltage divider and the drain terminal D2 of the second field effect transistor FET2 lies, by way of a r sistor X2, at the positive pole of operating voltage UB and, by way of a capacitor C3, at an output resistor R; the resistance value of drain resistor X2 must here be greater than the value of output resistance R.
In order to obtain the optimum transmission behavior of the circuit arrangement according to the invention, the capacitive voltage divider must be dimensioned in such a way that the time constants of both components of the capacitive voltage divider are the same, that is, the following condi-tion must be met:
R1 Cl = R2 C2.
The complex resistances of the two components of the capacitive voltage divider Rl and R2 result as follows:
R1 = 1 + j~ R1 C1 R2 = 1 + j~ R2 C2 The current gain of the circuit arrangement thus results as follows:
Vi = 1 + Rl . 1 + j~ R2 C2 R2 1 + j~ R1 C1 and, under the condition that R1 C1 = R2 C2, it is the following:
Vi = 1 + C2/C1 = 1 + R1/R2.
Under consideration of the negative feedback by way of the capacitive voltage divider the loop gain Vs of the circuit arrangement is calculated according to the following formula:
S1 ~ X1 Vs = 1 + 1 + j~ Rl Cl For low frequencies, the following applies:
Vst = Sl Xl and the following for high frequencies:
Vsh = S1 X1 1 +
Under the assumption that the steepness S1 of field effect transistor FETl is 50ms and, for example, the follow-ing dimensions exist:
X1 = ~oo Ohm C = 1 pF, Cl = 0.25 pF, 2~66282 a gain of 20 dB results for low frequencies and a gain of 6 dB for high frequencies.
From these derivations it can be seen that the ratio of C/Cl determines the loop gain at high frequencies. Thus the optimum selection of capacitor C1 ensures a sufficient amplification factor for the circuit arrangement according to the invention even at high frequencies.
In the embodiment according to Figure 2, for example, a resistance value of 50 Ohm can be selected as output resis-tance R. As an alternative, however, a further transistor stage in the form of a cascode circuit may b~ added as shown in Figure 5. Instead of the load resistor X~, Figure 5 includes a gate stage and a cascode circuit including a source follower, respectively. For this purpose, a field effect transistor FET3 including a load resistor R3 is provided. The output of this field effect transistor FET3 is connectad to the gate terminal of an output field effect transistor FET4 at whose source resistor R4 the output signal is availa~le.
Another embodiment of an output configuration of the circuit arrangement according to the invention is shown in Figure 6. Here a transimpedance amplifier TV constructed in a known manner is connected to the output of a current ampli-fier SV, here shown as a block according to Figure 2, with 2~66282 the transfer function of transimpedance amplifier TV being essentially dependent upon a negative feedback resistor RT.
It is an object of the invention to provide a circuit arrangement having the features defined in the preamble of the main ~laim for amplifying an electrical signal in which the transmiesion behavior during the amplification of the photocurrent of a photodiode is improved.
This is accomplished according to the invention by the characterizing features of the main claim.
The circuit arrangement according to the invention is of advantage primarily because of the use of a negative feedback network composed of two capacitive voltage dividers, which is very easy to realize from a circuit engineering point of view and which does not adversely affect the other characteristics of the current amplifier principle but nevertheless ensures a considerable improvement of the transmission characteristics of the circuit arrangement at high frequencies with a sufficient signal to noise ratio in the signal to be process-ed.
one embodiment of the circuit arrangement according to the invention, incorporating the features of claim 2, permits in an advantageous manner an optimum loop gain by way of suitable dimensioning of the resistors and capacitors of the capacitive voltage dividers, with particularly the low 2~66~82 impedance circuit point at the source terminal of the second transistor stage being utilized. This makes it possible to select the resistor disposed in the negative feedback path of the voltage divider to be highly resistant and to obtain a favorable signal to noise ratio. This high resistance value is possible since the relatively low impedance circuit point at the center tap of the capacitive voltage divider allows the latter to be capacitively loaded, thus permitting the use of a relatively small capacitor in the negative feedback path. However, it can always be ensured that the time constants of the two components of the capacitive voltage divider are identical and a dividing ratio of, for example, 1:10 can be realized. With this embodiment, an excellent transmission behavior is thus also ensured for high frequencies.
In the embodiment of the circuit arrangement according to claim 3 of the invention which includes two field effect transistors, the advantages resulting from a combination of a PIN diode with a current amplifier circuit become particular-ly evident. The use of a PIN diode is advantageous particu-larly compared to the usually employed avalanche photo-diodes, since the latter, although they have a very high sensitivity, are very expensive and a high voltage is required to supply such a photodiode with voltage. Thus the 2~66282 circuit arrangement is significantly simplified and made less expensive.
Other advantageous features of the invention are disclosed in the remaining dependent claims.
One embodiment of the invention will now be described and explained with reference to Figures 1 to 4. It is shown in:
Figure 1, a block circuit diagram for a current ampli-fier with current-current feedback;
Figure 2, a basic circuit arrangement for a current amplifier including a PIN photodiode at its input;
Figure 3, a basic circuit diagram for a loop voltage divider;
Figure 4, a basic circuit diagram for a transmission voltage divider;
Figure 5, an example of an output circuit for the current amplifier of Figure 2 including a connected gate drain stage;
Figure 6, a further example of an output circuit for the current amplifier including a transimpedance amplifier.
Figure 1 shows a block circuit diagram including two series connected amplifier stages Tl and T2 which are 2;~66282 constructed as current amplifier including a current shunt negative feedback by way of a voltage divider composed of resistors R1 and R~. Resistor R1 is here fed back from the second stage T2 to the input of the first stage Tl. A
current source Q is disposed at the input of the first amplifier stage T1 and furnishes a current Io as the signal to be amplified. An output resistor R at which the output voltage U can be pi~ked up is disposed at the output of the second amplifier stage T2. A current Io here flows through resistor R1, a current Io' = Io R1/R2 flows through resistor R2 and a current Io'' according to the equation Io'' = Io (1 + R1/R2) flows at the output of the second stage, with the resulting transmission constant of the current amplifier being Io''tIo.
Figure 2 shows a basic embodiment of the circuit arrangement according to the invention in which the current source is a PIN diode which is connected as photodiode P
between the gate G1 of a first amplifier stage formed of a field effect transistor FET1 and the positive pole of the operating voltage UB. This photodiode P furnishes a current Io as the input signal for the current amplifier. Between gate G1 of field effect transistor FETl and the zero 2~6282 potential of operating voltage UB, there is disposed a capacitance C which is essentially composed of the switching capacitances of the input region of the circuit arrangement including the inherent capacitances of photodiode P and of field effect transistor FETl. Connected thereto is a capacitive transmission voltaqe divider composed of a first parallel connection of a resistor R1 and a capacitor Cl and a ~econd parallel connection of a resistor R2 and a capacitor C2. The transmission voltage divider is shown individually in Figure 4, with the transmission constant being derivable from the relationship Uo/U. Figure 3 is a schematic repre-sentation of a loop voltage divider formed of a capacitance C
and the parallel connection of R1 and C1 which is determina-tive for the calculation of the loop gain and can be repre-sented by a calculated separation of the negative feedback path.
The source terminal SO1 of the first field effect transistor FETl (Figure 2) is connected directly to the zero potential of operating voltage UB and the drain terminal Dl is connected, on the one hand, by way of a resistor X1 to the positive pole of operating voltage UB and, on the other hand, directly to the gate G2 of a second field effect transistor FET2.
20~82 The source terminal S2 of the second field effect transistor FET2 is brought to a center tap M of the capaci-tive voltage divider and the drain terminal D2 of the second field effect transistor FET2 lies, by way of a r sistor X2, at the positive pole of operating voltage UB and, by way of a capacitor C3, at an output resistor R; the resistance value of drain resistor X2 must here be greater than the value of output resistance R.
In order to obtain the optimum transmission behavior of the circuit arrangement according to the invention, the capacitive voltage divider must be dimensioned in such a way that the time constants of both components of the capacitive voltage divider are the same, that is, the following condi-tion must be met:
R1 Cl = R2 C2.
The complex resistances of the two components of the capacitive voltage divider Rl and R2 result as follows:
R1 = 1 + j~ R1 C1 R2 = 1 + j~ R2 C2 The current gain of the circuit arrangement thus results as follows:
Vi = 1 + Rl . 1 + j~ R2 C2 R2 1 + j~ R1 C1 and, under the condition that R1 C1 = R2 C2, it is the following:
Vi = 1 + C2/C1 = 1 + R1/R2.
Under consideration of the negative feedback by way of the capacitive voltage divider the loop gain Vs of the circuit arrangement is calculated according to the following formula:
S1 ~ X1 Vs = 1 + 1 + j~ Rl Cl For low frequencies, the following applies:
Vst = Sl Xl and the following for high frequencies:
Vsh = S1 X1 1 +
Under the assumption that the steepness S1 of field effect transistor FETl is 50ms and, for example, the follow-ing dimensions exist:
X1 = ~oo Ohm C = 1 pF, Cl = 0.25 pF, 2~66282 a gain of 20 dB results for low frequencies and a gain of 6 dB for high frequencies.
From these derivations it can be seen that the ratio of C/Cl determines the loop gain at high frequencies. Thus the optimum selection of capacitor C1 ensures a sufficient amplification factor for the circuit arrangement according to the invention even at high frequencies.
In the embodiment according to Figure 2, for example, a resistance value of 50 Ohm can be selected as output resis-tance R. As an alternative, however, a further transistor stage in the form of a cascode circuit may b~ added as shown in Figure 5. Instead of the load resistor X~, Figure 5 includes a gate stage and a cascode circuit including a source follower, respectively. For this purpose, a field effect transistor FET3 including a load resistor R3 is provided. The output of this field effect transistor FET3 is connectad to the gate terminal of an output field effect transistor FET4 at whose source resistor R4 the output signal is availa~le.
Another embodiment of an output configuration of the circuit arrangement according to the invention is shown in Figure 6. Here a transimpedance amplifier TV constructed in a known manner is connected to the output of a current ampli-fier SV, here shown as a block according to Figure 2, with 2~66282 the transfer function of transimpedance amplifier TV being essentially dependent upon a negative feedback resistor RT.
Claims (6)
1. A circuit arrangement for amplifying an electrical signal generated by a photodiode as a function of the intensity of the light incident on the photodiode, the arrangement including a negative feedback network equipped with a feedback resistor, characterized in that the circuit arrangement is configured as a current amplifier including a current shunt feedback; the frequency response of the circuit arrangement, which is influenced by the feedback resistor (R1) and by a capacitor (C1) of the negative feedback network (C, C1, R1, C2, R2), is compensated in that the negative feedback network (C, C1, R1, C2, R2) is formed of two capacitive voltage dividers, with a transmission voltage divider C1, R1, C2, R2) being provided in the negative feedback path of the current amplifier and a loop voltage divider (C, C1, R1) at the input of the current amplifier;
and the value of the capacitor (C1) of the transmission voltage divider is selected in such a way that an optimum loop gain is ensured even at the highest required cutoff frequency of the circuit arrangement.
and the value of the capacitor (C1) of the transmission voltage divider is selected in such a way that an optimum loop gain is ensured even at the highest required cutoff frequency of the circuit arrangement.
2. A circuit arrangement according to claim 1, charac-terized in that the circuit arrangement is a two-stage transistor amplifier composed of an emitter (source) and collector (drain) stage, and the emitter-source terminal (SO2) of the second transistor (FET2) is connected as a low impedance switching point to the center tap (M) of the capacitive voltage divider (C, C1, R1, C2, R2), with the time constants of the two components (R1, C1 / R2, C2) of the capacitive voltage divider being dimensioned to be ap-proximately equal.
3. A circuit arrangement according to claim 2, charac-terized in that the transistor amplifier is composed of two field effect transistors (FET1, FET2) and is configured as follows:
- a PIN diode is employed as the photodiode (P) and is disposed between the gate (G1) of the first transistor (FET1) and the positive pole of the operating voltage (UB);
- the drain terminal (D1) of the first transistor (FET1) is connected via a resistor (X1) to the positive pole of the operating voltage (UB) and the source terminal (SO1) is connected directly to the zero potential of the operating voltage (UB);
- between the gate (G1) of the first transistor (FET1) and the zero potential of the operating voltage (UB) lies a capacitance (C), whose effective magnitude is in-fluenced by the switching capacitances of the input region of the circuit arrangement, as well as the transmission voltage divider (R1, C1, R2, C2);
- the gate terminal (G2) of the second transistor (FET2) is connected with the drain terminal (D1) of the first transistor (FETl);
- the source terminal (SO2) of the second transis-tor (FET2) lies at the center tap of the capacitive voltage divider (R1, C1, R2, C2) and the drain terminal (D2) is connected by way of a resistor (X2) to the positive pole of the operating voltage (UB) and by way of a capacitor (C3) to a resistor (R) at which the output signal is available.
- a PIN diode is employed as the photodiode (P) and is disposed between the gate (G1) of the first transistor (FET1) and the positive pole of the operating voltage (UB);
- the drain terminal (D1) of the first transistor (FET1) is connected via a resistor (X1) to the positive pole of the operating voltage (UB) and the source terminal (SO1) is connected directly to the zero potential of the operating voltage (UB);
- between the gate (G1) of the first transistor (FET1) and the zero potential of the operating voltage (UB) lies a capacitance (C), whose effective magnitude is in-fluenced by the switching capacitances of the input region of the circuit arrangement, as well as the transmission voltage divider (R1, C1, R2, C2);
- the gate terminal (G2) of the second transistor (FET2) is connected with the drain terminal (D1) of the first transistor (FETl);
- the source terminal (SO2) of the second transis-tor (FET2) lies at the center tap of the capacitive voltage divider (R1, C1, R2, C2) and the drain terminal (D2) is connected by way of a resistor (X2) to the positive pole of the operating voltage (UB) and by way of a capacitor (C3) to a resistor (R) at which the output signal is available.
4. A circuit arrangement according to claim 3, charac-terized in that the resistor (R) at the output of the circuit arrangement has the value of 50 Ohm.
5. A circuit arrangement according to claim 3, charac-terized in that the resistor (R) at the output of the circuit arrangement is a gate drain stage composed of further field effect transistors (FET3, FET4).
6. A circuit arrangement according to claim 3, charac-terized in that the resistor (R) at the output of the circuit arrangement is a transimpedance amplifier circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP4112557.6 | 1991-04-17 | ||
| DE19914112557 DE4112557A1 (en) | 1991-04-17 | 1991-04-17 | CIRCUIT ARRANGEMENT FOR THE AMPLIFICATION OF AN ELECTRICAL SIGNAL |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2066282A1 true CA2066282A1 (en) | 1992-10-18 |
Family
ID=6429804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2066282 Abandoned CA2066282A1 (en) | 1991-04-17 | 1992-04-16 | Circuit arrangement for amplifying an electrical signal |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0509272A1 (en) |
| JP (1) | JPH05121964A (en) |
| AU (1) | AU1494192A (en) |
| CA (1) | CA2066282A1 (en) |
| DE (1) | DE4112557A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10058952B4 (en) * | 2000-11-28 | 2007-02-01 | Infineon Technologies Ag | Circuit arrangement for converting an analog input signal |
| LU92272B1 (en) * | 2013-08-28 | 2015-03-02 | Iee Sarl | Inductive respiration sensor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4075576A (en) * | 1977-02-25 | 1978-02-21 | Rockwell International Corporation | Sensitive high speed solid state preamp |
| JPS6143004A (en) * | 1984-08-03 | 1986-03-01 | Fujitsu Ltd | Optical reception circuit |
| FR2630598B1 (en) * | 1988-04-22 | 1994-04-15 | Thomson Csf | VERY BROADBAND AND LOW NOISE AMPLIFIER |
-
1991
- 1991-04-17 DE DE19914112557 patent/DE4112557A1/en not_active Withdrawn
-
1992
- 1992-03-24 EP EP19920105024 patent/EP0509272A1/en not_active Withdrawn
- 1992-04-10 AU AU14941/92A patent/AU1494192A/en not_active Withdrawn
- 1992-04-16 CA CA 2066282 patent/CA2066282A1/en not_active Abandoned
- 1992-04-16 JP JP4096698A patent/JPH05121964A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| AU1494192A (en) | 1992-10-22 |
| DE4112557A1 (en) | 1992-10-22 |
| EP0509272A1 (en) | 1992-10-21 |
| JPH05121964A (en) | 1993-05-18 |
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