CA2055546C - Self-routing network using optical gate array driven by control voltages coincidental with packet header pulses - Google Patents
Self-routing network using optical gate array driven by control voltages coincidental with packet header pulsesInfo
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- CA2055546C CA2055546C CA002055546A CA2055546A CA2055546C CA 2055546 C CA2055546 C CA 2055546C CA 002055546 A CA002055546 A CA 002055546A CA 2055546 A CA2055546 A CA 2055546A CA 2055546 C CA2055546 C CA 2055546C
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- 230000003287 optical effect Effects 0.000 title claims abstract description 502
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 230000011664 signaling Effects 0.000 claims description 6
- 238000003491 array Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 23
- 208000034530 PLAA-associated neurodevelopmental disease Diseases 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 4
- 230000005281 excited state Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002674 ointment Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005513 bias potential Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0005—Switch and router aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q11/0066—Provisions for optical burst or packet networks
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Optical Communication System (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
In an optical self-routing network, N optical splitters are associated respectively with N inlet terminals for splitting an optical signal from the associated inlet terminal into M replicas of the optical signal. M optical combiners, associated respectively with M outlet terminals, combines N
optical signals incident thereon into a combined optical signal and couples it to the associated outlet terminal. M sets of N optical gates are connected between the N optical splitters and the M optical combiners.
Each optical gate allows passage of an optical signal incident thereon when it timely coincides with an electrical signal applied thereto. A
controller supplies a gate control electrical signal to the optical gates of each set during M successive intervals. Contention between optical packets simultaneously incident on the optical gates of the same set is resolved by the controller.
optical signals incident thereon into a combined optical signal and couples it to the associated outlet terminal. M sets of N optical gates are connected between the N optical splitters and the M optical combiners.
Each optical gate allows passage of an optical signal incident thereon when it timely coincides with an electrical signal applied thereto. A
controller supplies a gate control electrical signal to the optical gates of each set during M successive intervals. Contention between optical packets simultaneously incident on the optical gates of the same set is resolved by the controller.
Description
CA 020~46 1998-02-18 ,~"~
TITLE OF THE INVENTION
"Self-Routlng Network Using Optical Gate Array Driven by Control Voltages Coincldental With Packet Header Pulses"
RELATED APPLICATIONS
This application is related to Co-pending Canadian Patent Application Serial Number 2,041,316 flled April 26, 1991 and asslgned to the same assignee as the present applicatlon.
BACKGROUND OF THE INVENTION
The present lnventlon relates generally to optical self-routlng networks for routlng optical packets accordlng to the lnformatlon contained in the header of the packets.
In prlor art optlcal self-routlng network, as described in "Springer Series in Electronics and Photonics", Vol, 25, pages 193-195, an optlcal packet ls fed lnto a splltter in which it is split into two replicas of the input signal, one belng applied to an optical swltch havlng two outlet terminals, and the other to an optlcal correlator. The optlcal correlator generates an optlcal output if the header of the incoming packet contalns a predetermlned blt sequence.
The output of the correlator ls converted to an electrlcal signal, ampllfied and applied to the control electrode of the optlcal swltch to direct the incident light to one of its outlet terminals.
However, a serlous disadvantage of the prlor art system is that the clrcuit complexity and practlcal implementatlon require a vast amount of optical, electro-. ...
CA 020~46 1998-02-18 ' "_"~
optical and electronic components.
SUMMARY OF THE INVENTION
It ls therefore an ob~ect of the present lnventlon to provlde an optical self-routlng network which allows implementation with a smaller number of components.
Accordlng to the present inventlon there is provided an optical self-routing network for self-routing an optical packet having a header, comprising: N optical splltters associated respectlvely wlth N lnlet termlnals of the network, each of the splitters receiving an optical packet incident from the associated inlet termlnal and splittlng the lncldent optical packet into M replicas of the optical packet; M
optical combiners assoclated respectlvely wlth M outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident optlcal packets into a combined optical signal and coupling the comblned optlcal slgnal to the assoclated outlet termlnal; a plurallty of optlcal gates divided into M sets corresponding respectlvely to the M optlcal comblners, each optlcal gate establishing a path between input and output ends thereof upon tlme colncldence between llght energy and electrlcal energy applled thereto, each of the M sets comprlslng N optlcal gates correspondlng respectlvely to the N
optlcal splitters, the optlcal gates of each set being respectively connected at lnput ends thereof to the corresponding N optlcal splitters and connected at output ends thereof to the M optlcal comblner to whlch the set of the optical gates corresponds, each optlcal gate of each set CA 020~46 1998-02-18 .","._ receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica and said electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set during M successive intervals as said electrical energy.
Priority selection may be provided by the gate control means for selecting one of the optical packets which are simultaneously made to be incident on the optical gates of each set when contention or competition arises among the optical packets.
According to a first aspect of the priority selection, the gate control means supplies successively shifted gate control electrical signals respectively to the optical gates of each set. Thus one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electrical signals which are successively applied to the optical gates of the given set.
According to a second aspect of the priority selection, the optical gates of each set are commonly assigned a unique time interval, and those of the optical signals which are supplied to the optical gates of each set are successively shifted during the unique time interval. The gate control . ,, ,_ means exclusively causes one of the optical gates of each set to allow passage of an optical signal incident thereon when the incident optical signal is the earliest of the optical signals incident on the optical gates of the set.
- 2b -., ~
, CA 020~46 1998-02-18 According to a third specific aspect of the priority selection, the gate 2 control means simultaneously supplies gate control electrical signals of 3 different amplitudes respectively to the optical gates of each set so that 4 one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the amplitude of the gate control 6 electrical signal applied thereto is the highest of the signals applied to the 7 optical gates of the given set.
8 According to a fourth aspect of the priority selection, the gate control g means simultaneously supplies gate control electrical signals of different amplitudes respectively to the optical gates of each set so that one of the 11 optical gates of a given set exclusively allows passage of an optical signal 12 incident thereon when the light intensity of the incident optical signal is 13 the highest of the optical signals incident on the optical gates of the given 1 4 set.
In a preferred embodiment of this invention, the optical signals are 16 respectively carried on a plurality of wavelengths, and each of the optical 17 gates is selectively transmissive of an optical signal of one of the 1 8 wavelengths.
The present invention will be described in further detail with reference 21 to the accompanying drawings, in which:
2 2 Fig. 1 is a block diagram of the optical self-routing network according 2 3 to a first embodiment of the present invention;
24 Fig. 2 is a timing diagram associated with the first embodiment;
Fig. 3 is a block diagram of a modified form of the first embodiment 2 6 of this invention, Fig. 3a being a side view of each optical gate;
27 Fig. 4 is a block diagram of a second embodiment of the present 2 8 invention;
2 9 Fig. 5 is a timing diagram associated with Fig. 4;
CA 020~46 1998-02-18 Fig. 6 is a block diagram of a modified form of the second 2 embodiment of this invention;
3 Fig. 7 is a timing diagram associated with Fig. 6;
4 Fig. 8 is a block diagram of a third embodiment of the present invention;
6 Fig. 9 is a timing diagram associated with Fig. 8;
7 Fig. 10 is a block diagram of a modified form of the third 8 embodiment;
g Fig. 1 1 is a timing diagram associated with Fig. 10;
Fig. 12 is a block diagram of a fourth embodiment of this invention;
1 1 Fig. 13 is a timing diagram associated with Fig. 12;
12 Fig. 14 is a block diagram of a modified form of the fourth 1 3 embodiment;
4 Fig. 15 is a timing diagram associated with Fig. 14;
Fig. 16 is a block diagram of a fifth embodiment of this invention;
6 Fig. 17 is a timing diagram associated with Fig. 16;
7 Fig. 18 is a block diagram of a modified form of the fifth embodiment;
18 Fig. 19 is a timing diagram associated with Fig. 18;
19 Fig. 20 is a block diagram of a sixth embodiment of the present 2 0 invention, Fig. 20A showing details of the optical gates of Fig. 20;
21 Fig. 21 is a timing diagram associated with Fig. 20;
22 Fig. 22 is a block diagram of a modification of the sixth embodiment 23 of the present invention; and 24 Figs. 23A and 23B are timing diagrams associated with Fig. 22.
DETAILED DESCRIPTION
26 Referring now to Fig. 1, there is shown an optical self-routing network 27 according to a first embodiment of the present invention. For purposes of 2 8 disclosure, the self-routing network is shown as a 3 x 4 switch 29 configuration. The network has three inlet terminals 21, 22 and 23, three CA 020~46 1998-02-18 optical splitters 31, 32, 33 respectively coupled to the inlet terminals for 2 splitting a respective optical input into four replicas of the optical input. A
3 3 x 4 array of optical gates 411 ~ 434 are provided, the gates being 4 horizontally arranged to form three groups of four gates 4il, 4i2, 4i3 and s 4;4 (where i = 1, 2 and 3) and vertically arranged to form four sets of three 6 gates 41j, 42j and 43j (where j = 1, 2, 3 and 4). Different groups of optical 7 gates are associated respectively with optical splitters 31, 32, 33, and 8 different sets of the optical gates are associated respectively with optical 9 combiners 51, 52, 53 and 54, each of which provides a combined signal 10 of the respective optical inputs. The outputs of combiners 51, 52, 53 and 11 54 are coupled respectively to outlet terminals 61, 62, 63 and 64 of the 1 2 network.
13 All optical gates are driven by electrical pulses that are supplied from 14 a gate controller 10. The driving pulses have a particular timing and 15 amplitude pattern determined in a manner to be described in detail later.
16 From user stations, electrical signals in the form of packets are 17 transmitted on access lines Ll, L2 and L3 to respective line interface circuits 18 11~ 12, and 13. Overall control of the network is provided by a routing 1 9 controller 11 which is coupled to line interface circuits 1 1, 12, 13. Each packet from user stations contains a header followed by a sequence of 21 data bits. Routing controller 11 reads the header information of each 22 incoming packet, assigns one or more pulse positions, or time slots in the 23 header of that packet using amplitude and timing information from gate 24 controller 10, and instructs the associated interface circuit to insert one or more header pulses into the assigned time slots of the packet for routing it 2 6 to a desired outlet terminal. As will be described, the assignment of time 2 7 slots is determined in relation to the timing and amplitude patterns of the 28 driving pulses generated by the gate controller 10.
29 Each of the line interface circuits 11, 12, 13 includes an electro-optical CA 020~46 1998-02-18 converter. After header pulse insertion, the incoming packets are converted to optlcal signals to form the inputs to the network and supplied to optical splitters 31~ 32' 33 via inlet terminals 21, 22, 23 reSpectively-As described in the aforesaid co-pending Canadian patent application and in a paper by I. Ogura et al, titled "A
Novel Switch Surface Transmission Electro-photonic Device"
(The 22nd International Conference on Solid-State Devices and Materials, 1990), each of the optical gates 4 is a gate-controlled, hetero~unction semiconductor device which is excited when optical energy incident thereon timely coincides with a short-duration, high triggering potential at the gate and remains excited by a long-duration, low bias potential that follows. During this excited state, the incident optical energy is allowed to pass through the device.
As shown in Fig. 2, gate controller 10 generates control voltage pulses C1, C2, C3 and C4, each having a high triggering voltage VH of duration T that exists anywhere between times t1 and t5 and a trailing, low bias voltage VL
that exists until time t8. Control pulses C1, C2, C3 and C4 are respectively applied to conductors 71~ 72' 73 and 74 that lead to the optlcal gates 4il' 4i2, i3 i4 and 3 respectively, as shown in Fig. 1. It is assumed that incoming optical packets P1, P2 and P3 appear at inlet terminals 21, 22 and 23, respectively. If the destinations of packets P1, P2 and P3 are such that they should be routed to outlet terminals 61, 62 and 63 respectively, then header pulses Pla, P2a and P3a are respectively inserted by interface ' CA 020~46 1998-02-18 circuits 11, 12 and 13 into time slots (or header slots) tl-t2, t2-t3, t3-t4 of optical packets Pl, P2 and P3. In thls way, header pulses Pla, P2a and P3a respectlvely coincide with the trlggerlng voltages VH of control pulses Cl, C2 and C3.
Note that data bits of each optical packet occupy the same lnterval between tlmes t6 and t7.
In response to the coincidence between the triggering voltage VH of pulse Cl and header pulse Pla, optical gate 411 changes to an excited state and malntalns lt under the influence of the tralling bias voltage VL. Thus, optical packet Pl is allowed to pass through gate 411 to optlcal comblner 51 and appears at outlet termlnal 61.
Llkewlse, the colncldence between the trlggerlng voltage VH of pulse C2 and header pulse P2a causes optlcal gate 422 to be exclted, allowlng optlcal packet P2 to be routed to outlet terminal 62 and the colncldence between the trlggerlng voltage VH ~f pulse C3 and header pulse P3a causes optlcal gate 433 to be excited, allowlng packet P3 to be routed to outlet terminal 63. It is seen that lf any of these packets ls destlned to outlet termlnal 64, a header pulse wlll be lnserted ln time slot t4-t5 of the packet. In thls way, an optlcal input to any one of splitters 31~ 32' 33 can be routed through the network to any one of outlet termlnals 61, 62, 63 and 64 by controlllng the posltlon of header pulses.
A flexible arrangement of the self-routing network can be implemented by a modlfled form of the lnventlon as shown ln Flg.3. In thls modlflcatlon, half-silvered mirrors 30 are posltloned between optlcal splltters 31' 32' 33 and the . ,~
CA 020~46 1998-02-18 optical gate array, and an array of optlcal lenses 31 are dlsposed on the outputs of splitters 31' 32 and 33 to dlrect thelr output llght beams through the half-sllvered mlrrors to the assoclated optlcal gates. Optlcal lenses 32 are dlsposed on the lnput ends of the comblners 51' 52' 53 and 54 to focus lncident llght beams to the comblners. Each optlcal gate 41 is provlded wlth a reflecting mirror 33 at one end of the device remote from the associated optical splitters as shown ln Flg, 3a. When each of the optlcal gates ls exclted, the light incldent thereon ls reflected off the wall 33 to the half-sllvered mirror through whlch lt has passed and where lt bends lts course at rlght angles to a correspondlng one of lenses 32.
Due to posslble timlng lnaccuracles, two or more header pulses may occur during the period of the same triggering voltage. In such sltuatlons, colllslon occurs at the lnputs of an optlcal combiner to which the packets are destined. The followlng embodlments overcome thls data colllslon problem.
A second embodlment of this lnventlon ls shown in Flg. 4 whlch dlffers from the Flg. 1 embodlment by the incluslon of a serles-connected reslstor-delay circuit in each of the gate control llnes 7; (where ~ = 1, 2, 3 and 4) that e~tend from gate controller lOa to optlcal gates 41~. Each control llne 7~ lncludes a reslstor 8; and delay elements 91 and 92j, wlth the clrcult ~unctlon between reslstor 81 and delay element 92j belng connected to optlcal gate 43~ and the iunctlon between delay elements 92j and 91~ belng connected to CA 020~46 1998-02-18 optlcal gate 42~. Gate control pulses C~ are successively generated at lntervals T equal to the duration of the header pulse, and delayed by delay elements 92~ and 91i to successively produce delayed control pulses Cl;.
As shown in Fig. 5, each of the delay elements 9 introduces a delay time that is one-third of the duration T of the header pulse, and the triggering voltage of each control pulse is equal to the delay time T/3. In this way, optical gates 43~ 42j and 41~ are supplied with successively shlfted control pulses C3~, C2~ and Cl~, respectively. Therefore, each optical gate of the network of Fig. 4 has a unlque trlggerlng lnstant, and the header pulse of each packet successlvely colncldes wlth the trlggerlng voltage of a sequence of three control pulses.
Due to the provlslon of the reslstor 8~ ln each column "~" of the gate array, excltatlon of one of the optlcal gates of a glven column causes a voltage drop to occur across the reslstor, As a result, when one of the gates of a glven column is excited the voltages applied to the other gates of the column located downstream of the exclted gate are not exclted even if their trlggerlng voltages colncide with a header pulse.
Assume that packets Pl and P2 on inlet termlnals 2 and 22 are destlned to outlet terminal 61 and packet P3 ls destined to outlet terminal 62. In order for packets Pl and P2 to arrlve at outlet termlnal 61 and for packet P3 to arrlve at terminal 62, it ls necessary that header pulses Pla and P2a should colnclde wlth control pulses Cll and C21, respectlvely, g CA 020~46 1998-02-18 '=_ and header pulse P3a should colncide wlth control pulse C32 as seen from Flg. 4. Therefore, header pulses Pla and P2a are inserted to the sarne interval tl-t4, and header pulse P3a is lnserted ln the interval t4-t7 as shown in Flg. 5. If this conditlon occurs, a coincldence occurs in gate 421 between header pulse P2a and the triggering voltage of pulse C21 earlier than a coincldence that occurs ln gate 411 between header pulse P2a and the trlggering voltage of pulse Cll, generating a voltage drop across resistor 81 immedlately followlng the excltatlon of gate 421. Because of the voltage drop, the voltage at the gate 411 ls too low for lt to be exclted, while gate 421 remains in the excited state. Packet P2 is thus allowed to pass through gate 421 to outlet terminal 61 whlle packet Pl is prevented from passing through gate 411.
On the other hand, header pulse P3a colncldes with the trlggerlng voltage of pulse C32, allowing gate 432 to transmit packet P3 to outlet terminal 62. Although not shown in the drawing, some provision will be made ln the network so that the fact that packet Pl ls corrupted as a result of a collislon or contentlon ls communlcated to the orlginating user for retransmission of a copy of the packet. It is seen that to avold collision between packets Pl, P2 and P3 it ls necessary that the header pulse of each packet exlst ln one of four discrete time intervals tl-t4, t4-t7, t7-tlo and tlo-tl3.
Returning brlefly to Flg. 2, lf the trlggerlng voltage of control pulse Cl ls delayed sllghtly wlth respect to its correct position, the successlve header pulses Pla and P2a would sequentlally coinclde with lt. This would result in .
CA 0205~46 1998-02-18 a collision between packets Pl and P2 at optical gates 411 and 421. Such a collision is avoided by an embodlment shown in Fig. 6. The embodiment of Fig. 6 is implemented by modifying Flg. 4 ln whlch all delay elements of Fig. 4 are removed from the gate array, directly coupling the voltage-dropping resistors to the associated optical gates. As shown in Flg.
7, this embodiment dlffers from Fig. 4 embodiment in that the trlggering voltage of each control pulse C; has a duration T, applying the same control pulse to the gates of the same column, and the header pulse of each optical packet has one-thlrd of the duration T. Control pulses Cl, C2, C3 and C4 are successively generated at T-intervals.
Assume that control pulse Cl ls delayed so that its trlggerlng hlgh voltage portlon successlvely colncldes wlth headers Pla and P2a (Fig. 2). However, due to the fact that the earlier occurrence of header pulse Pla generates a voltagé
drop across resistor 81 and the voltage at the gate 421 ls lowered to a level not sufficient to cause it to exclte in response to header pulse P2a. Therefore, packet Pl is passed through gate 411' whlle packet P2 is blocked at gate 421.
Header pulse P3a is assumed to be assigned a position that coincldes with the triggering voltage of ~ontrol pulse C2.
Gate 432 ls thus excited, allowing packet P3 to be routed to combiner 52.
A third embodiment of the present invention is shown in Fig. 8. Thls embodlment differs from the Fig. 1 embodiment by the lnclusion of a fourth group of optical gates 415 ~ 418~
a flfth group of optical gates 425 ~ 428' and a slxth group of ,~
CA 020~S~46 1998-02-18 optical gates 435 ~ 438' wlth the optlcal gates of the fourth, flfth and sixth groups being respectively connected to the outputs of the optical gates of the first, second and third groups. Controller lOc drives the optical gates of the fourth, fifth and sixth groups through control lines 75 ~ 78 (=7~+4, where ~=1, 2, 3 and 4~ extendlng to optlcal gates 415 ~ 418. Each of control lines 74+~ includes serles-connected resistors 101~, 102~ and 103~ wlth the ~unctlon between resistors 101~ and 102~ belng connected to optical gates 42(j+4) and the ~unctlon between resistors 102~ and 103; being connected to optical gates 43(j+4). The outputs of optlcal gates 41(i~4) are connected to the ith lnput of comblners 5~.
Controller lOc successlvely applles control pulses Cla, C2a, C3a and C4a to llnes 71 ~ 74 respectlvely, durlng a flrst interval between tlmes tl and tl3, and successively applies additional control pulses to llnes 75 ~ 78 durlng a second interval between tlmes tl3 and t25. These addltional pulses are indlcated by waveforms Cl~, C2b, C3b, and C4b ln Fig. 9 after experiencing a voltage drop by reslstors 1031, 1032, 1033 and 1034. The triggerlng voltage of each of these control pulses has a duration T and the header pulse of each packet has one-third of the duratlon T, as ln the Flg. 7 ernbodiment. The triggering voltages of pulses Clb, C2b, C3b and C4b on control lines 75 ~ 78 has a voltage level Vl after experlencing a voltage drop by resistors 1031, 1032, 1033 and 1034. When one of the optical gates connected to the same control line is exclted, the voltage at the ~unction of resistors 103~ and 102; drops to a lower level V2 and the ! .
~, CA 020~46 1998-02-18 voltage at the ~unction of resistors 102~ and 101~ drops to a lowest level V3. The optlcal gate whose trlggering voltage ls hlgher that any of the other gates of the same control llne ls glven prlorlty. Thus, lf a contentlon arlses ln any of the fourth, flfth and slxth groups of optical gatesl only one packet ls selected by the gate havlng prlorlty. To achleve the prlorlty selectlon, each optical packet has a second header pulse "b" whlch ls spaced from the flrst header pulse "a" by an interval equal to 4T.
Assume that the header pulses Pla and Plb of optlcal packet Pl are lnserted respectlvely to tlme slots tl - t2 and tl3 ~ tl4 and the header pulses P2a and P3a of packet P2 occurs ln the same tlme slots. The header pulses P3a, P3b of packet P3 are assumed to be lnserted to posltlons t4 ~ t5 and tl6 ~ tl7. Since header pulses Pla and P2a colnclde wlth the triggerlng voltage of control pulse Cla, optical gates 411 and 421 are slmultaneously exclted, allowlng packets Pl and P2 to be forwarded to optical gates 415 and 425' respectlvely, whlle header pulse P3a excltes gate 432 upon colncldence wlth the triggerlng voltage of control pulse C2a, thus applying packets P3 and gate 436. Header pulse Plb coincldes wlth the triggerlng voltage of control pulse C"lb that is applled to gate 415' and the header pulse P26 colncldes wlth the triggering voltage of control pulse C'lb that is applied to gate 425. Therefore, the triggerlng voltage at gate 425 reduces to lower level V2, while the voltage at gate 415 reduces to lowest level V3 as lndlcated ln Flg. 9, glvlng priorlty to gate 425 ln passlng packet P2 to comblner 51.
- 12a -. , , ~ ~.
CA 020~46 1998-02-18 1~
Header pulse P3b then coincides wlth the triggerlng voltage of control pulse C2b at gate 436 and packet P3 ls passed through it to comblner 52.
A modlfled embodlment of Flg. 8 ls shown in Fig. 10 which differs from lt by the excluslon of reslstors 101~ and 102~ from the control llnes 7(j+4) and by the use of second header pulses havlng dlfferent light intensltles Sl, S2 and S3 as shown ln Flg. 11, wlth the llght intensltles havlng a relationship Sl ~ S2 ~ S3. Assume that all header pulses of packets Pl, P2 and P3 are lnserted to the same tlme slots as ln the Fig. 8 embodlment, and that thelr second header pulses Plb, P2b and P3b have light lntenslties Sl, S2 and S3, respectively. In the same manner as described ln the prevlous embodlment, packets Pl, P2 and P3 are passed through optlcal gates 411' 421 and 431 respectlvely, when thelr flrst header pulses Pla, P2a and P3a colncide wlth control pulses Cla and C2a and are dlrected to optlcal gates 415~ 425 and 436' respectlvely. Because of the hlghest llght lntenslty of header pulse Plb, colncldence between header pulse Pla and control pulse Clb causes gate 415 to draw a greater current for excltatlon than the current draw by gate 425. A sharp voltage drop thus develops across reslstor 1031, preventlng gate 425 from belng exclted. Thus, packet Pl ls glven prlorlty over contending packet P2, whlle packet P~ ls allowed - 12b -'"",~,_ to pass through gate 436 to combiner 52 without contentlon in response to lts second header pulse coinciding with control pulse C2b.
A fourth embodiment of this invention is shown in Fig. 12 as 4 x 2 - 12c -., CA 020~46 1998-02-18 switch configuration. Four optical splitters 31 ~ 34, each having two 2 outputs, are provided to receive incoming optical packets P1, P2, P3 and 3 P4, respectively. Optical gates 401 n (where n = 1 and 2) have their inputs 4 coupled respectively to the first (upper) outputs of splitters 301 and 3~2, s and optical gates 4~2n have their inputs coupled respectively to the first 6 outputs of splitters 303 and 304. Similarly, optical gates 4~3n have their 7 inputs coupled respectively to the second (lower) outputs of splitters 301 8 and 3~2, and optical gates 4~4n have their inputs coupled respectively to 9 the second outputs of splitters 303 and 304. Optical combiners 50m 10 (where m = 1, 2, 3 and 4) are associated respectively with optical gates 11 40mn. Each combiner 50m has two inputs which are connected to the 12 outputs of the associated optical gates 4mn. The outputs of combiners 13 50m are connected respectively to optical gates 41 m. The outputs of 14 gates 411 and 412 are respectively coupled by optical combiner 505 to 1 s outlet terminal 601, those of gates 413 and 414 being coupled by 16 combiner 5~6 to outlet terminal 602.
17 Gate controller 1Od generates four control pulses C1, C2, C3 and 4.
18 Control pulse C1 is supplied to gate 401 1 through resistors 112 and 111 1 9 and to gate 4~12 through resistor 1 12, the same pulse being applied to gate 4~21 through resistors 122 and 121 and to gate 4~22 through resistor 21 122, thus supplying differentvoltages C11, C12, C13 and C14 to gates 22 401 1, 4~12, 4~21 and 4~22, respectively. Likewise, control pulse C2 is 23 supplied to gate 4031 through resistors 132 and 1 31 and to gate 4~32 24 through resistor 132, the same pulse being applied to gate 4041 through 2 S resistors 142 and 141 and to gate 4~42 through resistor 142, thus 26 supplying different voltages C21, C22, C23 and C24 to gates 4~31, 4~32, 27 4~41 and 4~42, respectively. In like manner, control pulse C3 is applied to 28 gate 411 through resistors 152 and 151 and to gate 412 through resistor 2 9 152, and control pulse C4 is applied to gate 413 through resistors 162 and CA 020~46 1998-02-18 161 and to gate 412 through resistor 162, thus supplying ditrere"t 2 voltages C31, C32, C41 and C42 to gates 411, 412, 413 and 414, 3 respectively. It is seen that gates 4~12, 4~22, 4~32, 4~42, 412 and 414 are 4 given priority over their companion gates 401 1, 4~21, 4~32, 4~41, 411 and s 413, when coincidence occurs between incoming header pulses and their 6 gate control pulses. The self-routing network of this configuration can be 7 said to operate on a successive "tournament" basis as will be understood 8 with reference to Fig. 13.
9 As shown in Fig. 13, the triggering voltage of each control pulse has a 10 duration T equal to the duration of each header pulse. Timing margins 11 are provided between the leading edges of successive gate control 12 pulses. For purposes of clarity, the timing margins are set equal to the 13 duration T. Assume that a contention is likely to occur between the 14 header pulses P1b and P3b of packets P1 and P3 and between the 15 header pulses P2b and P4b of packets P2 and P4.
16 The header pulse P1 a of packet P1 coincides with control pulse C11 at 17 gate 401 1 without contention with gate 4~12, allowing the packet to be 18 routed through combiner 50l to output gate 411~ while the header pulse 1 9 P3a of packet P3 coincides with control pulse C1 3 at gate 4~21 without 20 contention with gate 4~22, routing the packet through combiner 5~2 to 21 output gate 412. In like manner, the header pulse P2a of packet P2 2 2 coincides with control pulse C22 at gate 4~32 without contention with gate 23 4~31, allowing the packet to be routed through combiner 503 to output 24 gate 413, while the header pulse P4a of packet P4 coincides with control 2 5 pulse C24 at gate 4~42 without contention with gate 4041, routing the 2 6 packet through combiner 504 to output gate 414.
27 Contention occurs between the header pulses P1 b and P3b at gates 28 411 and 412 as they are simultaneously supplied with the triggering 2 9 voltages of control pulses C31 and C32. Since control pulse C32 has a CA 020~46 1998-02-18 .".~
hiaher trlggering voltage than control pulse C31, gate 412 wlns the contentlon, passlng packet P3 through combiner 505 to outlet terminal 601. A slmllar sltuatlon occurs between the header pulses P2b and P4b at gates 413 and 414, as they are simultaneously supplled wlth the trlggerlng voltages of control pulses C41 and C42. Because of the higher triggering voltage gate 414 wins the contention for transmitting packet P4 to outlet terminal 602. If a contentlon occurs between lnput gates 4011 and 4~12 (where 1= 1, 2, 3, 4), gate 4~12 ls alwàys the winner by vlrtue of thelr higher trlggerlng voltage.
An embodlment shown ln Fig. 14 ls a modlflcatlon of the embodlment of Flg. 12, the dlfference being ln the excluslon of reslstors 111, 121, 131, 141, 151 and 161 so that equal triggering voltages (Cla, Clb, C2a, C2b, 3a' 4a supplied to the optical gates of contending partners (pairs) and in the generation of header pulses having different light intensltles as seen from Flg. 15. As lllustrated, the header pulses are assumed to occur ln the same tlme slots as ln the case of Flg. 14. As ln the previous embodlment, packets Pl and P3 are routed through lnput gates wlthout contentlon to output gates 411 and 412 between whlch contentlon arises, and the other packets are routed to output gates 413 and 414 between which contentlon arlses. The header pulses of packet Pl have the hlghest llght lntenslty, and those of packets P2, P3 and P4 have decreaslng llght lntensltles ln the order given. Slnce header pulses Plb and P2b have a hlgher llght lntensity than those of the contending packets, packets routed "~
CA 020~46 1998-02-18 ~ .
to output gates 411 and 413 are the winners of the contentions, so that Pl is passed through combiner 505 to outlet terminal 601 and P2 is passed through comblner 5~6 to outlet terminal 602.
A self-routlng network of a 4 X 2 swltch conflguratlon can also be implemented ln a slngle contentlon stage for each outlet terrninal as shown in Flg. 16. Optlcal gates 411 ~ 424 are coupled respectively to the first outputs of splitters 301 - 304 for resolving a contention among packets destined to outlet termlnal 601 through combiner 501, and optical gates 431 ~ 434 are coupled respectlvely to the second outputs of splltters 301 ~ 304 for resolvlng a contentlon among packets that are destlned for outlet termlnal 6~2 through combiner 5~2 Gate controller 10e supplies a control pulse Cl through series-connected resistors 174, 173, 172 and 171 to develop successively decreaslng control g C14, C13, C12 and Cll for coupllng to gates 42 42 422 and 421, respectlvely. Llkewlse, gate controller 10e further supplles a control pulse C2 through serles-connected reslstors 184, 183, 182 and 181 to develop successlvely decreaslng control voltages C24, C23, C22, and C21 for coupllng to gates 434~ 433~ 432' and 431~ respectlvely.
As shown ln Flg. 17, each optlcal packet has a single header pulse. If header pulse Pla and P3a occur ln the same time slot t so that packets Pl and P3 are destined to l-t2 outlet terminal 601 and header pulse P2a and P4a occur in the same time slot t2-t3 so that packets P2 and P4 are destined to outlet terminal 602, contention occurs at gates 421 and 423 as CA 020~46 1998-02-18 well as gates 432 and 434 as packets Pl and P3 colncide with control pulses Cll and C13, respectlvely, and the other packets P2 and P4 coincide with control pulses C22 and C24, respectlvely. Slnce gate 423 ls supplled wlth a hlgher trlggerlng voltage than the voltage supplled to gate 421, packet P3 wlns the race for contentlon with packet Pl. In a similar manner, if gate 434 is supplied with a higher triggering voltage than the voltage at gate 431' packet P4 is the winner.
Fig 18. is a modification of the embodiment of Fig.
16, the difference being the exclusion of reslstors 171 ~ 173 and resistors 181 - 183, so that equal triggering voltages (C'l and C'2~ are supplied to the optical gates of contending partners (sets) and in the generatlon of header pulses having different light intensities, as seen from Fig. 19. As illustrated, the header pulses are assumed to occur in the same time slots as in the case of Fig. 17. As in the previous embodlment, packets Pl and P3 are applied to gates 421 and 423, respectlvely, and packets P2 and P4 are applled to gates 432 and 434, respectlvely. As shown, ln Flg. 19, the header pulses of packet Pl have the highest light intensity, and those of packets P2, P3 and P4 have decreasing llght intensities in the order given. Since header pulses Plb and P2b have a higher light intensity than those of the contendlng packets, packet Pl and P2 supplied to gates 421 and 432 are the wlnners of the race to respective outlet terminals 601 and 6~2 ~
The length of a header increases with the amount of .~ , CA 020~46 1998-02-18 traffic to be carrled by the self-routing network. The header length can be conserved by multlplexlng optlcal packets upon different llght wavelengths. The wavelength rnultlplexing concept of thls lnventlon for two wavelengths ls implemented by a 2 x 4 network conflguration as shown ln Fig. 20.
Electrical packets Pl and P2 from a user statlon are successively transmltted on access llne Ll and received by llne lnterface 1'1 and packets P3 and P4 from another user statlon are successively transmitted on access line L2 and received by llne lnterface 1'2. Routlng controller 120 is coupled to the llne interfaces, determines a wavelength and a header time slot according to the lnformatlon contalned ln a packet recelved from the assoclated lnterface ln relatlon to the timing and amplitude pattern of the gate control pulses supplled from gate controller 10f, and lnstructs the lnterface to carry the packet on the determined wavelength and lnsert a header pulse lnto the determlned time slot. For purposes of illustrationl packets Pl and P2 are converted by line interface 1'1 to optlcal slgnals of wavelength Al, and packets P3 and P4 are converted by line interface 1'2 to optical slgnals of wavelengths A2 and Al, respectlvely. The outputs of interfaces 1'1 and 1'2 are connected respectively by light waveguides 701 and 7~2 to optlcal splitters 801 and 802, each having four outputs. Optical gates 9~11' 9~12~ 9~13 and 9~14 are connected respectlvely to the outputs of splltters 801r and gates g011 and 9~12 are tuned to wavelength ~1~ and gates 9~13 and 9~14 are turned to wavelength A2. Optlcal gates 9~21' 9~22' 9~23 and 9~24 are likewise connected to the '~, CA 020~46 1998-02-18 outputs of splitter 802, with gates 9~21 and 9~22 being tuned to wavelength A1 and gates 9~23 and 9~24 belng tuned to wavelength ~2. The outputs of gates 90i~(~=1,2,3,4) are connected respectlvely to the flrst lnputs of comblners 100 and the outputs of gates 9~2~ are connected to the second inputs of comblners 100~. Gate controller lOf supplies control pulses C1 and C2 to gates 9~11 and 9~i2 (1=1, 2) and control pulses C3 and C4 to gates 9~13 and 9~14.
As shown in Fig. 20A, each of the optical gates 90i~
ls preferably constructed of a narrow-band wavelength tunable optlcal element 85 and a wlde-band wavelength tunable optlcal element 86 coupled together and arranged in the path of incident light beam.
As illustrated in Fig. 21, the triggering voltages of all control pulses C1 ~ C4 have equal amplitude VH for gate excltatlon, with the trlggerlng voltages of pulses Cl and C3 having an equal time slot t1-t2 and those of pulses C2 and C4 having an equal tlme slot t2-t3. Accordlng to dlfferent wavelengths, control pulses Cl and C2 have a tralllng voltage VL1 for tuning to wavelength ~1' whlle the traillng voltage of pulses C3 and C4 is set equal to VL2 for tuning the wavelength Assume that header pulses Pla and P2a for packets Pl(ll) and P2(~1) are lnserted lnto the same time slot tl-t2 of successive headers and the header pulse P3a of packet P3( 2) ls lnserted to the time slot t1-t2 of an inltial - 18a -,1 ':~
header. The header pulse P4a and packet P4(A1) ls assumed to be inserted in the time slot t2-t3 of a subsequent header.
It is seen that header pulses Pla and P2a successively coincide with - 18b -CA 020~46 1998-02-18 control pulse C1 at gate 9~11~ so packets P1(~1) and P2(~1) are routed to 2 an outlet terminal 1 101 via combiner 1001. Header pulse P3a coincides 3 with control pulse C3 at gate 9~23, allowing packet P3(~2) to be routed to 4 outlet terminal 1103 via combiner 1003. In like manner, header pulse P4a S coincides with control pulse C2 at gate 9~22, routing packet P4(~1) to 6 outlet terminal 1102 via combiner 1002.
7 However, data collision is likely to occur between packets of the same 8 wavelength at the inputs of a combiner 100 if their header pulses are g inserted to successive time slots of the same header and partially coincide 0 with a control pulse due to timing inaccuracies. To resolve the collision 11 problem, the embodiment of Fig. 20 is modified as shown in Fig. 22 in 12 which the network is implemented in a 4 x 2 switch configuration. Optical 13 splitters 801, 802, 803 and 804, arranged to receive optical packets P1(~1), 14 P2(~2), P3(~1) and P4(~2) from waveguides 701~704, are connected 1 S respectively to wavelength tunable optical gates 911 j, 91 2j, 91 3j and 91 4j 16 (j=l, 2). The outputs of gates 91;1 and 91 i2 (i = 1, 2, 3, 4) are coupled to 17 the ith inputs of combiners 1 ~~l and 1002. Gates 91 il and 91 i2 are tuned18 to wavelength ~1 and ~2, respectively, and supplied with control pulses 19 C'1 and C'2 via resistors 191 and 192, respectively, from gate controller 21 As shown in Fig. 23A, gate control pulses C1 and C2 generated by 22 controller 109 have triggering voltages of a duration twice as long as the 23 duration of the header pulse. Assume that header pulses P1a and P2a 24 are inserted to time slot t1-t2, and header pulses P3a and P4a are assigned time slot t2-t3. It is seen that gate 911 1 is excited upon 26 coincidence between header pulse P1a and control pulse C'1, producing 27 a voltage drop across resistor 191 and allowing packet P1(~1) to be 28 routed to combiner 1001. Similarly, gate 9122 is excited upon coincidence 29 between header pulse P2a and control pulse C'2, producing a voltage CA 020~46 1998-02-18 drop across resistor 192 and allowing packet P2(~2) to be routed to 2 combiner 1002. However, due to the voltage drop across resistor 191, 3 gate 9131 is not excited and packet P3(~1) is the loser of the contention 4 with packet P1(~1). In like manner, packet P4(~2) is the loser of the s contenbon with packet P2(~2).
6 Alternatively, the triggering voltages of all control pulses are of equal 7 duration to the duration of the header pulse and the header of each 8 packet has different light intensities as shown in Fig. 23B. In this way, 9 packets P1-P4 have decreasing levels of priority ;n the order named so 10 that contention between packets P1 and P3 at gates 911 1 and 9131 is 11 resolved by giving priority to packet P1, while contenbon between 12 packets P2 and P4 is resolved by giving priority to packet P2.
13 The foregoing description shows only preferred embodiments of the 14 present invention. Various modifications are apparent to those skilled in 15 the art without departing from the scope of the present invention which is 16 only limited by the appended claims. Therefore, the embodiments 17 shown and described are only illustrative, not restrictive.
TITLE OF THE INVENTION
"Self-Routlng Network Using Optical Gate Array Driven by Control Voltages Coincldental With Packet Header Pulses"
RELATED APPLICATIONS
This application is related to Co-pending Canadian Patent Application Serial Number 2,041,316 flled April 26, 1991 and asslgned to the same assignee as the present applicatlon.
BACKGROUND OF THE INVENTION
The present lnventlon relates generally to optical self-routlng networks for routlng optical packets accordlng to the lnformatlon contained in the header of the packets.
In prlor art optlcal self-routlng network, as described in "Springer Series in Electronics and Photonics", Vol, 25, pages 193-195, an optlcal packet ls fed lnto a splltter in which it is split into two replicas of the input signal, one belng applied to an optical swltch havlng two outlet terminals, and the other to an optlcal correlator. The optlcal correlator generates an optlcal output if the header of the incoming packet contalns a predetermlned blt sequence.
The output of the correlator ls converted to an electrlcal signal, ampllfied and applied to the control electrode of the optlcal swltch to direct the incident light to one of its outlet terminals.
However, a serlous disadvantage of the prlor art system is that the clrcuit complexity and practlcal implementatlon require a vast amount of optical, electro-. ...
CA 020~46 1998-02-18 ' "_"~
optical and electronic components.
SUMMARY OF THE INVENTION
It ls therefore an ob~ect of the present lnventlon to provlde an optical self-routlng network which allows implementation with a smaller number of components.
Accordlng to the present inventlon there is provided an optical self-routing network for self-routing an optical packet having a header, comprising: N optical splltters associated respectlvely wlth N lnlet termlnals of the network, each of the splitters receiving an optical packet incident from the associated inlet termlnal and splittlng the lncldent optical packet into M replicas of the optical packet; M
optical combiners assoclated respectlvely wlth M outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident optlcal packets into a combined optical signal and coupling the comblned optlcal slgnal to the assoclated outlet termlnal; a plurallty of optlcal gates divided into M sets corresponding respectlvely to the M optlcal comblners, each optlcal gate establishing a path between input and output ends thereof upon tlme colncldence between llght energy and electrlcal energy applled thereto, each of the M sets comprlslng N optlcal gates correspondlng respectlvely to the N
optlcal splitters, the optlcal gates of each set being respectively connected at lnput ends thereof to the corresponding N optlcal splitters and connected at output ends thereof to the M optlcal comblner to whlch the set of the optical gates corresponds, each optlcal gate of each set CA 020~46 1998-02-18 .","._ receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica and said electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set during M successive intervals as said electrical energy.
Priority selection may be provided by the gate control means for selecting one of the optical packets which are simultaneously made to be incident on the optical gates of each set when contention or competition arises among the optical packets.
According to a first aspect of the priority selection, the gate control means supplies successively shifted gate control electrical signals respectively to the optical gates of each set. Thus one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electrical signals which are successively applied to the optical gates of the given set.
According to a second aspect of the priority selection, the optical gates of each set are commonly assigned a unique time interval, and those of the optical signals which are supplied to the optical gates of each set are successively shifted during the unique time interval. The gate control . ,, ,_ means exclusively causes one of the optical gates of each set to allow passage of an optical signal incident thereon when the incident optical signal is the earliest of the optical signals incident on the optical gates of the set.
- 2b -., ~
, CA 020~46 1998-02-18 According to a third specific aspect of the priority selection, the gate 2 control means simultaneously supplies gate control electrical signals of 3 different amplitudes respectively to the optical gates of each set so that 4 one of the optical gates of a given set exclusively allows passage of an optical signal incident thereon when the amplitude of the gate control 6 electrical signal applied thereto is the highest of the signals applied to the 7 optical gates of the given set.
8 According to a fourth aspect of the priority selection, the gate control g means simultaneously supplies gate control electrical signals of different amplitudes respectively to the optical gates of each set so that one of the 11 optical gates of a given set exclusively allows passage of an optical signal 12 incident thereon when the light intensity of the incident optical signal is 13 the highest of the optical signals incident on the optical gates of the given 1 4 set.
In a preferred embodiment of this invention, the optical signals are 16 respectively carried on a plurality of wavelengths, and each of the optical 17 gates is selectively transmissive of an optical signal of one of the 1 8 wavelengths.
The present invention will be described in further detail with reference 21 to the accompanying drawings, in which:
2 2 Fig. 1 is a block diagram of the optical self-routing network according 2 3 to a first embodiment of the present invention;
24 Fig. 2 is a timing diagram associated with the first embodiment;
Fig. 3 is a block diagram of a modified form of the first embodiment 2 6 of this invention, Fig. 3a being a side view of each optical gate;
27 Fig. 4 is a block diagram of a second embodiment of the present 2 8 invention;
2 9 Fig. 5 is a timing diagram associated with Fig. 4;
CA 020~46 1998-02-18 Fig. 6 is a block diagram of a modified form of the second 2 embodiment of this invention;
3 Fig. 7 is a timing diagram associated with Fig. 6;
4 Fig. 8 is a block diagram of a third embodiment of the present invention;
6 Fig. 9 is a timing diagram associated with Fig. 8;
7 Fig. 10 is a block diagram of a modified form of the third 8 embodiment;
g Fig. 1 1 is a timing diagram associated with Fig. 10;
Fig. 12 is a block diagram of a fourth embodiment of this invention;
1 1 Fig. 13 is a timing diagram associated with Fig. 12;
12 Fig. 14 is a block diagram of a modified form of the fourth 1 3 embodiment;
4 Fig. 15 is a timing diagram associated with Fig. 14;
Fig. 16 is a block diagram of a fifth embodiment of this invention;
6 Fig. 17 is a timing diagram associated with Fig. 16;
7 Fig. 18 is a block diagram of a modified form of the fifth embodiment;
18 Fig. 19 is a timing diagram associated with Fig. 18;
19 Fig. 20 is a block diagram of a sixth embodiment of the present 2 0 invention, Fig. 20A showing details of the optical gates of Fig. 20;
21 Fig. 21 is a timing diagram associated with Fig. 20;
22 Fig. 22 is a block diagram of a modification of the sixth embodiment 23 of the present invention; and 24 Figs. 23A and 23B are timing diagrams associated with Fig. 22.
DETAILED DESCRIPTION
26 Referring now to Fig. 1, there is shown an optical self-routing network 27 according to a first embodiment of the present invention. For purposes of 2 8 disclosure, the self-routing network is shown as a 3 x 4 switch 29 configuration. The network has three inlet terminals 21, 22 and 23, three CA 020~46 1998-02-18 optical splitters 31, 32, 33 respectively coupled to the inlet terminals for 2 splitting a respective optical input into four replicas of the optical input. A
3 3 x 4 array of optical gates 411 ~ 434 are provided, the gates being 4 horizontally arranged to form three groups of four gates 4il, 4i2, 4i3 and s 4;4 (where i = 1, 2 and 3) and vertically arranged to form four sets of three 6 gates 41j, 42j and 43j (where j = 1, 2, 3 and 4). Different groups of optical 7 gates are associated respectively with optical splitters 31, 32, 33, and 8 different sets of the optical gates are associated respectively with optical 9 combiners 51, 52, 53 and 54, each of which provides a combined signal 10 of the respective optical inputs. The outputs of combiners 51, 52, 53 and 11 54 are coupled respectively to outlet terminals 61, 62, 63 and 64 of the 1 2 network.
13 All optical gates are driven by electrical pulses that are supplied from 14 a gate controller 10. The driving pulses have a particular timing and 15 amplitude pattern determined in a manner to be described in detail later.
16 From user stations, electrical signals in the form of packets are 17 transmitted on access lines Ll, L2 and L3 to respective line interface circuits 18 11~ 12, and 13. Overall control of the network is provided by a routing 1 9 controller 11 which is coupled to line interface circuits 1 1, 12, 13. Each packet from user stations contains a header followed by a sequence of 21 data bits. Routing controller 11 reads the header information of each 22 incoming packet, assigns one or more pulse positions, or time slots in the 23 header of that packet using amplitude and timing information from gate 24 controller 10, and instructs the associated interface circuit to insert one or more header pulses into the assigned time slots of the packet for routing it 2 6 to a desired outlet terminal. As will be described, the assignment of time 2 7 slots is determined in relation to the timing and amplitude patterns of the 28 driving pulses generated by the gate controller 10.
29 Each of the line interface circuits 11, 12, 13 includes an electro-optical CA 020~46 1998-02-18 converter. After header pulse insertion, the incoming packets are converted to optlcal signals to form the inputs to the network and supplied to optical splitters 31~ 32' 33 via inlet terminals 21, 22, 23 reSpectively-As described in the aforesaid co-pending Canadian patent application and in a paper by I. Ogura et al, titled "A
Novel Switch Surface Transmission Electro-photonic Device"
(The 22nd International Conference on Solid-State Devices and Materials, 1990), each of the optical gates 4 is a gate-controlled, hetero~unction semiconductor device which is excited when optical energy incident thereon timely coincides with a short-duration, high triggering potential at the gate and remains excited by a long-duration, low bias potential that follows. During this excited state, the incident optical energy is allowed to pass through the device.
As shown in Fig. 2, gate controller 10 generates control voltage pulses C1, C2, C3 and C4, each having a high triggering voltage VH of duration T that exists anywhere between times t1 and t5 and a trailing, low bias voltage VL
that exists until time t8. Control pulses C1, C2, C3 and C4 are respectively applied to conductors 71~ 72' 73 and 74 that lead to the optlcal gates 4il' 4i2, i3 i4 and 3 respectively, as shown in Fig. 1. It is assumed that incoming optical packets P1, P2 and P3 appear at inlet terminals 21, 22 and 23, respectively. If the destinations of packets P1, P2 and P3 are such that they should be routed to outlet terminals 61, 62 and 63 respectively, then header pulses Pla, P2a and P3a are respectively inserted by interface ' CA 020~46 1998-02-18 circuits 11, 12 and 13 into time slots (or header slots) tl-t2, t2-t3, t3-t4 of optical packets Pl, P2 and P3. In thls way, header pulses Pla, P2a and P3a respectlvely coincide with the trlggerlng voltages VH of control pulses Cl, C2 and C3.
Note that data bits of each optical packet occupy the same lnterval between tlmes t6 and t7.
In response to the coincidence between the triggering voltage VH of pulse Cl and header pulse Pla, optical gate 411 changes to an excited state and malntalns lt under the influence of the tralling bias voltage VL. Thus, optical packet Pl is allowed to pass through gate 411 to optlcal comblner 51 and appears at outlet termlnal 61.
Llkewlse, the colncldence between the trlggerlng voltage VH of pulse C2 and header pulse P2a causes optlcal gate 422 to be exclted, allowlng optlcal packet P2 to be routed to outlet terminal 62 and the colncldence between the trlggerlng voltage VH ~f pulse C3 and header pulse P3a causes optlcal gate 433 to be excited, allowlng packet P3 to be routed to outlet terminal 63. It is seen that lf any of these packets ls destlned to outlet termlnal 64, a header pulse wlll be lnserted ln time slot t4-t5 of the packet. In thls way, an optlcal input to any one of splitters 31~ 32' 33 can be routed through the network to any one of outlet termlnals 61, 62, 63 and 64 by controlllng the posltlon of header pulses.
A flexible arrangement of the self-routing network can be implemented by a modlfled form of the lnventlon as shown ln Flg.3. In thls modlflcatlon, half-silvered mirrors 30 are posltloned between optlcal splltters 31' 32' 33 and the . ,~
CA 020~46 1998-02-18 optical gate array, and an array of optlcal lenses 31 are dlsposed on the outputs of splitters 31' 32 and 33 to dlrect thelr output llght beams through the half-sllvered mlrrors to the assoclated optlcal gates. Optlcal lenses 32 are dlsposed on the lnput ends of the comblners 51' 52' 53 and 54 to focus lncident llght beams to the comblners. Each optlcal gate 41 is provlded wlth a reflecting mirror 33 at one end of the device remote from the associated optical splitters as shown ln Flg, 3a. When each of the optlcal gates ls exclted, the light incldent thereon ls reflected off the wall 33 to the half-sllvered mirror through whlch lt has passed and where lt bends lts course at rlght angles to a correspondlng one of lenses 32.
Due to posslble timlng lnaccuracles, two or more header pulses may occur during the period of the same triggering voltage. In such sltuatlons, colllslon occurs at the lnputs of an optlcal combiner to which the packets are destined. The followlng embodlments overcome thls data colllslon problem.
A second embodlment of this lnventlon ls shown in Flg. 4 whlch dlffers from the Flg. 1 embodlment by the incluslon of a serles-connected reslstor-delay circuit in each of the gate control llnes 7; (where ~ = 1, 2, 3 and 4) that e~tend from gate controller lOa to optlcal gates 41~. Each control llne 7~ lncludes a reslstor 8; and delay elements 91 and 92j, wlth the clrcult ~unctlon between reslstor 81 and delay element 92j belng connected to optlcal gate 43~ and the iunctlon between delay elements 92j and 91~ belng connected to CA 020~46 1998-02-18 optlcal gate 42~. Gate control pulses C~ are successively generated at lntervals T equal to the duration of the header pulse, and delayed by delay elements 92~ and 91i to successively produce delayed control pulses Cl;.
As shown in Fig. 5, each of the delay elements 9 introduces a delay time that is one-third of the duration T of the header pulse, and the triggering voltage of each control pulse is equal to the delay time T/3. In this way, optical gates 43~ 42j and 41~ are supplied with successively shlfted control pulses C3~, C2~ and Cl~, respectively. Therefore, each optical gate of the network of Fig. 4 has a unlque trlggerlng lnstant, and the header pulse of each packet successlvely colncldes wlth the trlggerlng voltage of a sequence of three control pulses.
Due to the provlslon of the reslstor 8~ ln each column "~" of the gate array, excltatlon of one of the optlcal gates of a glven column causes a voltage drop to occur across the reslstor, As a result, when one of the gates of a glven column is excited the voltages applied to the other gates of the column located downstream of the exclted gate are not exclted even if their trlggerlng voltages colncide with a header pulse.
Assume that packets Pl and P2 on inlet termlnals 2 and 22 are destlned to outlet terminal 61 and packet P3 ls destined to outlet terminal 62. In order for packets Pl and P2 to arrlve at outlet termlnal 61 and for packet P3 to arrlve at terminal 62, it ls necessary that header pulses Pla and P2a should colnclde wlth control pulses Cll and C21, respectlvely, g CA 020~46 1998-02-18 '=_ and header pulse P3a should colncide wlth control pulse C32 as seen from Flg. 4. Therefore, header pulses Pla and P2a are inserted to the sarne interval tl-t4, and header pulse P3a is lnserted ln the interval t4-t7 as shown in Flg. 5. If this conditlon occurs, a coincldence occurs in gate 421 between header pulse P2a and the triggering voltage of pulse C21 earlier than a coincldence that occurs ln gate 411 between header pulse P2a and the trlggering voltage of pulse Cll, generating a voltage drop across resistor 81 immedlately followlng the excltatlon of gate 421. Because of the voltage drop, the voltage at the gate 411 ls too low for lt to be exclted, while gate 421 remains in the excited state. Packet P2 is thus allowed to pass through gate 421 to outlet terminal 61 whlle packet Pl is prevented from passing through gate 411.
On the other hand, header pulse P3a colncldes with the trlggerlng voltage of pulse C32, allowing gate 432 to transmit packet P3 to outlet terminal 62. Although not shown in the drawing, some provision will be made ln the network so that the fact that packet Pl ls corrupted as a result of a collislon or contentlon ls communlcated to the orlginating user for retransmission of a copy of the packet. It is seen that to avold collision between packets Pl, P2 and P3 it ls necessary that the header pulse of each packet exlst ln one of four discrete time intervals tl-t4, t4-t7, t7-tlo and tlo-tl3.
Returning brlefly to Flg. 2, lf the trlggerlng voltage of control pulse Cl ls delayed sllghtly wlth respect to its correct position, the successlve header pulses Pla and P2a would sequentlally coinclde with lt. This would result in .
CA 0205~46 1998-02-18 a collision between packets Pl and P2 at optical gates 411 and 421. Such a collision is avoided by an embodlment shown in Fig. 6. The embodiment of Fig. 6 is implemented by modifying Flg. 4 ln whlch all delay elements of Fig. 4 are removed from the gate array, directly coupling the voltage-dropping resistors to the associated optical gates. As shown in Flg.
7, this embodiment dlffers from Fig. 4 embodiment in that the trlggering voltage of each control pulse C; has a duration T, applying the same control pulse to the gates of the same column, and the header pulse of each optical packet has one-thlrd of the duration T. Control pulses Cl, C2, C3 and C4 are successively generated at T-intervals.
Assume that control pulse Cl ls delayed so that its trlggerlng hlgh voltage portlon successlvely colncldes wlth headers Pla and P2a (Fig. 2). However, due to the fact that the earlier occurrence of header pulse Pla generates a voltagé
drop across resistor 81 and the voltage at the gate 421 ls lowered to a level not sufficient to cause it to exclte in response to header pulse P2a. Therefore, packet Pl is passed through gate 411' whlle packet P2 is blocked at gate 421.
Header pulse P3a is assumed to be assigned a position that coincldes with the triggering voltage of ~ontrol pulse C2.
Gate 432 ls thus excited, allowing packet P3 to be routed to combiner 52.
A third embodiment of the present invention is shown in Fig. 8. Thls embodlment differs from the Fig. 1 embodiment by the lnclusion of a fourth group of optical gates 415 ~ 418~
a flfth group of optical gates 425 ~ 428' and a slxth group of ,~
CA 020~S~46 1998-02-18 optical gates 435 ~ 438' wlth the optlcal gates of the fourth, flfth and sixth groups being respectively connected to the outputs of the optical gates of the first, second and third groups. Controller lOc drives the optical gates of the fourth, fifth and sixth groups through control lines 75 ~ 78 (=7~+4, where ~=1, 2, 3 and 4~ extendlng to optlcal gates 415 ~ 418. Each of control lines 74+~ includes serles-connected resistors 101~, 102~ and 103~ wlth the ~unctlon between resistors 101~ and 102~ belng connected to optical gates 42(j+4) and the ~unctlon between resistors 102~ and 103; being connected to optical gates 43(j+4). The outputs of optlcal gates 41(i~4) are connected to the ith lnput of comblners 5~.
Controller lOc successlvely applles control pulses Cla, C2a, C3a and C4a to llnes 71 ~ 74 respectlvely, durlng a flrst interval between tlmes tl and tl3, and successively applies additional control pulses to llnes 75 ~ 78 durlng a second interval between tlmes tl3 and t25. These addltional pulses are indlcated by waveforms Cl~, C2b, C3b, and C4b ln Fig. 9 after experiencing a voltage drop by reslstors 1031, 1032, 1033 and 1034. The triggerlng voltage of each of these control pulses has a duration T and the header pulse of each packet has one-third of the duratlon T, as ln the Flg. 7 ernbodiment. The triggering voltages of pulses Clb, C2b, C3b and C4b on control lines 75 ~ 78 has a voltage level Vl after experlencing a voltage drop by resistors 1031, 1032, 1033 and 1034. When one of the optical gates connected to the same control line is exclted, the voltage at the ~unction of resistors 103~ and 102; drops to a lower level V2 and the ! .
~, CA 020~46 1998-02-18 voltage at the ~unction of resistors 102~ and 101~ drops to a lowest level V3. The optlcal gate whose trlggering voltage ls hlgher that any of the other gates of the same control llne ls glven prlorlty. Thus, lf a contentlon arlses ln any of the fourth, flfth and slxth groups of optical gatesl only one packet ls selected by the gate havlng prlorlty. To achleve the prlorlty selectlon, each optical packet has a second header pulse "b" whlch ls spaced from the flrst header pulse "a" by an interval equal to 4T.
Assume that the header pulses Pla and Plb of optlcal packet Pl are lnserted respectlvely to tlme slots tl - t2 and tl3 ~ tl4 and the header pulses P2a and P3a of packet P2 occurs ln the same tlme slots. The header pulses P3a, P3b of packet P3 are assumed to be lnserted to posltlons t4 ~ t5 and tl6 ~ tl7. Since header pulses Pla and P2a colnclde wlth the triggerlng voltage of control pulse Cla, optical gates 411 and 421 are slmultaneously exclted, allowlng packets Pl and P2 to be forwarded to optical gates 415 and 425' respectlvely, whlle header pulse P3a excltes gate 432 upon colncldence wlth the triggerlng voltage of control pulse C2a, thus applying packets P3 and gate 436. Header pulse Plb coincldes wlth the triggerlng voltage of control pulse C"lb that is applled to gate 415' and the header pulse P26 colncldes wlth the triggering voltage of control pulse C'lb that is applied to gate 425. Therefore, the triggerlng voltage at gate 425 reduces to lower level V2, while the voltage at gate 415 reduces to lowest level V3 as lndlcated ln Flg. 9, glvlng priorlty to gate 425 ln passlng packet P2 to comblner 51.
- 12a -. , , ~ ~.
CA 020~46 1998-02-18 1~
Header pulse P3b then coincides wlth the triggerlng voltage of control pulse C2b at gate 436 and packet P3 ls passed through it to comblner 52.
A modlfled embodlment of Flg. 8 ls shown in Fig. 10 which differs from lt by the excluslon of reslstors 101~ and 102~ from the control llnes 7(j+4) and by the use of second header pulses havlng dlfferent light intensltles Sl, S2 and S3 as shown ln Flg. 11, wlth the llght intensltles havlng a relationship Sl ~ S2 ~ S3. Assume that all header pulses of packets Pl, P2 and P3 are lnserted to the same tlme slots as ln the Fig. 8 embodlment, and that thelr second header pulses Plb, P2b and P3b have light lntenslties Sl, S2 and S3, respectively. In the same manner as described ln the prevlous embodlment, packets Pl, P2 and P3 are passed through optlcal gates 411' 421 and 431 respectlvely, when thelr flrst header pulses Pla, P2a and P3a colncide wlth control pulses Cla and C2a and are dlrected to optlcal gates 415~ 425 and 436' respectlvely. Because of the hlghest llght lntenslty of header pulse Plb, colncldence between header pulse Pla and control pulse Clb causes gate 415 to draw a greater current for excltatlon than the current draw by gate 425. A sharp voltage drop thus develops across reslstor 1031, preventlng gate 425 from belng exclted. Thus, packet Pl ls glven prlorlty over contending packet P2, whlle packet P~ ls allowed - 12b -'"",~,_ to pass through gate 436 to combiner 52 without contentlon in response to lts second header pulse coinciding with control pulse C2b.
A fourth embodiment of this invention is shown in Fig. 12 as 4 x 2 - 12c -., CA 020~46 1998-02-18 switch configuration. Four optical splitters 31 ~ 34, each having two 2 outputs, are provided to receive incoming optical packets P1, P2, P3 and 3 P4, respectively. Optical gates 401 n (where n = 1 and 2) have their inputs 4 coupled respectively to the first (upper) outputs of splitters 301 and 3~2, s and optical gates 4~2n have their inputs coupled respectively to the first 6 outputs of splitters 303 and 304. Similarly, optical gates 4~3n have their 7 inputs coupled respectively to the second (lower) outputs of splitters 301 8 and 3~2, and optical gates 4~4n have their inputs coupled respectively to 9 the second outputs of splitters 303 and 304. Optical combiners 50m 10 (where m = 1, 2, 3 and 4) are associated respectively with optical gates 11 40mn. Each combiner 50m has two inputs which are connected to the 12 outputs of the associated optical gates 4mn. The outputs of combiners 13 50m are connected respectively to optical gates 41 m. The outputs of 14 gates 411 and 412 are respectively coupled by optical combiner 505 to 1 s outlet terminal 601, those of gates 413 and 414 being coupled by 16 combiner 5~6 to outlet terminal 602.
17 Gate controller 1Od generates four control pulses C1, C2, C3 and 4.
18 Control pulse C1 is supplied to gate 401 1 through resistors 112 and 111 1 9 and to gate 4~12 through resistor 1 12, the same pulse being applied to gate 4~21 through resistors 122 and 121 and to gate 4~22 through resistor 21 122, thus supplying differentvoltages C11, C12, C13 and C14 to gates 22 401 1, 4~12, 4~21 and 4~22, respectively. Likewise, control pulse C2 is 23 supplied to gate 4031 through resistors 132 and 1 31 and to gate 4~32 24 through resistor 132, the same pulse being applied to gate 4041 through 2 S resistors 142 and 141 and to gate 4~42 through resistor 142, thus 26 supplying different voltages C21, C22, C23 and C24 to gates 4~31, 4~32, 27 4~41 and 4~42, respectively. In like manner, control pulse C3 is applied to 28 gate 411 through resistors 152 and 151 and to gate 412 through resistor 2 9 152, and control pulse C4 is applied to gate 413 through resistors 162 and CA 020~46 1998-02-18 161 and to gate 412 through resistor 162, thus supplying ditrere"t 2 voltages C31, C32, C41 and C42 to gates 411, 412, 413 and 414, 3 respectively. It is seen that gates 4~12, 4~22, 4~32, 4~42, 412 and 414 are 4 given priority over their companion gates 401 1, 4~21, 4~32, 4~41, 411 and s 413, when coincidence occurs between incoming header pulses and their 6 gate control pulses. The self-routing network of this configuration can be 7 said to operate on a successive "tournament" basis as will be understood 8 with reference to Fig. 13.
9 As shown in Fig. 13, the triggering voltage of each control pulse has a 10 duration T equal to the duration of each header pulse. Timing margins 11 are provided between the leading edges of successive gate control 12 pulses. For purposes of clarity, the timing margins are set equal to the 13 duration T. Assume that a contention is likely to occur between the 14 header pulses P1b and P3b of packets P1 and P3 and between the 15 header pulses P2b and P4b of packets P2 and P4.
16 The header pulse P1 a of packet P1 coincides with control pulse C11 at 17 gate 401 1 without contention with gate 4~12, allowing the packet to be 18 routed through combiner 50l to output gate 411~ while the header pulse 1 9 P3a of packet P3 coincides with control pulse C1 3 at gate 4~21 without 20 contention with gate 4~22, routing the packet through combiner 5~2 to 21 output gate 412. In like manner, the header pulse P2a of packet P2 2 2 coincides with control pulse C22 at gate 4~32 without contention with gate 23 4~31, allowing the packet to be routed through combiner 503 to output 24 gate 413, while the header pulse P4a of packet P4 coincides with control 2 5 pulse C24 at gate 4~42 without contention with gate 4041, routing the 2 6 packet through combiner 504 to output gate 414.
27 Contention occurs between the header pulses P1 b and P3b at gates 28 411 and 412 as they are simultaneously supplied with the triggering 2 9 voltages of control pulses C31 and C32. Since control pulse C32 has a CA 020~46 1998-02-18 .".~
hiaher trlggering voltage than control pulse C31, gate 412 wlns the contentlon, passlng packet P3 through combiner 505 to outlet terminal 601. A slmllar sltuatlon occurs between the header pulses P2b and P4b at gates 413 and 414, as they are simultaneously supplled wlth the trlggerlng voltages of control pulses C41 and C42. Because of the higher triggering voltage gate 414 wins the contention for transmitting packet P4 to outlet terminal 602. If a contentlon occurs between lnput gates 4011 and 4~12 (where 1= 1, 2, 3, 4), gate 4~12 ls alwàys the winner by vlrtue of thelr higher trlggerlng voltage.
An embodlment shown ln Fig. 14 ls a modlflcatlon of the embodlment of Flg. 12, the dlfference being ln the excluslon of reslstors 111, 121, 131, 141, 151 and 161 so that equal triggering voltages (Cla, Clb, C2a, C2b, 3a' 4a supplied to the optical gates of contending partners (pairs) and in the generation of header pulses having different light intensltles as seen from Flg. 15. As lllustrated, the header pulses are assumed to occur ln the same tlme slots as ln the case of Flg. 14. As ln the previous embodlment, packets Pl and P3 are routed through lnput gates wlthout contentlon to output gates 411 and 412 between whlch contentlon arises, and the other packets are routed to output gates 413 and 414 between which contentlon arlses. The header pulses of packet Pl have the hlghest llght lntenslty, and those of packets P2, P3 and P4 have decreaslng llght lntensltles ln the order given. Slnce header pulses Plb and P2b have a hlgher llght lntensity than those of the contending packets, packets routed "~
CA 020~46 1998-02-18 ~ .
to output gates 411 and 413 are the winners of the contentions, so that Pl is passed through combiner 505 to outlet terminal 601 and P2 is passed through comblner 5~6 to outlet terminal 602.
A self-routlng network of a 4 X 2 swltch conflguratlon can also be implemented ln a slngle contentlon stage for each outlet terrninal as shown in Flg. 16. Optlcal gates 411 ~ 424 are coupled respectively to the first outputs of splitters 301 - 304 for resolving a contention among packets destined to outlet termlnal 601 through combiner 501, and optical gates 431 ~ 434 are coupled respectlvely to the second outputs of splltters 301 ~ 304 for resolvlng a contentlon among packets that are destlned for outlet termlnal 6~2 through combiner 5~2 Gate controller 10e supplies a control pulse Cl through series-connected resistors 174, 173, 172 and 171 to develop successively decreaslng control g C14, C13, C12 and Cll for coupllng to gates 42 42 422 and 421, respectlvely. Llkewlse, gate controller 10e further supplles a control pulse C2 through serles-connected reslstors 184, 183, 182 and 181 to develop successlvely decreaslng control voltages C24, C23, C22, and C21 for coupllng to gates 434~ 433~ 432' and 431~ respectlvely.
As shown ln Flg. 17, each optlcal packet has a single header pulse. If header pulse Pla and P3a occur ln the same time slot t so that packets Pl and P3 are destined to l-t2 outlet terminal 601 and header pulse P2a and P4a occur in the same time slot t2-t3 so that packets P2 and P4 are destined to outlet terminal 602, contention occurs at gates 421 and 423 as CA 020~46 1998-02-18 well as gates 432 and 434 as packets Pl and P3 colncide with control pulses Cll and C13, respectlvely, and the other packets P2 and P4 coincide with control pulses C22 and C24, respectlvely. Slnce gate 423 ls supplled wlth a hlgher trlggerlng voltage than the voltage supplled to gate 421, packet P3 wlns the race for contentlon with packet Pl. In a similar manner, if gate 434 is supplied with a higher triggering voltage than the voltage at gate 431' packet P4 is the winner.
Fig 18. is a modification of the embodiment of Fig.
16, the difference being the exclusion of reslstors 171 ~ 173 and resistors 181 - 183, so that equal triggering voltages (C'l and C'2~ are supplied to the optical gates of contending partners (sets) and in the generatlon of header pulses having different light intensities, as seen from Fig. 19. As illustrated, the header pulses are assumed to occur in the same time slots as in the case of Fig. 17. As in the previous embodlment, packets Pl and P3 are applied to gates 421 and 423, respectlvely, and packets P2 and P4 are applled to gates 432 and 434, respectlvely. As shown, ln Flg. 19, the header pulses of packet Pl have the highest light intensity, and those of packets P2, P3 and P4 have decreasing llght intensities in the order given. Since header pulses Plb and P2b have a higher light intensity than those of the contendlng packets, packet Pl and P2 supplied to gates 421 and 432 are the wlnners of the race to respective outlet terminals 601 and 6~2 ~
The length of a header increases with the amount of .~ , CA 020~46 1998-02-18 traffic to be carrled by the self-routing network. The header length can be conserved by multlplexlng optlcal packets upon different llght wavelengths. The wavelength rnultlplexing concept of thls lnventlon for two wavelengths ls implemented by a 2 x 4 network conflguration as shown ln Fig. 20.
Electrical packets Pl and P2 from a user statlon are successively transmltted on access llne Ll and received by llne lnterface 1'1 and packets P3 and P4 from another user statlon are successively transmitted on access line L2 and received by llne lnterface 1'2. Routlng controller 120 is coupled to the llne interfaces, determines a wavelength and a header time slot according to the lnformatlon contalned ln a packet recelved from the assoclated lnterface ln relatlon to the timing and amplitude pattern of the gate control pulses supplled from gate controller 10f, and lnstructs the lnterface to carry the packet on the determined wavelength and lnsert a header pulse lnto the determlned time slot. For purposes of illustrationl packets Pl and P2 are converted by line interface 1'1 to optlcal slgnals of wavelength Al, and packets P3 and P4 are converted by line interface 1'2 to optical slgnals of wavelengths A2 and Al, respectlvely. The outputs of interfaces 1'1 and 1'2 are connected respectively by light waveguides 701 and 7~2 to optlcal splitters 801 and 802, each having four outputs. Optical gates 9~11' 9~12~ 9~13 and 9~14 are connected respectlvely to the outputs of splltters 801r and gates g011 and 9~12 are tuned to wavelength ~1~ and gates 9~13 and 9~14 are turned to wavelength A2. Optlcal gates 9~21' 9~22' 9~23 and 9~24 are likewise connected to the '~, CA 020~46 1998-02-18 outputs of splitter 802, with gates 9~21 and 9~22 being tuned to wavelength A1 and gates 9~23 and 9~24 belng tuned to wavelength ~2. The outputs of gates 90i~(~=1,2,3,4) are connected respectlvely to the flrst lnputs of comblners 100 and the outputs of gates 9~2~ are connected to the second inputs of comblners 100~. Gate controller lOf supplies control pulses C1 and C2 to gates 9~11 and 9~i2 (1=1, 2) and control pulses C3 and C4 to gates 9~13 and 9~14.
As shown in Fig. 20A, each of the optical gates 90i~
ls preferably constructed of a narrow-band wavelength tunable optlcal element 85 and a wlde-band wavelength tunable optlcal element 86 coupled together and arranged in the path of incident light beam.
As illustrated in Fig. 21, the triggering voltages of all control pulses C1 ~ C4 have equal amplitude VH for gate excltatlon, with the trlggerlng voltages of pulses Cl and C3 having an equal time slot t1-t2 and those of pulses C2 and C4 having an equal tlme slot t2-t3. Accordlng to dlfferent wavelengths, control pulses Cl and C2 have a tralllng voltage VL1 for tuning to wavelength ~1' whlle the traillng voltage of pulses C3 and C4 is set equal to VL2 for tuning the wavelength Assume that header pulses Pla and P2a for packets Pl(ll) and P2(~1) are lnserted lnto the same time slot tl-t2 of successive headers and the header pulse P3a of packet P3( 2) ls lnserted to the time slot t1-t2 of an inltial - 18a -,1 ':~
header. The header pulse P4a and packet P4(A1) ls assumed to be inserted in the time slot t2-t3 of a subsequent header.
It is seen that header pulses Pla and P2a successively coincide with - 18b -CA 020~46 1998-02-18 control pulse C1 at gate 9~11~ so packets P1(~1) and P2(~1) are routed to 2 an outlet terminal 1 101 via combiner 1001. Header pulse P3a coincides 3 with control pulse C3 at gate 9~23, allowing packet P3(~2) to be routed to 4 outlet terminal 1103 via combiner 1003. In like manner, header pulse P4a S coincides with control pulse C2 at gate 9~22, routing packet P4(~1) to 6 outlet terminal 1102 via combiner 1002.
7 However, data collision is likely to occur between packets of the same 8 wavelength at the inputs of a combiner 100 if their header pulses are g inserted to successive time slots of the same header and partially coincide 0 with a control pulse due to timing inaccuracies. To resolve the collision 11 problem, the embodiment of Fig. 20 is modified as shown in Fig. 22 in 12 which the network is implemented in a 4 x 2 switch configuration. Optical 13 splitters 801, 802, 803 and 804, arranged to receive optical packets P1(~1), 14 P2(~2), P3(~1) and P4(~2) from waveguides 701~704, are connected 1 S respectively to wavelength tunable optical gates 911 j, 91 2j, 91 3j and 91 4j 16 (j=l, 2). The outputs of gates 91;1 and 91 i2 (i = 1, 2, 3, 4) are coupled to 17 the ith inputs of combiners 1 ~~l and 1002. Gates 91 il and 91 i2 are tuned18 to wavelength ~1 and ~2, respectively, and supplied with control pulses 19 C'1 and C'2 via resistors 191 and 192, respectively, from gate controller 21 As shown in Fig. 23A, gate control pulses C1 and C2 generated by 22 controller 109 have triggering voltages of a duration twice as long as the 23 duration of the header pulse. Assume that header pulses P1a and P2a 24 are inserted to time slot t1-t2, and header pulses P3a and P4a are assigned time slot t2-t3. It is seen that gate 911 1 is excited upon 26 coincidence between header pulse P1a and control pulse C'1, producing 27 a voltage drop across resistor 191 and allowing packet P1(~1) to be 28 routed to combiner 1001. Similarly, gate 9122 is excited upon coincidence 29 between header pulse P2a and control pulse C'2, producing a voltage CA 020~46 1998-02-18 drop across resistor 192 and allowing packet P2(~2) to be routed to 2 combiner 1002. However, due to the voltage drop across resistor 191, 3 gate 9131 is not excited and packet P3(~1) is the loser of the contention 4 with packet P1(~1). In like manner, packet P4(~2) is the loser of the s contenbon with packet P2(~2).
6 Alternatively, the triggering voltages of all control pulses are of equal 7 duration to the duration of the header pulse and the header of each 8 packet has different light intensities as shown in Fig. 23B. In this way, 9 packets P1-P4 have decreasing levels of priority ;n the order named so 10 that contention between packets P1 and P3 at gates 911 1 and 9131 is 11 resolved by giving priority to packet P1, while contenbon between 12 packets P2 and P4 is resolved by giving priority to packet P2.
13 The foregoing description shows only preferred embodiments of the 14 present invention. Various modifications are apparent to those skilled in 15 the art without departing from the scope of the present invention which is 16 only limited by the appended claims. Therefore, the embodiments 17 shown and described are only illustrative, not restrictive.
Claims (23)
1. An optical self-routing network for self-routing an optical packet having a header, comprising:
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident optical packets into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
a plurality of optical gates divided into M sets corresponding respectively to the M optical combiners, each optical gates establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, each of the M sets comprising N optical gates corresponding respectively to the N
optical splitters, the optical gates of each set being respectively connected at input ends thereof to the corresponding N optical splitters and connected at output ends thereof to the M optical combiner to which the set of the optical gates corresponds, each optical gate of each set receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica and said electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set during M successive intervals as said electrical energy.
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident optical packets into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
a plurality of optical gates divided into M sets corresponding respectively to the M optical combiners, each optical gates establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, each of the M sets comprising N optical gates corresponding respectively to the N
optical splitters, the optical gates of each set being respectively connected at input ends thereof to the corresponding N optical splitters and connected at output ends thereof to the M optical combiner to which the set of the optical gates corresponds, each optical gate of each set receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica and said electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set during M successive intervals as said electrical energy.
2. An optical self-routing network as claimed in claim 1, wherein said gate control means includes priority selection means for selecting one of optical packets incident on the optical gates of each set when contention arises among said optical packets.
3. An optical self-routing network as claimed in claim 1, wherein said gate control means supplies successively shifted gate control electrical signals of predetermined waveforms respectively to the optical gates of each set as said electrical energy so that one of the optical packet incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electric signals which are successively applied to the optical gates of said given set.
4. An optical self-routing network as claimed in claim 1, wherein the optical gates of each set are commonly assigned a unique time interval, wherein those of said optical packets which are supplied to said N optical gates of each set are successively shifted during said unique time interval, and wherein said gate control means exclusively causes one of the optical gates of each set to allow passage of an optical packet incident thereon when the header of the incident optical packet is the earliest of the headers of the optical packets incident on the optical gates of the set.
5. An optical self-routing network as claimed in claim 1, wherein said gate control means simultaneously supplies gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set as said electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the electrical signals applied to the optical gates of the given set.
6. An optical self-routing network as claimed in claim 1, wherein said gate control means simultaneously supplies gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set as said electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the light intensity of the header of the incident optical packet incident on the optical gates of the given set.
7. An optical self-routing network for self-routing an optical packet having a first and a second header, comprising:
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners combining N optical packets incident thereon into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
first and second arrays of optical gates, each optical gate establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, the first array being divided into M sets of N
optical gates each, the N optical gates of each set being connected respectively at input ends thereof to the N optical splitters, each optical gate of each set receiving one of M
replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica therethrough upon time coincidence between the first header of the incident replica and first electrical energy;
the second array being divided into M sets of N
optical gates each, the M sets of the second array corresponding respectively to the M optical combiners, and the N optical gates of each set being connected at input ends thereof respectively to the N optical gates of each set of the first array and connected at output ends thereof to the optical combiner to which the set of the optical gates corresponds, each optical gate of the second array receiving an optical packet incident from the first array and allowing passage of the incident optical packet therethrough upon time coincidence between the second header of the incident packet and second electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of the first array during M successive intervals as said first electrical energy, subsequently simultaneously supplying N gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set of the second array during M successive intervals as said second electrical energy so that one of the N optical gates of a given set of the second array exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the gate control electrical signals applied to the N optical gates of said given set.
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners combining N optical packets incident thereon into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
first and second arrays of optical gates, each optical gate establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, the first array being divided into M sets of N
optical gates each, the N optical gates of each set being connected respectively at input ends thereof to the N optical splitters, each optical gate of each set receiving one of M
replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica therethrough upon time coincidence between the first header of the incident replica and first electrical energy;
the second array being divided into M sets of N
optical gates each, the M sets of the second array corresponding respectively to the M optical combiners, and the N optical gates of each set being connected at input ends thereof respectively to the N optical gates of each set of the first array and connected at output ends thereof to the optical combiner to which the set of the optical gates corresponds, each optical gate of the second array receiving an optical packet incident from the first array and allowing passage of the incident optical packet therethrough upon time coincidence between the second header of the incident packet and second electrical energy; and gate control means for supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of the first array during M successive intervals as said first electrical energy, subsequently simultaneously supplying N gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set of the second array during M successive intervals as said second electrical energy so that one of the N optical gates of a given set of the second array exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the gate control electrical signals applied to the N optical gates of said given set.
8. An optical self-routing network for self-routing an optical packet having a first and a second header comprising:
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident N optical packets into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
first and second arrays of optical gates, each optical gate establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, and each of the array being divided into M sets of N optical gates each;
the N optical gates of each set of the first array being connected respectively at input ends thereof to the N
optical splitters, each optical gate of each set receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica therethrough upon time coincidence between the first header of the incident replica and first electrical energy;
the M sets of the second array corresponding respectively to the M optical combiners, and the N optical gates of each set of the second arrays being respectively connected at input ends thereof to the N optical gates of each set of the first array and connected at output ends thereof to the optical combiner to which the set of the optical gates corresponds, each optical gate of the second array receiving an optical packet incident from the first array and allowing passage of the incident optical packet therethrough upon time coincidence between the second header of the incident packet and second electrical energy, wherein the optical gates of each array are assigned a unique time interval and the first headers of optical packets incident on the optical gates of the first array occur at different points within said unique time interval and the second headers of optical packets incident on the optical gates of the second array have different light intensities;
and gate control means for supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of said first array during M successive intervals as said first electrical energy, subsequently supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of said second array during M successive intervals as said second electrical energy so that one of the N optical gates of a given set of the second array exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers of the optical packets incident on the N optical gates of said given set.
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M optical combiners associated respectively with M
outlet terminals of the network, each of the optical combiners receiving N optical packets incident thereon and combining the incident N optical packets into a combined optical signal and coupling the combined optical signal to the associated outlet terminal;
first and second arrays of optical gates, each optical gate establishing a path between input and output ends thereof upon time coincidence between light energy and electrical energy applied thereto, and each of the array being divided into M sets of N optical gates each;
the N optical gates of each set of the first array being connected respectively at input ends thereof to the N
optical splitters, each optical gate of each set receiving one of M replicas of an optical packet incident from the corresponding optical splitter and allowing passage of the incident replica therethrough upon time coincidence between the first header of the incident replica and first electrical energy;
the M sets of the second array corresponding respectively to the M optical combiners, and the N optical gates of each set of the second arrays being respectively connected at input ends thereof to the N optical gates of each set of the first array and connected at output ends thereof to the optical combiner to which the set of the optical gates corresponds, each optical gate of the second array receiving an optical packet incident from the first array and allowing passage of the incident optical packet therethrough upon time coincidence between the second header of the incident packet and second electrical energy, wherein the optical gates of each array are assigned a unique time interval and the first headers of optical packets incident on the optical gates of the first array occur at different points within said unique time interval and the second headers of optical packets incident on the optical gates of the second array have different light intensities;
and gate control means for supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of said first array during M successive intervals as said first electrical energy, subsequently supplying a gate control electrical signal of a predetermined waveform to each set of optical gates of said second array during M successive intervals as said second electrical energy so that one of the N optical gates of a given set of the second array exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers of the optical packets incident on the N optical gates of said given set.
9. An optical self-routing network for self-routing an optical packet having a first and a second header, comprising:
a plurality of pairs of first-stage optical gates, each optical gate allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
a plurality of first optical combiners associated respectively with said pairs of first-stage optical gates, each of the optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
a plurality of pairs of second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto;
means for receiving optical packets incident from the second-stage optical gates into one or more optical signals and combining the incident optical packets; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of said given pair, and subsequently simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the second-stage optical gates as said second electrical energy so that one of the second-stage optical gates exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the second-stage optical gates.
a plurality of pairs of first-stage optical gates, each optical gate allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
a plurality of first optical combiners associated respectively with said pairs of first-stage optical gates, each of the optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
a plurality of pairs of second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto;
means for receiving optical packets incident from the second-stage optical gates into one or more optical signals and combining the incident optical packets; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of said given pair, and subsequently simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the second-stage optical gates as said second electrical energy so that one of the second-stage optical gates exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the second-stage optical gates.
10. An optical self-routing network for self-routing an optical packet having a first and a second header, comprising:
M self-routing circuits, each of the circuits comprising:
N first-stage optical gates, each of the first-stage optical gates allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
N/2 first-stage optical combiners associated respectively with a pair of said first-stage optical gates, each of the first-stage optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
N/2 second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto; and N/4 second-stage optical combiners associated respectively with a pair of said second-stage gates for receiving optical packets incident from the second-stage optical gates of the associated pair and combining the incident optical packets;
N optical splitters associated respectively with N
inlet terminals, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet and coupling each replica of the optical packet to a respective one of the N first-stage optical gates of one of said M self-routing circuits; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of said given pair, and subsequently simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the second-stage optical gates of each pair as said second electrical energy so that one of the second-stage optical gates of a given pair exclusively allows passage of an optical packet applied thereto is the highest of the signals applied to the second stage optical gates of said given pair.
M self-routing circuits, each of the circuits comprising:
N first-stage optical gates, each of the first-stage optical gates allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
N/2 first-stage optical combiners associated respectively with a pair of said first-stage optical gates, each of the first-stage optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
N/2 second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto; and N/4 second-stage optical combiners associated respectively with a pair of said second-stage gates for receiving optical packets incident from the second-stage optical gates of the associated pair and combining the incident optical packets;
N optical splitters associated respectively with N
inlet terminals, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet and coupling each replica of the optical packet to a respective one of the N first-stage optical gates of one of said M self-routing circuits; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of said given pair, and subsequently simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the second-stage optical gates of each pair as said second electrical energy so that one of the second-stage optical gates of a given pair exclusively allows passage of an optical packet applied thereto is the highest of the signals applied to the second stage optical gates of said given pair.
11. An optical self-routing network for self-routing an optical packet having a first and a second header, comprising:
a plurality of pairs of first-stage optical gates, each optical gate allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
a plurality of second-stage optical gates associated with incident from the first-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto;
means for receiving optical packets incident from the second-stage optical gates and combining the incident optical packets; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the first-stage optical gates as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows air passage of an optical packet incident thereon when the light intensity of the first header of the incident optical packet is the highest of the first headers incident on the optical gates of said given pair, and subsequently simultaneously supplying a gate control electrical signal of a predetermined waveform to the second-stage optical gates as said second electrical energy so that one of the second-stage optical gates exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers incident on the second-stage optical gates.
a plurality of pairs of first-stage optical gates, each optical gate allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
a plurality of second-stage optical gates associated with incident from the first-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto;
means for receiving optical packets incident from the second-stage optical gates and combining the incident optical packets; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the first-stage optical gates as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows air passage of an optical packet incident thereon when the light intensity of the first header of the incident optical packet is the highest of the first headers incident on the optical gates of said given pair, and subsequently simultaneously supplying a gate control electrical signal of a predetermined waveform to the second-stage optical gates as said second electrical energy so that one of the second-stage optical gates exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers incident on the second-stage optical gates.
12. An optical self-routing network self-routing an optical packet having a first and a second header, comprising:
M self-routing circuits, each of the circuits comprising:
N first-stage optical gates, each of the first-stage optical gates allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
N/2 first-stage optical combiners associated respectively with a pair of said first-stage optical gates, each of the first-stage optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
N/2 second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto; and N/4 second-stage optical combiners associated respectively with a pair of second-stage optical gates for receiving optical packets incident from the second-stage optical gates of the associated pair and combining the incident optical packets;
N optical splitters associated respectively with N
inlet terminals, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet and coupling each replica of the optical packet to a respective one of the N first-stage optical gates of one of said M self-routing circuits; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the light intensity of the first header of the incident optical packet is the highest of the first headers incident on the optical gates of said given pair, and subsequently simultaneously supplying a gate control electrical signal of a predetermined waveform to the second-stage optical gates of each pair as said second electrical energy so that one of the second-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers incident on the second-stage optical gates of said given pair.
M self-routing circuits, each of the circuits comprising:
N first-stage optical gates, each of the first-stage optical gates allowing passage of an optical packet incident thereon when the first header of said incident optical packet timely coincides with first electrical energy applied thereto;
N/2 first-stage optical combiners associated respectively with a pair of said first-stage optical gates, each of the first-stage optical combiners receiving optical packets incident from the first-stage optical gates of the associated pair and combining the incident optical packets;
N/2 second-stage optical gates associated respectively with said optical combiners, each of the second-stage optical gates receiving an optical packet incident thereon from the associated combiner and allowing passage of the incident optical packet when the second header of said incident optical packet timely coincides with second electrical energy applied thereto; and N/4 second-stage optical combiners associated respectively with a pair of second-stage optical gates for receiving optical packets incident from the second-stage optical gates of the associated pair and combining the incident optical packets;
N optical splitters associated respectively with N
inlet terminals, each of the splitters splitting an optical packet from the associated inlet terminal into M replicas of the optical packet and coupling each replica of the optical packet to a respective one of the N first-stage optical gates of one of said M self-routing circuits; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the first-stage optical gates of each pair as said first electrical energy so that one of the first-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the light intensity of the first header of the incident optical packet is the highest of the first headers incident on the optical gates of said given pair, and subsequently simultaneously supplying a gate control electrical signal of a predetermined waveform to the second-stage optical gates of each pair as said second electrical energy so that one of the second-stage optical gates of a given pair exclusively allows passage of an optical packet incident thereon when the light intensity of the second header of the incident optical packet is the highest of the second headers incident on the second-stage optical gates of said given pair.
13. An optical self-routing network for self-routing an optical packet having a header, comprising:
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M sets of optical gates, each optical gate receiving an optical packet incident thereon and allowing passage of the incident optical packet when the header of said incident optical packet timely coincides with electrical energy applied thereto;
M optical combiners associated respectively with the M sets of optical gates, each optical combiner receiving optical packet incident from the optical gates of the associated set and combining the incident optical packets into a combined optical signal and coupling the combined optical signal to an outlet terminal of the network; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set as electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of the given set.
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M sets of optical gates, each optical gate receiving an optical packet incident thereon and allowing passage of the incident optical packet when the header of said incident optical packet timely coincides with electrical energy applied thereto;
M optical combiners associated respectively with the M sets of optical gates, each optical combiner receiving optical packet incident from the optical gates of the associated set and combining the incident optical packets into a combined optical signal and coupling the combined optical signal to an outlet terminal of the network; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates of each set as electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the signals applied to the optical gates of the given set.
14. An optical network for self-routing an optical packet having a header, comprising:
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M sets of optical gates, each optical gate receiving an optical packet incident thereon and allowing passage of the incident optical packet when the header of said incident optical packet timely coincides with electrical energy applied thereto;
M optical combiners associated respectively with the M sets of optical gates, each optical combiner receiving optical packets incident from the optical gates of the associated set and combining the incident optical packets into a combined optical signal and coupling the combined optical signals to an outlet terminal of the network; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set as said electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the light intensity of the header of the incident optical packet is the highest of the headers incident on the optical gates of said given set.
N optical splitters associated respectively with N
inlet terminals of the network, each of the splitters receiving an optical packet incident from the associated inlet terminal and splitting the incident optical packet into M
replicas of the optical packet;
M sets of optical gates, each optical gate receiving an optical packet incident thereon and allowing passage of the incident optical packet when the header of said incident optical packet timely coincides with electrical energy applied thereto;
M optical combiners associated respectively with the M sets of optical gates, each optical combiner receiving optical packets incident from the optical gates of the associated set and combining the incident optical packets into a combined optical signal and coupling the combined optical signals to an outlet terminal of the network; and gate control means for simultaneously supplying a gate control electrical signal of a predetermined waveform to the optical gates of each set as said electrical energy so that one of the optical gates of a given set exclusively allows passage of an optical packet incident thereon when the light intensity of the header of the incident optical packet is the highest of the headers incident on the optical gates of said given set.
15. An optical self-routing network as claimed in claim 1, wherein the optical signals applied to said self-routing network are respectively carried on a plurality of wavelengths, and wherein each of said optical gates is selectively transmissive of an optical signal of one of said wavelengths.
16. An optical self-routing network as claimed in claim 15, wherein each of said optical gates comprises a narrow-band optical gate element for passing therethrough an optical packet incident from one side of the optical gate, and a wide-band optical gate element connected to said narrow-band optical gate for passing an optical packet incident from the narrow-band optical gate element to the other side of the optical gate.
17. An optical self-routing network as claimed in claim 4, wherein the optical packets applied to said self-routing network are carried on a plurality of wavelengths, and wherein each of said optical gates is selectively transmissive of an optical packet of one of said wavelengths.
18. An optical self-routing network as claimed in claim 6, wherein the optical packets applied to said self-routing network are carried on a plurality of wavelengths, and wherein each of said optical gates is selectively transmissive of an optical packet of one of said wavelengths.
19. An optical self-routing network as claimed in claim 1, further comprising means disposed between said N optical splitters and said NXM optical gates for passing optical packets from said splitters to said NXM optical gates and directing optical packets returning from said optical gates to said M optical combiners.
20. An optical priority selection circuit for a self-routing network for routing an optical packet having a header, comprising:
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for supplying successively shifted gate control electrical signals of predetermined waveforms respectively to the optical gates as said electric energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electrical signals which are successively applied to the optical gates.
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for supplying successively shifted gate control electrical signals of predetermined waveforms respectively to the optical gates as said electric energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the gate control electrical signal applied thereto is the earliest of the gate control electrical signals which are successively applied to the optical gates.
21. An optical priority selection circuit for a self-routing network for routing an optical packet having a header, comprising:
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto, and wherein the optical gates of each set are commonly assigned a unique time interval, and optical packets supplied to said optical gates are successively shifted during said unique time interval; and gate control means for supplying a gate control electrical signal to said optical gates as said electrical energy so that one of the optical gates allows passage of an optical packet incident thereon when the incident optical packet is the earliest of the packets incident on the optical gates.
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto, and wherein the optical gates of each set are commonly assigned a unique time interval, and optical packets supplied to said optical gates are successively shifted during said unique time interval; and gate control means for supplying a gate control electrical signal to said optical gates as said electrical energy so that one of the optical gates allows passage of an optical packet incident thereon when the incident optical packet is the earliest of the packets incident on the optical gates.
22. An optical priority selection circuit for self-routing network for routing an optical packet having a header, comprising:
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates as said electrical energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the electrical signals applied to the optical gates.
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates as said electrical energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the amplitude of the gate control electrical signal applied thereto is the highest of the electrical signals applied to the optical gates.
23. An optical priority selection circuit for a self-routing network for routing an optical packet having a header, comprising:
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates as said electrical energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the light intensity of the header of the incident optical packet is the highest of the headers of the optical packets incident on the optical gates.
a plurality of optical gates, each of the optical gates receiving said optical packet and allowing passage of the received optical packet when the header of the packet timely coincides with electrical energy applied thereto; and gate control means for simultaneously supplying gate control electrical signals of predetermined amplitudes respectively to the optical gates as said electrical energy so that one of the optical gates exclusively allows passage of an optical packet incident thereon when the light intensity of the header of the incident optical packet is the highest of the headers of the optical packets incident on the optical gates.
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-307649 | 1990-11-14 | ||
| JP2307649A JP2827501B2 (en) | 1990-11-14 | 1990-11-14 | Optical self-routing circuit |
| JP3597091A JP2850550B2 (en) | 1991-03-01 | 1991-03-01 | Optical self-routing circuit |
| JP3-35970 | 1991-03-01 | ||
| JP8588091A JP2855878B2 (en) | 1991-03-27 | 1991-03-27 | Optical self-routing circuit |
| JP3-85880 | 1991-03-27 | ||
| JP17823491A JP2748726B2 (en) | 1991-07-18 | 1991-07-18 | Optical self-routing circuit |
| JP3-178234 | 1991-07-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2055546A1 CA2055546A1 (en) | 1992-05-15 |
| CA2055546C true CA2055546C (en) | 1999-02-02 |
Family
ID=27460184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002055546A Expired - Fee Related CA2055546C (en) | 1990-11-14 | 1991-11-14 | Self-routing network using optical gate array driven by control voltages coincidental with packet header pulses |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5341234A (en) |
| EP (1) | EP0486023B1 (en) |
| CA (1) | CA2055546C (en) |
| DE (1) | DE69127423T2 (en) |
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| AU712810B2 (en) * | 1995-07-28 | 1999-11-18 | British Telecommunications Public Limited Company | Packet routing |
| FR2754352B1 (en) * | 1996-10-07 | 1998-11-13 | Alsthom Cge Alcatel | OPTICAL SWITCH |
| US6271949B1 (en) * | 1996-12-18 | 2001-08-07 | Nec Corporation | Optical communication system using wavelength-division multiplexed light |
| US5959767A (en) * | 1996-12-31 | 1999-09-28 | Lucent Technologies | Loss-less optical cross-connect |
| JP3481442B2 (en) | 1997-12-22 | 2003-12-22 | 日本電気株式会社 | Optical network |
| US6128113A (en) * | 1998-03-04 | 2000-10-03 | Dynamics Research Corporation | Transparent optical communications switch |
| JPH11275614A (en) * | 1998-03-26 | 1999-10-08 | Nec Corp | Photo switching device |
| KR100295097B1 (en) | 1998-08-22 | 2001-08-07 | 오길록 | Optical gate based optical spaced-deivision switch |
| US6782210B1 (en) * | 1999-08-25 | 2004-08-24 | Nippon Telegraph And Telephone Corporation | Optical packet routing network system based on optical label switching technique |
| JP4290320B2 (en) * | 2000-09-28 | 2009-07-01 | 富士通株式会社 | Routing device |
| US20020122225A1 (en) * | 2001-03-01 | 2002-09-05 | Yigal Rappaport | Multiport wavelength division multiplex network element |
| US6501886B1 (en) * | 2001-07-30 | 2002-12-31 | Agilent Technologies, Inc. | Compact optical splitter and combiner |
| US7161936B1 (en) * | 2001-12-28 | 2007-01-09 | Cisco Technology, Inc. | Method and system for distributing data communications utilizing a crossbar switch |
| US9729946B2 (en) * | 2009-04-03 | 2017-08-08 | Infinera Corporation | High-capacity switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB945373A (en) * | 1960-09-02 | 1963-12-23 | Ass Elect Ind | Improvements relating to static switching arrangements of the cross-point type |
| GB945374A (en) * | 1960-11-04 | 1963-12-23 | Ass Elect Ind | Improvements relating to switching systems employing co-ordinate switching arrangements of the cross-point type |
| US3141067A (en) * | 1960-11-17 | 1964-07-14 | Lester M Spandorfer | Automatic electronic communication switching exchange |
| US3223978A (en) * | 1962-06-08 | 1965-12-14 | Radiation Inc | End marking switch matrix utilizing negative impedance crosspoints |
| US3452157A (en) * | 1966-02-01 | 1969-06-24 | Itt | Current controlled,self-seeking telephone switching system |
| US4731878A (en) * | 1985-11-29 | 1988-03-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Self-routing switch node combining electronic and photonic switching |
| US4787692A (en) * | 1987-03-13 | 1988-11-29 | American Telephone And Telegraph Company At&T Bell Laboratories | Electro optical switch architectures |
| DE3856531T2 (en) * | 1987-09-30 | 2003-01-16 | Nec Corp., Tokio/Tokyo | Time and wavelength division switching system |
| JPH0834479B2 (en) * | 1987-10-22 | 1996-03-29 | 国際電信電話株式会社 | Optical packet switching system |
| IT1219054B (en) * | 1988-02-29 | 1990-04-24 | Cselt Centro Studi Lab Telecom | NODE FOR FAST SWITCHING NETWORK OF PACKAGE IN OPTICAL ELECTRIC TECHNOLOGY |
| JPH025663A (en) * | 1988-06-23 | 1990-01-10 | Nec Corp | Optical packet exchange |
| US5023864A (en) * | 1989-05-08 | 1991-06-11 | At&T Bell Laboratories | Crossover network utilizing two-dimensional arrays of nodes |
| JP2692316B2 (en) * | 1989-11-20 | 1997-12-17 | 日本電気株式会社 | Wavelength division optical switch |
| US5181134A (en) * | 1991-03-15 | 1993-01-19 | At&T Bell Laboratories | Photonic cross-connect switch |
-
1991
- 1991-11-14 CA CA002055546A patent/CA2055546C/en not_active Expired - Fee Related
- 1991-11-14 US US07/792,191 patent/US5341234A/en not_active Expired - Fee Related
- 1991-11-14 DE DE69127423T patent/DE69127423T2/en not_active Expired - Fee Related
- 1991-11-14 EP EP91119452A patent/EP0486023B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0486023A2 (en) | 1992-05-20 |
| DE69127423D1 (en) | 1997-10-02 |
| DE69127423T2 (en) | 1998-02-19 |
| EP0486023B1 (en) | 1997-08-27 |
| CA2055546A1 (en) | 1992-05-15 |
| US5341234A (en) | 1994-08-23 |
| EP0486023A3 (en) | 1993-05-12 |
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