CA2052179C - Image display system - Google Patents
Image display systemInfo
- Publication number
- CA2052179C CA2052179C CA 2052179 CA2052179A CA2052179C CA 2052179 C CA2052179 C CA 2052179C CA 2052179 CA2052179 CA 2052179 CA 2052179 A CA2052179 A CA 2052179A CA 2052179 C CA2052179 C CA 2052179C
- Authority
- CA
- Canada
- Prior art keywords
- address
- display
- horizontal
- vertical
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 claims abstract description 80
- 238000006243 chemical reaction Methods 0.000 claims abstract description 55
- 230000004044 response Effects 0.000 claims description 9
- 244000003363 Allium ursinum Species 0.000 description 34
- 125000001874 trioxidanyl group Chemical group [*]OOO[H] 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/391—Resolution modifying circuits, e.g. variable screen formats
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
An image display system capable of moving, enlarging, reducing or otherwise manipulating an image being displayed on a screen. Display addresses are divided in the horizontal and vertical directions. A horizontal and a vertical display address conversion RAM are each connected to respective one of display address buses so as to convert the display addresses in the horizontal or vertical direction. An additional bit representative of an image display timing may be assigned to each of conversion table data stored in horizontal and vertical address conversion RAMs which are connected to particular one of a plurality of video memories.
Description
IMAGE DISPLAY SYSTEM
BACKGROUND OF THE IN~rENTION
The present invention relates to an image display system and, more particularly, to an image display system capable of moving, enlarging, reducing or otherwise manipulating an image S being displayed on a display.
An conventional image display system of the type described has a display clock generator, a display address counter, an address bus switch, a display address conversion RAM lRandom Access Memory), a memory address switch, a 10 video memory, a digital-to-analog (r~A) converter, and a microprocessor. The display clock generator generates a display ciock ha~ing a predetermined period. When data is to be read out of the video memory, the display address counter outputs a display address by counting the display clock in response to a 15 command from the microprocessor. The display address is applied to the address input of the conversion RAM via the address bus switch. The conversion RAM converts the input display address on the basis of data stored therein and feeds out the converted display address to a data line. The converted 20 display address is delivered to the address terminal of the video memory with the result that image data designated by the display address is read out. The DA converter converts the image data to a video signal.
To change the position or the size of an image being 5 displayed, the microprocessor is used to switch the display address switch and memory address switch such that the address bus and data bus of the conversion RAM are connected to those of the microprocessor. After the microprocessor has changed the data stored in the RAM, the switches are restored to their 10 original states so as to display the manipulated image. This kind of technology for reading data out of a video memory by address conversion is disclosed in, for example, "A Raster Assembly Processor (RAP) for Integrated HDTV Display of Video data and Image windows," IEEE 1987, pp. 731-739.
The problem with the conventional system is that the conversion RAM has to convert all of the display addresses sequentially generated by the display address couriter znd, therefore, needs an extremely great capacity. For example, when the display has a resolution of 640 dots (horizontal) x 400 20 lines (vertical), a conversion RAM whose capacity is as great as 4, 6 0 8, 0 0 0 bits is needed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to 2 5 provide an image display system which noticeably reduces the required capacity an address conversion RAM.
- ~ It is another obiect of the present invention to provide a generally improved image display system.
An image display system of the present invention 5 comprises a horizontal display address counter for outputting a horizontal display address in response to a display clock, a vertical display address counter for outputting a vertical display address in response to the display clock, a horizontal display address conversion memory having an address input to which the 10 horizontal display address is connected, a vertical display address conversion memory having an address input to which the vertical display address is connected, a video memory having address inputs to which a data bus from the horizontal display address conversion memory and a data bus from the vertical 15 display address conversion memory are connected, the video memory outputting video data on the basis of the input addresses, and a rewriting circuit for rewriting data stored in the horizontal and vertical display address conversion memories.
BRIEF DESCRIPTION OF T~IE DRAWINGS
The above and other obiects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
2 5 FIG. 1 is a bloclc diagram schematically showing a 205~ 1 79 conventional image display system;
FIG. 2 is a block diagram schematically showing an image display system embodying the present invention;
FIG 3 is a memory map representative of a video 5 memory included in the embodiment;
FIGS. 4A and 4B are memorY maps representative of, respectively, a horizontal and a vertical display address conversion RA M also included in the embodiment;
FIG. 5 is a memory map indicative of a specific condition 10 wherein data stored in the vertical display address conversion R A M is manipulated;
FIG 6 shows table data to be written to the horizontal and vertical conversion RA Ms for doubling the size of an image;
FIG 7 shows a relation between the video memory and a 15 display in the condition shown in FIG. 6;
FIG. 8 is a block diagram schematically showing an alternative e~bodiment of the present invention; and FIGS. 9A and ~B show additional bis and a specific condition of a screen.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
To better understand the present invention, a brief reference will be made to a prior art image display system, shown in FIG 1. As shown, the convenional image display system, generally 10 0, has a display clock generator 101, a display address counter 10 2, an address bus switch 10 3, a display address conversion RAM 104, a memory address switch 10 5, a video memory 10 6, a DA converter 10 7, and a microprocessor 108. The display clock generator 101 generates a display clock having a predetermined period. When data is to be read out of the video memory 10 6, the microprocessor 10 8 causes the display address counter 102 to count the display clock to thereby generate a display address. The display address is applied to the address terminal of the RAM 104 via the address bus switch 103. In response, the RAM 104 converts the display address on the basis of data stored therein and feeds the resulting converted address to the address terminal of the v}deo memory 10 6 via the memory address switch 10 5 . On receiving the display address, the video memory 106 outputs video data.
The DA converter 107 converts the video data fed thereto from the video memory 106 to a video signa;. To change the position or the size of an image being displayed, the microprocessor 108 is used to switch the display address switch 10 3 and memory address switch 10 5 such that the address bus and data bus of the RAM 104 are connected to those of the microprocessor 108.
After the microprocessor 108 has changed the data stored in the RAM 104, the switches 103 and 105 are restored to their original states so as to display an image.
- The conventional system 10 0 has a draback that the 5 address conversion RAM has to convert all of the display addresses sequentially generated by the display address counter 102 and, therefore, needs an extremely great capacity, as discussed earlier.
Referring to FIG. 2, an image display system embodying 10 the present invention is shown and generally designated by the reference numeral 200. As shown, the system 200 has a disp;ay clock generator 201 for generating a display clock. A horizontal display address counter 202 counts the display clock while sequentially outputting horizontal display addresses. A vertical 15 display address counter 203 is incremented every time it receives m clock pulses from the horizontal clock generator 201 (m being the number of addresses in the horizontal direction), while outputting the resulting count as a vertical display address. A
horizontal address bus switch 20 4 selects either one of an address bus extending from the horizontal display address counter 202 and an address bus extending from a microprocessor 212 which will be described. A vertical address bus switch 20 5 selects either one of an address bus extending from the vertical address counter 203 and the address bus 2 5 extending from the microprocessor 212. A horizontal display address conversion RAM 206 has an address input to which the horizontal display address is connected. A vertical display address conversion RAM 207 has an address input to which the vertical display address is connected. The reference numeral 5 210 designates a video memory. A horizontal memory address switch 208 is connected to the horizontal display address conversion RAM 206 for selecting either one of a data bus terminating at the video memory 210 and a data bus terminating - at the microprocessor 212. A vertical memory address switch 10 209 selects either one of a data bus terminating at the video memory 210 and the data bus terminating at the microprocessor 212. A DA converter 211 converts video data read out of the video memory 210 to a video signal and feeds it to a conventional display 214. The microprocessor 212 controls the states of the switches 204, 205, 208 and 209 and rewrites the data stored in the RAMs 206 and 207. The reference numeral 213 designates an image processing circuit.
The image processing circuit 213 sequentially writes the first to n-th lines of video data in the video memory 210 pixel by 20 pixel. Specifically, the circuit 213 processes TV (Television) video data in a predetermined manner to generate video data pixel by pixel and generates horizontal and vertical addresses representative of particular horizontal and vertical writing positions of the video memory 210 at the same time, thereby 25 writing the image data in such addresses. The display 214 displays the image data stored in the video memory 10 line by line in synchronism with a horizontal scanning signal. The switches 204, 205, 20 ~ and 209 play the role of rewriting means in combination.
In the embodiment, the resolution is assumed to be 640 dots in the horizontal direction of the display 214 and 400 lines in the vertical direction. Hence, the horizontal and vertical display addresses require 10 bits and 9 bits, respectively.
FIG. 3 is a memory map representative of the video memory 210. In the figure, image data A on the second line is designated by an address "0000000001000000001". FIGS. 4A
and 4B are memory maps representative of the RAMs 206 and 207, respectively.
In operation, the display clock generator 201 feeds a display dot clock to the horizontal display address counter 202 and vertical display address counter 203. The horizontal display address counter 2 û 2 starts counting the input clock In response to a start signal a from the microprocessor 212. The counter 202 repetitively counts the display addresses 0-639 of dots in the horizontal direction in synchronism with the horizontal scanning period of the display 14, while delivering the count to the 10-bit horizontal display address bus. The horizontal address bus switch 204 has a first input connected to the display address bus from the address counter 202 and a second input connected to the address bus from the microprocessor 212. The switch 204, 20~ ~ 79 g therefore, selects either one of the address buses connected to the first and second inputs thereof and connects it to the address terminal of the horizontal address conversion RAM 206.
During an image display period, the horizontal address 5 bus switch 204 is connected to the horizontal address counter 2 0 2 . In this condition, display addresses synchronous to the clock signal from the display clock generator 2 01 are sequentially inputted to the horizontal address conversion RAM
2 0 6, whereby data are sequentially read out of the RAM 2 0 6 .
The data from the RAM 206 has a 10-bit bus width and is applied to the horizontal memory address switch 208. This switch 208 delivers the input 1 0-bit data to the lower 1 0-bit data bus of the video memory 210. The video data in the horizontal direction are sequentially read out as designated by 15 the addresses which are fed to the lower address of the video memory 210.
Regarding the display in the vertical direction, the vertical address counter 203 counts the addresses 0-399 of the display lines while delivering the count to the 9-bit vertical 2 0 display address bus. During an image display period, the vertical display address from the address counter 203 is applied to the vertical address conversion RAM 2 0 7 via the vertical address bus switch 205. As a result, 9-bit data is read out of the RAM 207 as designated by the input address and then routed 2 5 through the switch 2 0 9 to the upper address bus of the video ~0.~79 --1 o--- memory.
The above-stated display in the horizontal and vertical directions is effected according to the sc~nning on the screen of the display 214. Consequently, video data are sequentially read 5 out of the video memory 10, converted to an analog video data by the DA converter 211, and then fed to the display 214.
The display addresses inputted to the video memory 10 are the data having been read out of the horizontal and vertical address conversion RAMs 206 and 207. Therefore, the 10 horizontal and vertical addresses in the video memory 210 can be changed if the data in the RAMs 206 and 207 are rewritten.
This allows an image being displayed to be moved in the horizontal and vertical directions, enlarged, reduced, or otherwise modified. It should be noted that the system 200 can 15 move an image only on the column or line basis of the video memory 210.
To rewrite the data stored in the conversion RAMs 206 and 207, the microprocessor 212 causes the horizontal and vertical address bus switches 204 and 205 to connect the address 20 bus of the microprocessor 212 to the address buses of the RAMs 206 and 207. Also, the microprocessor 212 causes the horizontal and vertical memory address switches 208 and 209 to connect the data bus of the microprocessor 212 to the data buses of the RAMs 206 and 207. In this condition, the microprocessor 212 rewrites the data stored in the RAMs 206 and 207.
Thereafter, the microprocessor 212 again connects the switches 204 and 205 to the address counters 202 and 203 and the switches 208 and 209 to the address buses of the video memory 210. In the illustrative embodiment, the switches 204, 205, 208 and 209 may each be implemented as a switch or a gate, as desired.
FIG. 5 shows a specific condition wherein the the second and 640-th line of the vertical address conversion RAM 207 are replaced with each other. In this case, all that is required is to substitute the data at the addresses 000000001 and 101111111 of the RAM 207 for each other. The data stored in the other RAM 206 remain in the same condition shown in FIG. 4A.
As shown in FIG 6, when it is desired to double the size of an image, table data are written to the horizontal conversion RAM 206, as follows:
(address: data~ = (O O OH: O O G H~ , (O O 1 H: O O O H) , (002H: 001H), (003H: OOlH), . . . , (27 FH : 13 FH) As a result, the display addresses in the horizontal direction are sequentially incremented by 1 (one) for 2 dots, as shown in FIG. 7. The image is, therefore, doubled in size in the horizontal direction. Likewise, table data are written to the vertical address conversion RAM 207, as follows:
(address: data) = (O O O H: O O O H) , (O O l H: O O O H) , (002H: OOlH), (003H: OOlH), . . ., (18FH: OC7H) 5 Then, as shown in FIG. 7, the display addresses in the vertical direction are sequentially incremented by 1 for 2 lines, doubling the image size in the vertical direction.
To halve the image size, table data are written to the - RAMS 207 and 207, as shown below:
RAM 206: (address : data) = (OOOH : OOOH), (OOlH: 002H), (002H: 004H), (003H: 006H), . . . , (27FH: 4FEH) RAM 207: (address : data) = (OOOH : OOOH), (001H : 002H), (002H: 004H), (003H: 006H), ... (18FH: 31EH) In this case, the horizontal and vertical display addresses are sequentially incremented by 2 for one 1 dot each. As a result, the horizontal and vertical addresses and, therefore, the image 25 size is halved.
By the procedure described above, an image being displayed on the display 214 can be moved in the horizontal and vertical directions, enlarged, reduced, or otherwise manipulated, as desired.
The display 214 has a resolution which is 640 dots in the horizontal direction and 400 lines in the vertical direction (see FIG. 7), as stated earlier. The horizontal and vertical display addresses, therefore, need 10 bits and 9 bits, respectively. It follows that the RAMs 206 and 207 need respectively only the capacity of 640 x 10 = 6,400 bits and the capacity of 400 x 9 = 3,600 bits, i. e., the total capacity is only 10,000 bits which is far smaller than the conventional capacity which is 4,608,000 bits.
As stated above, the image display system 200 divides display addresses in the horizontal and vertical directions, connects a horizontal and a vertical address conversion RAM to display address buses, and converts the display addresses i~n the horizontal and vertical directions. The system 200, therefore, can shift, enlarge, reduce or otherwise modify an image while noticeably reducing the required capacity of the RAMSs.
The system 200 described above changes the display addresses by use of a single video memory to thereby change a particular condition of a single image such as the position or the size. Hence, the system 200 is not practicable with two or more images.
20~2 1 79 Referring to FIG. 8, an alternative embodiment of the present invention will be described which is capable of handling two different images at the same time. As shown, the image display system or multi-display system, generally 800, has a display clock generator 801. A horizontal and a vertical address counter 802 and 803 each receives the display clock and outputs a horizontal or vertical display address. A first and a second horizontal display address conversion RAM 806 and 814 each has an address input to which the horizontal display address is connected. A first and a second vertical display conversion RAM
807 and 815 each has an address input to which the vertical display address is connected. A first and a second video memory 810 and 818 are connected at the lower side of the address inputs thereof to the data buses of the horizontal address conversion RAMs 806 and 814, respectively, and at the upper side of the same to the data buses of the vertical address converâioil RAMs 807 and 815, respectively. These video memories 810 and 818 deliver video data to the associated data buses. A controller 820 rewrites data stored in the RAMs 806, 807, 814 and 815, as needed. A first and a second address switch 804 and 812 are respectively connected to the RAMs 906 and 814, and each selects either one of the address bus extending from the horizontal display address counter 802 and the address bus extending from the controller 820. A first and a second address bus switch 805 and 813 are respectively `- 2052 1 79 connected to the RAMs 807 and 815, and each selects either one of the address bus extending from the controller 820 and the address bus extending from the vertical display address counter 803. A first and a second data bus switch 808 and 816 are respectively connected to the RAMs 806 and 814, and each selects either one of the data bus to the video memory 810 or 818 and the data bus to the controller 820. A first and a second data bus switch 809 and 817 are respectively connected to the RAMs 807 and 815, and each selects either one of the data bus to the video memory 810 or 818 and the data bus to the controller 820. An AND gate 821 produces AND of additional bits provided in conversion table data of the RAMs 806 and 807, as will be described. A second AND gate 822 ANDs the additional bits provided in the conversion table data of the RAMS 814 and 815. A first and a second analog switch 811 and 819 are turned on and off by the AND gates 821 and 822, respectively. The additional bits are added to the uppermost bits of the horizonta;
and vertical display addresses. Therefore, the inputs of the AND
gates 821 and 822 are connected to the uppermost bits of the address buses.
In operation, the horizontal and vertical address counters 820 and 808 each generates a horizontal or vertical display address in response to the display clock from the clock generator 801. The horizontal and vertical display addresses are respectively routed through the first horizontal and vertical address bus switches 804 and 805 and the second horizontal and vertical address bus switches 812 and 813 to the fist horizontal and vertical address conversion RAMs 806 and 807 and the second horizontal and vertical address conversion RAMs 814 and 815. In response, the RAMs 806 and 807 and the RAMs 814 and 815 convert the input display addresses on the basis of data stored therein. The resulting outputs of the RAMs 806, 807, 814 and 815 are respectively routed through the associated data bus switches 808, 809, 816 and 817 to the lower and upper addresses of the first video memory 810 and the lower and upper addresses of the second video memory 818. As a result, video data are fed from the video memories 810 and 818 to a display, not shown.
Assume that the resolution of the display is 640 dots ~horizontal) x 400 lines (vertical) . Then, the horizontal address conversion RAMS 814 and 816 each needs 10 bits since it counts up to 640 dots, while the vertical address conversior.
RAMs 807 and 815 each needs 9 bits since it counts up to 400 lines. In the illustrative embodiment, each of the horizontal and vertical address conversion RAMs is provided with an additional bit indicative of the display timing of a particular image. When the additional bits of the associated RAMs both are 1, image data is applied to the display; when either one of them is 0, the output of image data is inhibited. For this purpose, the analog switches 811 and 819 are respectively connected to the image data outputs of the video memories 810 and 818 and have their outputs commonly connected to the display.
FIGS. 9A and 9B show respectively the additional bits for implementing the above-stated control and specific images appearing on a screen 900. At the timing for horizontal and vertical display, 1 is written to the additional bits I and II of the first horizontal and vertical address conversion RAMs 806 and 807 and to the additional bits III and IY of the second horizontal and vertical address conversion RAMs 814 and 815; at the other timings, 0 is written to the additional bits I-IV. In the specific condition shown in FIGS. 9A and 9B, "00110000" is written to the additional bit I of the RAM 806, "00001100 " is written to the additional bit II of the RAM 807, "00000110 " is written to the additional bit III of th RAM 14, and "00110000 " is written to the additional bit IV of the RAM 815. When the additional bits I and II of the RAMs 806 and 807 both are 1, the analog switch 811 is turned on to deliver video data from the video memory 810 to the display with the result that a first image 901 appears on the display. When the additional addresses III and IV of the RAMs 814 and 815 both are 1, the analog switch 819 is turned on to deliver video data from the video memory 818 to the display with the result that a second image 902 appears on the display.
In the manner described above, the first and second images 900 and 901 appear on the screen 900 at the same time.
In summary, the multi-display system 900 described above assigns an additional bit representative of an image display timing to each of conversion table data stored in horizontal and vertical address conversion RAMs which are connected to particular one of a plurality of video memories, 5 thereby controlling the output timing of image data. The system 9 0 O, therefore, allows video data from a plurality of video memories to be displayed in combination on a single screen, as desired.
- Various modifications will become possible for those 10 skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
BACKGROUND OF THE IN~rENTION
The present invention relates to an image display system and, more particularly, to an image display system capable of moving, enlarging, reducing or otherwise manipulating an image S being displayed on a display.
An conventional image display system of the type described has a display clock generator, a display address counter, an address bus switch, a display address conversion RAM lRandom Access Memory), a memory address switch, a 10 video memory, a digital-to-analog (r~A) converter, and a microprocessor. The display clock generator generates a display ciock ha~ing a predetermined period. When data is to be read out of the video memory, the display address counter outputs a display address by counting the display clock in response to a 15 command from the microprocessor. The display address is applied to the address input of the conversion RAM via the address bus switch. The conversion RAM converts the input display address on the basis of data stored therein and feeds out the converted display address to a data line. The converted 20 display address is delivered to the address terminal of the video memory with the result that image data designated by the display address is read out. The DA converter converts the image data to a video signal.
To change the position or the size of an image being 5 displayed, the microprocessor is used to switch the display address switch and memory address switch such that the address bus and data bus of the conversion RAM are connected to those of the microprocessor. After the microprocessor has changed the data stored in the RAM, the switches are restored to their 10 original states so as to display the manipulated image. This kind of technology for reading data out of a video memory by address conversion is disclosed in, for example, "A Raster Assembly Processor (RAP) for Integrated HDTV Display of Video data and Image windows," IEEE 1987, pp. 731-739.
The problem with the conventional system is that the conversion RAM has to convert all of the display addresses sequentially generated by the display address couriter znd, therefore, needs an extremely great capacity. For example, when the display has a resolution of 640 dots (horizontal) x 400 20 lines (vertical), a conversion RAM whose capacity is as great as 4, 6 0 8, 0 0 0 bits is needed.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to 2 5 provide an image display system which noticeably reduces the required capacity an address conversion RAM.
- ~ It is another obiect of the present invention to provide a generally improved image display system.
An image display system of the present invention 5 comprises a horizontal display address counter for outputting a horizontal display address in response to a display clock, a vertical display address counter for outputting a vertical display address in response to the display clock, a horizontal display address conversion memory having an address input to which the 10 horizontal display address is connected, a vertical display address conversion memory having an address input to which the vertical display address is connected, a video memory having address inputs to which a data bus from the horizontal display address conversion memory and a data bus from the vertical 15 display address conversion memory are connected, the video memory outputting video data on the basis of the input addresses, and a rewriting circuit for rewriting data stored in the horizontal and vertical display address conversion memories.
BRIEF DESCRIPTION OF T~IE DRAWINGS
The above and other obiects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
2 5 FIG. 1 is a bloclc diagram schematically showing a 205~ 1 79 conventional image display system;
FIG. 2 is a block diagram schematically showing an image display system embodying the present invention;
FIG 3 is a memory map representative of a video 5 memory included in the embodiment;
FIGS. 4A and 4B are memorY maps representative of, respectively, a horizontal and a vertical display address conversion RA M also included in the embodiment;
FIG. 5 is a memory map indicative of a specific condition 10 wherein data stored in the vertical display address conversion R A M is manipulated;
FIG 6 shows table data to be written to the horizontal and vertical conversion RA Ms for doubling the size of an image;
FIG 7 shows a relation between the video memory and a 15 display in the condition shown in FIG. 6;
FIG. 8 is a block diagram schematically showing an alternative e~bodiment of the present invention; and FIGS. 9A and ~B show additional bis and a specific condition of a screen.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
To better understand the present invention, a brief reference will be made to a prior art image display system, shown in FIG 1. As shown, the convenional image display system, generally 10 0, has a display clock generator 101, a display address counter 10 2, an address bus switch 10 3, a display address conversion RAM 104, a memory address switch 10 5, a video memory 10 6, a DA converter 10 7, and a microprocessor 108. The display clock generator 101 generates a display clock having a predetermined period. When data is to be read out of the video memory 10 6, the microprocessor 10 8 causes the display address counter 102 to count the display clock to thereby generate a display address. The display address is applied to the address terminal of the RAM 104 via the address bus switch 103. In response, the RAM 104 converts the display address on the basis of data stored therein and feeds the resulting converted address to the address terminal of the v}deo memory 10 6 via the memory address switch 10 5 . On receiving the display address, the video memory 106 outputs video data.
The DA converter 107 converts the video data fed thereto from the video memory 106 to a video signa;. To change the position or the size of an image being displayed, the microprocessor 108 is used to switch the display address switch 10 3 and memory address switch 10 5 such that the address bus and data bus of the RAM 104 are connected to those of the microprocessor 108.
After the microprocessor 108 has changed the data stored in the RAM 104, the switches 103 and 105 are restored to their original states so as to display an image.
- The conventional system 10 0 has a draback that the 5 address conversion RAM has to convert all of the display addresses sequentially generated by the display address counter 102 and, therefore, needs an extremely great capacity, as discussed earlier.
Referring to FIG. 2, an image display system embodying 10 the present invention is shown and generally designated by the reference numeral 200. As shown, the system 200 has a disp;ay clock generator 201 for generating a display clock. A horizontal display address counter 202 counts the display clock while sequentially outputting horizontal display addresses. A vertical 15 display address counter 203 is incremented every time it receives m clock pulses from the horizontal clock generator 201 (m being the number of addresses in the horizontal direction), while outputting the resulting count as a vertical display address. A
horizontal address bus switch 20 4 selects either one of an address bus extending from the horizontal display address counter 202 and an address bus extending from a microprocessor 212 which will be described. A vertical address bus switch 20 5 selects either one of an address bus extending from the vertical address counter 203 and the address bus 2 5 extending from the microprocessor 212. A horizontal display address conversion RAM 206 has an address input to which the horizontal display address is connected. A vertical display address conversion RAM 207 has an address input to which the vertical display address is connected. The reference numeral 5 210 designates a video memory. A horizontal memory address switch 208 is connected to the horizontal display address conversion RAM 206 for selecting either one of a data bus terminating at the video memory 210 and a data bus terminating - at the microprocessor 212. A vertical memory address switch 10 209 selects either one of a data bus terminating at the video memory 210 and the data bus terminating at the microprocessor 212. A DA converter 211 converts video data read out of the video memory 210 to a video signal and feeds it to a conventional display 214. The microprocessor 212 controls the states of the switches 204, 205, 208 and 209 and rewrites the data stored in the RAMs 206 and 207. The reference numeral 213 designates an image processing circuit.
The image processing circuit 213 sequentially writes the first to n-th lines of video data in the video memory 210 pixel by 20 pixel. Specifically, the circuit 213 processes TV (Television) video data in a predetermined manner to generate video data pixel by pixel and generates horizontal and vertical addresses representative of particular horizontal and vertical writing positions of the video memory 210 at the same time, thereby 25 writing the image data in such addresses. The display 214 displays the image data stored in the video memory 10 line by line in synchronism with a horizontal scanning signal. The switches 204, 205, 20 ~ and 209 play the role of rewriting means in combination.
In the embodiment, the resolution is assumed to be 640 dots in the horizontal direction of the display 214 and 400 lines in the vertical direction. Hence, the horizontal and vertical display addresses require 10 bits and 9 bits, respectively.
FIG. 3 is a memory map representative of the video memory 210. In the figure, image data A on the second line is designated by an address "0000000001000000001". FIGS. 4A
and 4B are memory maps representative of the RAMs 206 and 207, respectively.
In operation, the display clock generator 201 feeds a display dot clock to the horizontal display address counter 202 and vertical display address counter 203. The horizontal display address counter 2 û 2 starts counting the input clock In response to a start signal a from the microprocessor 212. The counter 202 repetitively counts the display addresses 0-639 of dots in the horizontal direction in synchronism with the horizontal scanning period of the display 14, while delivering the count to the 10-bit horizontal display address bus. The horizontal address bus switch 204 has a first input connected to the display address bus from the address counter 202 and a second input connected to the address bus from the microprocessor 212. The switch 204, 20~ ~ 79 g therefore, selects either one of the address buses connected to the first and second inputs thereof and connects it to the address terminal of the horizontal address conversion RAM 206.
During an image display period, the horizontal address 5 bus switch 204 is connected to the horizontal address counter 2 0 2 . In this condition, display addresses synchronous to the clock signal from the display clock generator 2 01 are sequentially inputted to the horizontal address conversion RAM
2 0 6, whereby data are sequentially read out of the RAM 2 0 6 .
The data from the RAM 206 has a 10-bit bus width and is applied to the horizontal memory address switch 208. This switch 208 delivers the input 1 0-bit data to the lower 1 0-bit data bus of the video memory 210. The video data in the horizontal direction are sequentially read out as designated by 15 the addresses which are fed to the lower address of the video memory 210.
Regarding the display in the vertical direction, the vertical address counter 203 counts the addresses 0-399 of the display lines while delivering the count to the 9-bit vertical 2 0 display address bus. During an image display period, the vertical display address from the address counter 203 is applied to the vertical address conversion RAM 2 0 7 via the vertical address bus switch 205. As a result, 9-bit data is read out of the RAM 207 as designated by the input address and then routed 2 5 through the switch 2 0 9 to the upper address bus of the video ~0.~79 --1 o--- memory.
The above-stated display in the horizontal and vertical directions is effected according to the sc~nning on the screen of the display 214. Consequently, video data are sequentially read 5 out of the video memory 10, converted to an analog video data by the DA converter 211, and then fed to the display 214.
The display addresses inputted to the video memory 10 are the data having been read out of the horizontal and vertical address conversion RAMs 206 and 207. Therefore, the 10 horizontal and vertical addresses in the video memory 210 can be changed if the data in the RAMs 206 and 207 are rewritten.
This allows an image being displayed to be moved in the horizontal and vertical directions, enlarged, reduced, or otherwise modified. It should be noted that the system 200 can 15 move an image only on the column or line basis of the video memory 210.
To rewrite the data stored in the conversion RAMs 206 and 207, the microprocessor 212 causes the horizontal and vertical address bus switches 204 and 205 to connect the address 20 bus of the microprocessor 212 to the address buses of the RAMs 206 and 207. Also, the microprocessor 212 causes the horizontal and vertical memory address switches 208 and 209 to connect the data bus of the microprocessor 212 to the data buses of the RAMs 206 and 207. In this condition, the microprocessor 212 rewrites the data stored in the RAMs 206 and 207.
Thereafter, the microprocessor 212 again connects the switches 204 and 205 to the address counters 202 and 203 and the switches 208 and 209 to the address buses of the video memory 210. In the illustrative embodiment, the switches 204, 205, 208 and 209 may each be implemented as a switch or a gate, as desired.
FIG. 5 shows a specific condition wherein the the second and 640-th line of the vertical address conversion RAM 207 are replaced with each other. In this case, all that is required is to substitute the data at the addresses 000000001 and 101111111 of the RAM 207 for each other. The data stored in the other RAM 206 remain in the same condition shown in FIG. 4A.
As shown in FIG 6, when it is desired to double the size of an image, table data are written to the horizontal conversion RAM 206, as follows:
(address: data~ = (O O OH: O O G H~ , (O O 1 H: O O O H) , (002H: 001H), (003H: OOlH), . . . , (27 FH : 13 FH) As a result, the display addresses in the horizontal direction are sequentially incremented by 1 (one) for 2 dots, as shown in FIG. 7. The image is, therefore, doubled in size in the horizontal direction. Likewise, table data are written to the vertical address conversion RAM 207, as follows:
(address: data) = (O O O H: O O O H) , (O O l H: O O O H) , (002H: OOlH), (003H: OOlH), . . ., (18FH: OC7H) 5 Then, as shown in FIG. 7, the display addresses in the vertical direction are sequentially incremented by 1 for 2 lines, doubling the image size in the vertical direction.
To halve the image size, table data are written to the - RAMS 207 and 207, as shown below:
RAM 206: (address : data) = (OOOH : OOOH), (OOlH: 002H), (002H: 004H), (003H: 006H), . . . , (27FH: 4FEH) RAM 207: (address : data) = (OOOH : OOOH), (001H : 002H), (002H: 004H), (003H: 006H), ... (18FH: 31EH) In this case, the horizontal and vertical display addresses are sequentially incremented by 2 for one 1 dot each. As a result, the horizontal and vertical addresses and, therefore, the image 25 size is halved.
By the procedure described above, an image being displayed on the display 214 can be moved in the horizontal and vertical directions, enlarged, reduced, or otherwise manipulated, as desired.
The display 214 has a resolution which is 640 dots in the horizontal direction and 400 lines in the vertical direction (see FIG. 7), as stated earlier. The horizontal and vertical display addresses, therefore, need 10 bits and 9 bits, respectively. It follows that the RAMs 206 and 207 need respectively only the capacity of 640 x 10 = 6,400 bits and the capacity of 400 x 9 = 3,600 bits, i. e., the total capacity is only 10,000 bits which is far smaller than the conventional capacity which is 4,608,000 bits.
As stated above, the image display system 200 divides display addresses in the horizontal and vertical directions, connects a horizontal and a vertical address conversion RAM to display address buses, and converts the display addresses i~n the horizontal and vertical directions. The system 200, therefore, can shift, enlarge, reduce or otherwise modify an image while noticeably reducing the required capacity of the RAMSs.
The system 200 described above changes the display addresses by use of a single video memory to thereby change a particular condition of a single image such as the position or the size. Hence, the system 200 is not practicable with two or more images.
20~2 1 79 Referring to FIG. 8, an alternative embodiment of the present invention will be described which is capable of handling two different images at the same time. As shown, the image display system or multi-display system, generally 800, has a display clock generator 801. A horizontal and a vertical address counter 802 and 803 each receives the display clock and outputs a horizontal or vertical display address. A first and a second horizontal display address conversion RAM 806 and 814 each has an address input to which the horizontal display address is connected. A first and a second vertical display conversion RAM
807 and 815 each has an address input to which the vertical display address is connected. A first and a second video memory 810 and 818 are connected at the lower side of the address inputs thereof to the data buses of the horizontal address conversion RAMs 806 and 814, respectively, and at the upper side of the same to the data buses of the vertical address converâioil RAMs 807 and 815, respectively. These video memories 810 and 818 deliver video data to the associated data buses. A controller 820 rewrites data stored in the RAMs 806, 807, 814 and 815, as needed. A first and a second address switch 804 and 812 are respectively connected to the RAMs 906 and 814, and each selects either one of the address bus extending from the horizontal display address counter 802 and the address bus extending from the controller 820. A first and a second address bus switch 805 and 813 are respectively `- 2052 1 79 connected to the RAMs 807 and 815, and each selects either one of the address bus extending from the controller 820 and the address bus extending from the vertical display address counter 803. A first and a second data bus switch 808 and 816 are respectively connected to the RAMs 806 and 814, and each selects either one of the data bus to the video memory 810 or 818 and the data bus to the controller 820. A first and a second data bus switch 809 and 817 are respectively connected to the RAMs 807 and 815, and each selects either one of the data bus to the video memory 810 or 818 and the data bus to the controller 820. An AND gate 821 produces AND of additional bits provided in conversion table data of the RAMs 806 and 807, as will be described. A second AND gate 822 ANDs the additional bits provided in the conversion table data of the RAMS 814 and 815. A first and a second analog switch 811 and 819 are turned on and off by the AND gates 821 and 822, respectively. The additional bits are added to the uppermost bits of the horizonta;
and vertical display addresses. Therefore, the inputs of the AND
gates 821 and 822 are connected to the uppermost bits of the address buses.
In operation, the horizontal and vertical address counters 820 and 808 each generates a horizontal or vertical display address in response to the display clock from the clock generator 801. The horizontal and vertical display addresses are respectively routed through the first horizontal and vertical address bus switches 804 and 805 and the second horizontal and vertical address bus switches 812 and 813 to the fist horizontal and vertical address conversion RAMs 806 and 807 and the second horizontal and vertical address conversion RAMs 814 and 815. In response, the RAMs 806 and 807 and the RAMs 814 and 815 convert the input display addresses on the basis of data stored therein. The resulting outputs of the RAMs 806, 807, 814 and 815 are respectively routed through the associated data bus switches 808, 809, 816 and 817 to the lower and upper addresses of the first video memory 810 and the lower and upper addresses of the second video memory 818. As a result, video data are fed from the video memories 810 and 818 to a display, not shown.
Assume that the resolution of the display is 640 dots ~horizontal) x 400 lines (vertical) . Then, the horizontal address conversion RAMS 814 and 816 each needs 10 bits since it counts up to 640 dots, while the vertical address conversior.
RAMs 807 and 815 each needs 9 bits since it counts up to 400 lines. In the illustrative embodiment, each of the horizontal and vertical address conversion RAMs is provided with an additional bit indicative of the display timing of a particular image. When the additional bits of the associated RAMs both are 1, image data is applied to the display; when either one of them is 0, the output of image data is inhibited. For this purpose, the analog switches 811 and 819 are respectively connected to the image data outputs of the video memories 810 and 818 and have their outputs commonly connected to the display.
FIGS. 9A and 9B show respectively the additional bits for implementing the above-stated control and specific images appearing on a screen 900. At the timing for horizontal and vertical display, 1 is written to the additional bits I and II of the first horizontal and vertical address conversion RAMs 806 and 807 and to the additional bits III and IY of the second horizontal and vertical address conversion RAMs 814 and 815; at the other timings, 0 is written to the additional bits I-IV. In the specific condition shown in FIGS. 9A and 9B, "00110000" is written to the additional bit I of the RAM 806, "00001100 " is written to the additional bit II of the RAM 807, "00000110 " is written to the additional bit III of th RAM 14, and "00110000 " is written to the additional bit IV of the RAM 815. When the additional bits I and II of the RAMs 806 and 807 both are 1, the analog switch 811 is turned on to deliver video data from the video memory 810 to the display with the result that a first image 901 appears on the display. When the additional addresses III and IV of the RAMs 814 and 815 both are 1, the analog switch 819 is turned on to deliver video data from the video memory 818 to the display with the result that a second image 902 appears on the display.
In the manner described above, the first and second images 900 and 901 appear on the screen 900 at the same time.
In summary, the multi-display system 900 described above assigns an additional bit representative of an image display timing to each of conversion table data stored in horizontal and vertical address conversion RAMs which are connected to particular one of a plurality of video memories, 5 thereby controlling the output timing of image data. The system 9 0 O, therefore, allows video data from a plurality of video memories to be displayed in combination on a single screen, as desired.
- Various modifications will become possible for those 10 skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
Claims (3)
1. An image display system comprising:
a horizontal display address counter for outputting a horizontal display address in response to a display clock;
a vertical display address counter for outputting a vertical display address in response to said display clock;
a horizontal display address conversion memory having an address input to which said horizontal display address is connected;
a vertical display address conversion memory having an address input to which said vertical display address is connected;
a video memory having address inputs to which a data bus from said horizontal display address conversion memory and a data bus from said vertical display address conversion memory are connected, said video memory outputting video data on the basis of the input addresses; and rewriting means for rewriting data stored in said horizontal and vertical display address conversion memories.
a horizontal display address counter for outputting a horizontal display address in response to a display clock;
a vertical display address counter for outputting a vertical display address in response to said display clock;
a horizontal display address conversion memory having an address input to which said horizontal display address is connected;
a vertical display address conversion memory having an address input to which said vertical display address is connected;
a video memory having address inputs to which a data bus from said horizontal display address conversion memory and a data bus from said vertical display address conversion memory are connected, said video memory outputting video data on the basis of the input addresses; and rewriting means for rewriting data stored in said horizontal and vertical display address conversion memories.
2. A system as claimed in claim 1, wherein said rewriting means comprises:
a microprocessor;
a horizontal display address bus switch for selecting either one of an address bus from said horizontal display address counter and an address bus from said microprocessor;
a vertical display address bus switch for selecting either one of an address bus from said vertical display address counter and the address bus from said microprocessor;
a horizontal memory address switch connected to said horizontal display address conversion memory for selecting either one of a data bus to said video memory and a data bus to said microprocessor; and a vertical memory address switch connected to said vertical display address conversion memory for selecting either one of a data bus to said video memory and said data bus to said microprocessor.
a microprocessor;
a horizontal display address bus switch for selecting either one of an address bus from said horizontal display address counter and an address bus from said microprocessor;
a vertical display address bus switch for selecting either one of an address bus from said vertical display address counter and the address bus from said microprocessor;
a horizontal memory address switch connected to said horizontal display address conversion memory for selecting either one of a data bus to said video memory and a data bus to said microprocessor; and a vertical memory address switch connected to said vertical display address conversion memory for selecting either one of a data bus to said video memory and said data bus to said microprocessor.
3. A system as claimed in claim 2, wherein said microprocessor controls said horizontal display address bus switch, said vertical display address bus switch, said horizontal memory address switch, and said vertical memory address switch and rewrites data stored in said horizontal display address conversion memory and data stored in said vertical display address conversion memory.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2254895A JPH04132480A (en) | 1990-09-25 | 1990-09-25 | Picture display system |
| JP2-254895 | 1990-09-25 | ||
| JP2-279919 | 1990-10-18 | ||
| JP27991990A JP2626232B2 (en) | 1990-10-18 | 1990-10-18 | Image multi display method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2052179A1 CA2052179A1 (en) | 1992-03-26 |
| CA2052179C true CA2052179C (en) | 1996-01-16 |
Family
ID=26541899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA 2052179 Expired - Fee Related CA2052179C (en) | 1990-09-25 | 1991-09-24 | Image display system |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0477843B1 (en) |
| CA (1) | CA2052179C (en) |
| DE (1) | DE69120755T2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB9424809D0 (en) * | 1994-12-08 | 1995-02-08 | Philips Electronics Uk Ltd | Variable display rate image coding |
| JP3377667B2 (en) * | 1995-12-25 | 2003-02-17 | 株式会社日立製作所 | Image display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4309700A (en) * | 1980-05-22 | 1982-01-05 | Technology Marketing, Inc. | Cathode ray tube controller |
| DE3381991D1 (en) * | 1982-06-28 | 1990-12-20 | Toshiba Kawasaki Kk | IMAGE DISPLAY CONTROL DEVICE. |
-
1991
- 1991-09-24 CA CA 2052179 patent/CA2052179C/en not_active Expired - Fee Related
- 1991-09-24 DE DE1991620755 patent/DE69120755T2/en not_active Expired - Fee Related
- 1991-09-24 EP EP91116212A patent/EP0477843B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69120755D1 (en) | 1996-08-14 |
| DE69120755T2 (en) | 1996-11-07 |
| EP0477843B1 (en) | 1996-07-10 |
| EP0477843A3 (en) | 1993-01-27 |
| CA2052179A1 (en) | 1992-03-26 |
| EP0477843A2 (en) | 1992-04-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4197590A (en) | Method for dynamically viewing image elements stored in a random access memory array | |
| US4070710A (en) | Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array | |
| USRE31200E (en) | Raster scan display apparatus for dynamically viewing image elements stored in a random access memory array | |
| EP0744731B1 (en) | Method and apparatus for synchronizing video and graphics data in a multimedia display system including a shared frame buffer | |
| US4367466A (en) | Display control apparatus of scanning type display | |
| JPH0557599B2 (en) | ||
| US4922238A (en) | Method and system for smooth scrolling of a displayed image on a display screen | |
| US5268682A (en) | Resolution independent raster display system | |
| EP0237706A2 (en) | Electrical display system | |
| US4716460A (en) | Display refresh memory apparatus utilizing one half frame updating | |
| EP0139095A2 (en) | Display selection in a raster scan display system | |
| US6141055A (en) | Method and apparatus for reducing video data memory in converting VGA signals to TV signals | |
| JP2629268B2 (en) | Teletext broadcast receiver | |
| EP0525986A2 (en) | Apparatus for fast copying between frame buffers in a double buffered output display system | |
| CA2052179C (en) | Image display system | |
| US4642626A (en) | Graphic display scan line blanking capability | |
| JPH0426273B2 (en) | ||
| US4754331A (en) | Digitizer for an image processing system | |
| EP0422300B1 (en) | Display system with graphics cursor | |
| JP2591064B2 (en) | Teletext broadcast receiver | |
| US6008782A (en) | Mapping apparatus for use with a cathode-ray tube controller for generating special screen effects | |
| JPS6228473B2 (en) | ||
| JPS60170894A (en) | Image display unit | |
| JPH02137070A (en) | Image processing device | |
| JP2506960B2 (en) | Display controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |