CA2045705A1 - In-register data manipulation in reduced instruction set processor - Google Patents

In-register data manipulation in reduced instruction set processor

Info

Publication number
CA2045705A1
CA2045705A1 CA002045705A CA2045705A CA2045705A1 CA 2045705 A1 CA2045705 A1 CA 2045705A1 CA 002045705 A CA002045705 A CA 002045705A CA 2045705 A CA2045705 A CA 2045705A CA 2045705 A1 CA2045705 A1 CA 2045705A1
Authority
CA
Canada
Prior art keywords
byte
register
address
unaligned
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002045705A
Other languages
English (en)
French (fr)
Inventor
Richard Lee Sites
Richard T. Witek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2045705A1 publication Critical patent/CA2045705A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3816—Instruction alignment, e.g. cache line crossing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
CA002045705A 1990-06-29 1991-06-26 In-register data manipulation in reduced instruction set processor Abandoned CA2045705A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54761990A 1990-06-29 1990-06-29
US07/547,619 1990-06-29

Publications (1)

Publication Number Publication Date
CA2045705A1 true CA2045705A1 (en) 1991-12-30

Family

ID=24185411

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002045705A Abandoned CA2045705A1 (en) 1990-06-29 1991-06-26 In-register data manipulation in reduced instruction set processor

Country Status (7)

Country Link
US (2) US5367705A (OSRAM)
EP (1) EP0465322B1 (OSRAM)
JP (1) JP3105960B2 (OSRAM)
KR (1) KR100231380B1 (OSRAM)
CA (1) CA2045705A1 (OSRAM)
DE (1) DE69131637T2 (OSRAM)
TW (1) TW285729B (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5664224A (en) * 1993-07-23 1997-09-02 Escom Ag Apparatus for selectively loading data blocks from CD-ROM disks to buffer segments using DMA operations
DE4334294C1 (de) * 1993-10-08 1995-04-20 Ibm Prozessor für Zeichenketten variabler Länge
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
SG48907A1 (en) * 1993-12-01 1998-05-18 Intel Corp Exception handling in a processor that performs speculative out-of-order instruction execution
US5802341A (en) * 1993-12-13 1998-09-01 Cray Research, Inc. Method for the dynamic allocation of page sizes in virtual memory
US5666507A (en) * 1993-12-29 1997-09-09 Unisys Corporation Pipelined microinstruction apparatus and methods with branch prediction and speculative state changing
US6003120A (en) * 1993-12-30 1999-12-14 Intel Corporation Method and apparatus for performing variable length processor write cycles
US5655132A (en) * 1994-08-08 1997-08-05 Rockwell International Corporation Register file with multi-tasking support
JP3452989B2 (ja) * 1994-09-26 2003-10-06 三菱電機株式会社 中央処理装置
US7301541B2 (en) * 1995-08-16 2007-11-27 Microunity Systems Engineering, Inc. Programmable processor and method with wide operations
US6295599B1 (en) * 1995-08-16 2001-09-25 Microunity Systems Engineering System and method for providing a wide operand architecture
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5953241A (en) * 1995-08-16 1999-09-14 Microunity Engeering Systems, Inc. Multiplier array processing system with enhanced utilization at lower precision for group multiply and sum instruction
US5701442A (en) * 1995-09-19 1997-12-23 Intel Corporation Method of modifying an instruction set architecture of a computer processor to maintain backward compatibility
US5745375A (en) * 1995-09-29 1998-04-28 Intel Corporation Apparatus and method for controlling power usage
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
EP0870226B1 (en) * 1995-10-06 2003-05-21 Patriot Scientific Corporation Risc microprocessor architecture
US5764959A (en) * 1995-12-20 1998-06-09 Intel Corporation Adaptive 128-bit floating point load and store instructions for quad-precision compatibility
US5889984A (en) * 1996-08-19 1999-03-30 Intel Corporation Floating point and integer condition compatibility for conditional branches and conditional moves
US6052753A (en) * 1997-01-21 2000-04-18 Alliedsignal Inc. Fault tolerant data bus
US5878252A (en) * 1997-06-27 1999-03-02 Sun Microsystems, Inc. Microprocessor configured to generate help instructions for performing data cache fills
US6016532A (en) * 1997-06-27 2000-01-18 Sun Microsystems, Inc. Method for handling data cache misses using help instructions
EP0951671A1 (en) * 1997-08-18 1999-10-27 Koninklijke Philips Electronics N.V. Data processing device with relative jump instruction
US6260137B1 (en) * 1997-09-12 2001-07-10 Siemens Aktiengesellschaft Data processing unit with digital signal processing capabilities
US6898700B2 (en) * 1998-03-31 2005-05-24 Intel Corporation Efficient saving and restoring state in task switching
US7206877B1 (en) 1998-12-22 2007-04-17 Honeywell International Inc. Fault tolerant data communication network
JP3444346B2 (ja) * 1999-01-04 2003-09-08 日本電気株式会社 仮想メモリ管理方式
KR20010018243A (ko) * 1999-08-18 2001-03-05 김영환 마이크로 프로세서의 레지스터 맵핑 방법
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6820195B1 (en) * 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
JP3776732B2 (ja) * 2001-02-02 2006-05-17 株式会社東芝 プロセッサ装置
US7051168B2 (en) * 2001-08-28 2006-05-23 International Business Machines Corporation Method and apparatus for aligning memory write data in a microprocessor
EP1449062B1 (en) * 2001-11-01 2018-05-16 Verisign, Inc. High speed non-concurrency controlled database
US7139904B2 (en) * 2002-03-01 2006-11-21 Gorman J Zachary Data byte insertion circuitry
TWI224735B (en) * 2002-10-25 2004-12-01 Via Tech Inc Method for storing and accessing data in random bit range between different platforms
US7212440B2 (en) * 2004-12-30 2007-05-01 Sandisk Corporation On-chip data grouping and alignment
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7243210B2 (en) * 2005-05-31 2007-07-10 Atmel Corporation Extracted-index addressing of byte-addressable memories
US20100332788A1 (en) * 2009-06-30 2010-12-30 Li Zhao Automatically using superpages for stack memory allocation
CN101697116B (zh) * 2009-10-27 2011-11-09 飞天诚信科技股份有限公司 数据变换方法及装置
US10474463B2 (en) 2011-12-23 2019-11-12 Intel Corporation Apparatus and method for down conversion of data types
US9990202B2 (en) * 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions
US20160179662A1 (en) * 2014-12-23 2016-06-23 David Pardo Keppel Instruction and logic for page table walk change-bits
US20170169132A1 (en) * 2015-12-15 2017-06-15 Analog Devices, Inc. Accelerated lookup table based function evaluation
US9922039B1 (en) * 2016-03-31 2018-03-20 EMC IP Holding Company LLC Techniques for mitigating effects of small unaligned writes
US10901940B2 (en) * 2016-04-02 2021-01-26 Intel Corporation Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width
CN119336824A (zh) 2023-07-20 2025-01-21 北京有竹居网络技术有限公司 数据处理方法及装置、电子设备、存储介质

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961170A (en) * 1971-04-22 1976-06-01 Ing. C. Olivetti & C., S.P.A. Fixed point to floating point conversion in an electronic computer
US3873976A (en) * 1973-07-30 1975-03-25 Burroughs Corp Memory access system
US3916388A (en) * 1974-05-30 1975-10-28 Ibm Shifting apparatus for automatic data alignment
US4085447A (en) * 1976-09-07 1978-04-18 Sperry Rand Corporation Right justified mask transfer apparatus
JPS5743239A (en) * 1980-08-27 1982-03-11 Hitachi Ltd Data processor
US4613935A (en) * 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit
US4569016A (en) * 1983-06-30 1986-02-04 International Business Machines Corporation Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
US4591982A (en) * 1983-08-29 1986-05-27 International Business Machines Corporation Storage selection override apparatus for a multimicroprocessor implemented data processing system
EP0187762A4 (en) * 1984-06-27 1987-10-19 Motorola Inc Method and apparatus for a bit field instruction.
US5034900A (en) * 1984-10-05 1991-07-23 Hitachi, Ltd. Method and apparatus for bit operational process
US4739471A (en) * 1985-06-28 1988-04-19 Hewlett-Packard Company Method and means for moving bytes in a reduced instruction set computer
DE3751503T2 (de) * 1986-03-26 1996-05-09 Hitachi Ltd Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen.
US4992934A (en) * 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
CA1327080C (en) * 1987-05-26 1994-02-15 Yoshiko Yamaguchi Reduced instruction set computer (risc) type microprocessor
DE3786080D1 (de) * 1987-08-20 1993-07-08 Ibm Speicherzugriffssteuerungsvorrichtung in einem gemischtdatenformatsystem.
US5019967A (en) * 1988-07-20 1991-05-28 Digital Equipment Corporation Pipeline bubble compression in a computer system
US4916654A (en) * 1988-09-06 1990-04-10 International Business Machines Corporation Method for transfer of data via a window buffer from a bit-planar memory to a selected position in a target memory
EP0363176B1 (en) * 1988-10-07 1996-02-14 International Business Machines Corporation Word organised data processors
US5051894A (en) * 1989-01-05 1991-09-24 Bull Hn Information Systems Inc. Apparatus and method for address translation of non-aligned double word virtual addresses
US5276891A (en) * 1990-01-11 1994-01-04 Bull Hn Information Systems Inc. Alignment of sign, data, edit byte operand results for storage in memory
US5093778A (en) * 1990-02-26 1992-03-03 Nexgen Microsystems Integrated single structure branch prediction cache

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8683182B2 (en) 1995-08-16 2014-03-25 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations
US8769248B2 (en) 1995-08-16 2014-07-01 Microunity Systems Engineering, Inc. System and apparatus for group floating-point inflate and deflate operations

Also Published As

Publication number Publication date
DE69131637D1 (de) 1999-10-28
EP0465322B1 (en) 1999-09-22
EP0465322A2 (en) 1992-01-08
EP0465322A3 (en) 1992-11-19
TW285729B (OSRAM) 1996-09-11
DE69131637T2 (de) 2000-06-08
KR920001320A (ko) 1992-01-30
JPH06119166A (ja) 1994-04-28
US5367705A (en) 1994-11-22
KR100231380B1 (ko) 1999-11-15
US5410682A (en) 1995-04-25
JP3105960B2 (ja) 2000-11-06

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Legal Events

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EEER Examination request
FZDE Discontinued